INTERNATIONAL CONFERENCE ON ADVANCES IN MULTI-DISCIPLINARY SCIENCES AND ENGINEERING RESEARCH: ICAMSER-2021
The present work analyses the fundamental transport property of photogenerated carriers named low... more The present work analyses the fundamental transport property of photogenerated carriers named low field mobility for Al 0.5 Ga 0.5 N/AlN/Sapphire-based MSM detector using five conventional mobility models. Using Atlas-Silvaco TCAD simulator, appropriate mobility models for differently doped structures were investigated for the least dark current density and improved photocurrent. For each doping case, low electric field mobility models have been compared for I-V characteristics, conduction current density, recombination rate, velocity and mobility of charge carriers. Since there are uncertainties for the most fundamental transport property like field-dependant mobility, therefore more study is required to model mobility for high performance of Wide Band Gap materials. In this work, the mobilities of carriers (mup and mun values) are not specified manually in the Silvaco simulation program however mobility model has been defined. The present work analyses various mobility models on dark current density, photocurrent, mobility and velocity of charge carriers in a photo-absorbent layer. Earlier experimental and theoretical studies have proved that variation in dark current density is greatly affected by doping concentration, structural dimension parameters and optical and electrical properties of detector's materials. The main objective of the present work is selecting the suitable mobility model to get high Conduction current density in light to Conduction current density in dark ratio for each doping case. We also found that selection of models has a significant impact on spectral response. This simulation work could help align theoretical performance with experimental data and utilising AlGaN MSM detectors in modern UV detection and low noise applications.
Journal on Today's Ideas - Tomorrow's Technologies, 2014
This paper represents fixed body biased CMOS Tapered Buffer which is designed to minimize the PDP... more This paper represents fixed body biased CMOS Tapered Buffer which is designed to minimize the PDP (Power Delay Product) of the circuit. CMOS Tapered Buffers are often used for driving large capacitive load at high speed. Since there are tradeoffs between performance parameters of Buffer for minimizing its PDP value and due to technology constraints on the threshold voltage of MOS; one can vary the Vth up to certain limit while keeping the V DD constant. The proposed work is helpful in designing power efficient CMOS Tapered Buffer. This is found that in proposed Buffer when Vth value for the first stage of inverter is taken between the range of (0.2V DD-0.4 V DD), its performance gets improved in terms of power dissipation. This analysis is verified by simulating the 2-stage Tapered buffer using standard 180nm CMOS technology in Cadence environment. Analysis performed on the schematic shows that FBB (Fixed Body Bias) Tapered Buffer reduces the average power dissipation across capacitive load by 77 % and static power has been reduced to 18.3% at very less penalty in delay. Hence the proposed approach is suitable in the design of low power buffer for increasing the current capability of logic gate at optimal speed.
This paper represents Fixed Body Biased CMOS
Tapered Buffer which is designed to minimize the ave... more This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay.
This paper represents fixed body biased CMOS Tapered Buffer which is designed to minimize the PDP... more This paper represents fixed body biased CMOS Tapered Buffer which is designed to minimize the PDP (Power Delay Product) of the circuit. CMOS Tapered Buffers are often used for driving large capacitive load at high speed. Since there are tradeoffs between performance parameters of Buffer for minimizing its PDP value and due to technology constraints on the threshold voltage of MOS; one can vary the Vth up to certain limit while keeping the VDD constant. The proposed work is helpful in designing power efficient CMOS Tapered Buffer. This is found that in proposed Buffer when Vth value for the first stage of inverter is taken between the range of (0.2VDD - 0.4 VDD), its performance gets improved in terms of power dissipation. This analysis is verified by simulating the 2-stage Tapered buffer using standard 180nm CMOS technology in Cadence environment. Analysis performed on the schematic shows that FBB (Fixed Body Bias) Tapered Buffer reduces the average power dissipation across capacitive load by 77 % and static power has been reduced to 18.3% at very less penalty in delay. Hence the proposed approach is suitable in the design of low power buffer for increasing the current capability of logic gate at optimal speed.
A CMOS Tapered buffer is used to increase the driving abillity of the logic circuitry whenever it... more A CMOS Tapered buffer is used to increase the driving abillity of the logic circuitry whenever it is connected with large capacitive load.The increasing width of each inverter in the chain of CMOS inverters is based on tapering factor.The scaling or tapering factor of each stage is dependant on technology used, driving load and the number of stages used.
INTERNATIONAL CONFERENCE ON ADVANCES IN MULTI-DISCIPLINARY SCIENCES AND ENGINEERING RESEARCH: ICAMSER-2021
The present work analyses the fundamental transport property of photogenerated carriers named low... more The present work analyses the fundamental transport property of photogenerated carriers named low field mobility for Al 0.5 Ga 0.5 N/AlN/Sapphire-based MSM detector using five conventional mobility models. Using Atlas-Silvaco TCAD simulator, appropriate mobility models for differently doped structures were investigated for the least dark current density and improved photocurrent. For each doping case, low electric field mobility models have been compared for I-V characteristics, conduction current density, recombination rate, velocity and mobility of charge carriers. Since there are uncertainties for the most fundamental transport property like field-dependant mobility, therefore more study is required to model mobility for high performance of Wide Band Gap materials. In this work, the mobilities of carriers (mup and mun values) are not specified manually in the Silvaco simulation program however mobility model has been defined. The present work analyses various mobility models on dark current density, photocurrent, mobility and velocity of charge carriers in a photo-absorbent layer. Earlier experimental and theoretical studies have proved that variation in dark current density is greatly affected by doping concentration, structural dimension parameters and optical and electrical properties of detector's materials. The main objective of the present work is selecting the suitable mobility model to get high Conduction current density in light to Conduction current density in dark ratio for each doping case. We also found that selection of models has a significant impact on spectral response. This simulation work could help align theoretical performance with experimental data and utilising AlGaN MSM detectors in modern UV detection and low noise applications.
Journal on Today's Ideas - Tomorrow's Technologies, 2014
This paper represents fixed body biased CMOS Tapered Buffer which is designed to minimize the PDP... more This paper represents fixed body biased CMOS Tapered Buffer which is designed to minimize the PDP (Power Delay Product) of the circuit. CMOS Tapered Buffers are often used for driving large capacitive load at high speed. Since there are tradeoffs between performance parameters of Buffer for minimizing its PDP value and due to technology constraints on the threshold voltage of MOS; one can vary the Vth up to certain limit while keeping the V DD constant. The proposed work is helpful in designing power efficient CMOS Tapered Buffer. This is found that in proposed Buffer when Vth value for the first stage of inverter is taken between the range of (0.2V DD-0.4 V DD), its performance gets improved in terms of power dissipation. This analysis is verified by simulating the 2-stage Tapered buffer using standard 180nm CMOS technology in Cadence environment. Analysis performed on the schematic shows that FBB (Fixed Body Bias) Tapered Buffer reduces the average power dissipation across capacitive load by 77 % and static power has been reduced to 18.3% at very less penalty in delay. Hence the proposed approach is suitable in the design of low power buffer for increasing the current capability of logic gate at optimal speed.
This paper represents Fixed Body Biased CMOS
Tapered Buffer which is designed to minimize the ave... more This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay.
This paper represents fixed body biased CMOS Tapered Buffer which is designed to minimize the PDP... more This paper represents fixed body biased CMOS Tapered Buffer which is designed to minimize the PDP (Power Delay Product) of the circuit. CMOS Tapered Buffers are often used for driving large capacitive load at high speed. Since there are tradeoffs between performance parameters of Buffer for minimizing its PDP value and due to technology constraints on the threshold voltage of MOS; one can vary the Vth up to certain limit while keeping the VDD constant. The proposed work is helpful in designing power efficient CMOS Tapered Buffer. This is found that in proposed Buffer when Vth value for the first stage of inverter is taken between the range of (0.2VDD - 0.4 VDD), its performance gets improved in terms of power dissipation. This analysis is verified by simulating the 2-stage Tapered buffer using standard 180nm CMOS technology in Cadence environment. Analysis performed on the schematic shows that FBB (Fixed Body Bias) Tapered Buffer reduces the average power dissipation across capacitive load by 77 % and static power has been reduced to 18.3% at very less penalty in delay. Hence the proposed approach is suitable in the design of low power buffer for increasing the current capability of logic gate at optimal speed.
A CMOS Tapered buffer is used to increase the driving abillity of the logic circuitry whenever it... more A CMOS Tapered buffer is used to increase the driving abillity of the logic circuitry whenever it is connected with large capacitive load.The increasing width of each inverter in the chain of CMOS inverters is based on tapering factor.The scaling or tapering factor of each stage is dependant on technology used, driving load and the number of stages used.
Uploads
Papers by harpreet Kaur
Tapered Buffer which is designed to minimize the average
power dissipation across large capacitive load. The
implementation of Reverse Body Bias (RBB) in the
proposed Buffer chain is to vary Vth value of NMOS in the
first stage. And with the increase in Vth /sub-threshold
leakage current and power has been reduced. The
technology constraints on the threshold voltage does not
allow designer to set high threshold voltage for MOS
devices. Hence, this was found that in proposed circuit that
when optimal Reverse Body Bias value is set within (0.2
VDD to 0.4 VDD) range, the average power dissipation
across capacitive load reduces to 82.2 % at very less
penalty in delay.
Tapered Buffer which is designed to minimize the average
power dissipation across large capacitive load. The
implementation of Reverse Body Bias (RBB) in the
proposed Buffer chain is to vary Vth value of NMOS in the
first stage. And with the increase in Vth /sub-threshold
leakage current and power has been reduced. The
technology constraints on the threshold voltage does not
allow designer to set high threshold voltage for MOS
devices. Hence, this was found that in proposed circuit that
when optimal Reverse Body Bias value is set within (0.2
VDD to 0.4 VDD) range, the average power dissipation
across capacitive load reduces to 82.2 % at very less
penalty in delay.