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    Peripheral Component Interconnect (Pci) Bus

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    Prince Thomas
    The document discusses the Peripheral Component Interconnect (PCI) bus. It describes PCI as a 32-bit, 33MHz parallel bus that was developed in 1992 to connect expansion boards, chips, and processor/memory subsystems. PCI improved on earlier buses by operating independently of the CPU speed and allowing full bus mastering for high bandwidth data transfers. Typical PCI cards connect via a 47-pin gold finger connector to the PCI slots on the motherboard. The document outlines the evolution from conventional PCI to PCI-X and PCI Express as data transfer needs increased over time.

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    Peripheral Component Interconnect (Pci) Bus

    Uploaded by

    Prince Thomas
    487 views19 pages
    The document discusses the Peripheral Component Interconnect (PCI) bus. It describes PCI as a 32-bit, 33MHz parallel bus that was developed in 1992 to connect expansion boards, chips, and processor/memory subsystems. PCI improved on earlier buses by operating independently of the CPU speed and allowing full bus mastering for high bandwidth data transfers. Typical PCI cards connect via a 47-pin gold finger connector to the PCI slots on the motherboard. The document outlines the evolution from conventional PCI to PCI-X and PCI Express as data transfer needs increased over time.

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    The document discusses the Peripheral Component Interconnect (PCI) bus. It describes PCI as a 32-bit, 33MHz parallel bus that was developed in 1992 to connect expansion boards, chips, and processor/memory subsystems. PCI improved on earlier buses by operating independently of the CPU speed and allowing full bus mastering for high bandwidth data transfers. Typical PCI cards connect via a 47-pin gold finger connector to the PCI slots on the motherboard. The document outlines the evolution from conventional PCI to PCI-X and PCI Express as data transfer needs increased over time.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    487 views19 pages

    Peripheral Component Interconnect (Pci) Bus

    Uploaded by

    Prince Thomas
    The document discusses the Peripheral Component Interconnect (PCI) bus. It describes PCI as a 32-bit, 33MHz parallel bus that was developed in 1992 to connect expansion boards, chips, and processor/memory subsystems. PCI improved on earlier buses by operating independently of the CPU speed and allowing full bus mastering for high bandwidth data transfers. Typical PCI cards connect via a 47-pin gold finger connector to the PCI slots on the motherboard. The document outlines the evolution from conventional PCI to PCI-X and PCI Express as data transfer needs increased over time.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 19

    PERIPHERAL COMPONENT INTERCONNECT (PCI) BUS

    NAVEENA JOHNSON Roll No:12 Mtech VLSIES

    What is a bus?

    Communication pathway connecting two or more devices Typical desktop PC has two main buses:

    1)System bus or Local bus - connects CPU and memory - fastest bus
    2)PCI bus -connects hard-disks , sound cards -slower bus
    2

    PCI BUS

    Parallel bus Developed by Intel in 1992

    Interconnects chips,expansion boards and processor memory subsystems


    5 volt, 33MHz, 32-bit bus with a basic data transfer rate of 133 Mb/s
    3

    Why PCI ?

    The original PC bus developed by IBM in 1982 was 16 bits wide and operated at 4.77 MHz This was known as ISA bus having datarate of 9Mbytes per sec! Gradually peripherals such as video cards and harddrives required a higher bandwidth It detached the speed of the peripheral bus from that of the memory Hence PCI devices can operate at their own independent speed
    4

    Dual Independent Bus (DIB)


    Backside Bus Frontside Bus PCI

    Direct access to system memory for connected devices Uses a bridge to connect to the frontside bus and therefore to the CPU
    5

    Real Motherboard

    PCI BUS Performance


    What makes the PCI bus one of the fastest I/O bus used today? Four features make this possible:

    Burst Mode: allows multiple sets of data to be sent. Full Bus Mastering: the ability of devices on the PCI bus to perform transfers directly. High Bandwidth : allows for increased speed of the PCI Plug and Play(PnP)
    7

    How a Device Works

    Example: PCI-based sound card


    The sound card will convert the analog signal to a digital signal. The digital audio data carried across the PCI bus to the bus controller, which determines which device on the PCI device has the priority to send data to the central processing unit (CPU) and whether the data will go directly to the CPU or to the system memory.

    3.

    1.

    2.

    4.

    If the sound card is in recording mode, the bus controller will assign a high priority to the data coming from the sound card. It will send the sound cards data over the bus bridge to the system bus. The system bus will save the data in system memory. When the recording is complete, then it will be up to the user to save the data from the sound card on either the hard drive, or will remain in memory for additional processing.
    8

    Typical PCI Card


    Connectors-Gold Fingers

    A typical PCI card

    PCI card 47 pins


    9

    PCI Slots in Motherboard

    10

    How to Install

    11

    PCI Technology

    Conventional PCI PCI-X PCI Express

    12

    Conventional PCI

    Plug-and-Play Functionality 32 bit and operates at 33 MHz PCI 2.1 supporting both 3.3V and 5V PCI 2.3 supporting only 3.3V

    13

    PCI-X

    Based on existing PCI architecture 64-Bit slots with support for 3.3V and Universal PCI PCI-X 1.0 has two speed grades:66MHz and 133MHz PCI-X 2.0 provides two additional speed grades : 266 MHz and 533 MHz

    14

    PCI-Express

    PCI bus with highest performance Serial connection switch that controls several point-topoint connections enable transfer rates of up to 2.5Gbits/second
    15

    Conclusion

    Due to the need for growing data transfer rates among IO devices, the original PCI Architecture has become outdated A new model of PCI, called PCI Express will replace the dated architecture giving it life for another decade
    16

    THANK YOU

    17

    Bus Arbitration

    Centralised Single hardware device controlling bus access Bus Controller Arbiter May be part of CPU or separate

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