Hazard and Glitches
Hazard and Glitches
Hazard and Glitches
change in response to an input change is the propagation delay. The time is mainly required to apply or drain voltages in the lower-level transistors. Timing diagrams are used to show delays.
Contd.
This example, for an inverter, shows how
signal values, on the vertical axis, change with time on the horizontal axis. becomes 0, and vice versa. changes
When the input becomes 1, the output There is a slight delay before the outputs
remain 1 if the inputs change from xyz = 111 to xyz = 110. But what really happens? There is a false error, and f becomes 0 temporarily! z and yz change right after z changes. But xz has notchanged yet, so f then (incorrectly) changes to 0. Only after xz changes does f go back to 1.
Contd.
Contd.
Part of the problem here is that there are
multiple paths from the inputs (z) to the outputs, and some paths are longer than others. It is called Hazard. Hazards can be very difficult to detect and prevent in general.
Contd.
GLITCHES
A GLITCH is the fast and small unwanted
Contd.
The glitch may occurs because the delay
paths through the circuit experience different propagation delays. The glitch may provides erroneous behavior of logic which has an asynchronous inputs. Usual solution to avoid any glitches is to use synchronous digital circuits and/or combinational hazard-free circuits.
GLITCHES
A HAZARD is a circuit (sub-circuit) which may
produce a glitch. Usually it happens when circuit has unbalanced propagation delay paths. There are four types of hazards:
Static-zero hazard: outgoing signal is static 0
and glitch 0>1>0 rises. Static-one hazard: outgoing signal is static 1 and glitch 1>0>1 falls. Dynamic hazard: double changing of signal, when it comes up. Dynamic hazard: double changing if signal, when it comes down.
program depends on conditions other than the inputs and the state In edge-triggered logic circuits, a momentary glitch resulting from a hazard can be converted into an erroneous output
prime implicants A Karnaugh map that contains adjacent, disjoint prime implicants is subject to a static 1 hazard Adjacent prime implicants: Only one variable needs to change value to move from one prime implicant to the other
Contd.
Disjoint prime implicants No prime implicant covers cells of both of the disjoint prime implicants Correspond to AND gates that must both change their outputs when a particular input is changed
X1 A B Y
Y
S B
A B
X2
Static-1 Hazard
A
A B
AND 2
Y X1 A B
OR 2
S B
BUFF
YS
DA
B
AND 2 A
Y X2
Glitch
S=0
0 S=1
Contd.
AB 00 0 01 1 11 1 10 0
S=0
S=1
The blue oval shows the redundant term used to cover the transition between product terms.
A B YS
AND 2
Y X1 A B C Y X2
OR 3
S B
D
A B A B
AND 2 A
AND 2
Y X3