Computer

Organization
And Architecture
DR. M. RAMPAVAN
Syllabu
s
 Text Books
1. Computer System Architecture - Morris Mano, Third
edition, Pearson publications.
2. Computer Organization - Carl Hamacher, Zvonko
Vranesic and Safwat Zaky, V Edition, McGraw-Hill
publications, Fifth Edition, Oxford University Press.

3. Computer Organization and Design: The

Hardware/Software interface, David A. Patterson and
John L. Hennessy, Elsevier.
Distribution of Marks (DOM)

 Continuous Evaluation

Test Conductin Convertin Final

Component g Marks g Marks Conversio
s n
Theory Mid Term 25 20 35
CLA-I 10 5
CLA-II 20 10
Practical Lab 50 15 15
Performanc
e
Total 50
Distribution of Marks (DOM)

 End Semester

Test Conducting Final

Components Marks Conversion
Theory Final Exam 50 35
Practical Project and 50 15
Lab
Performance
Total 50
Why
Computer Organization
And Architecture?
Importance of Studying Computer
Organization and Architecture
 Foundational Knowledge: It provides the fundamental principles of how
computers work, which is essential for all areas of computer science.
 Performance Optimization: Knowledge of hardware components and their
interactions helps in writing more efficient and optimized software.
 Troubleshooting and Debugging: Understanding the underlying architecture
aids in diagnosing and resolving hardware-related issues in software.
 Interdisciplinary Applications: It bridges the gap between hardware and
software, essential for fields like embedded systems, robotics, and IoT.
Pioneers of COA

Charles Babbage (1791-1871): Conceptualized the Analytical Engine, laying the

groundwork for modern computers with features like an arithmetic logic unit and memory.
Ada Lovelace (1815-1852): Regarded as the first computer programmer, she created
algorithms for Babbage's Analytical Engine.
John von Neumann (1903-1957): Proposed the von Neumann architecture, a stored-
program computer design that became foundational for most modern systems.
Alan Turing (1912-1954): Developed the Turing machine concept, formalizing
algorithms and computation, and helped break the Enigma code during WWII.
John Bardeen, Walter Brattain, and William Shockley: Invented the transistor in
1947, revolutionizing computer design by making computers smaller, faster, and more
reliable.
George Boole (1815-1864): Developed Boolean algebra, laying the mathematical
foundation for digital logic and circuit design used in computers.
Claude Shannon (1916-2001): Applied Boolean algebra to electrical circuits,
establishing digital circuit design principles and transforming electrical engineering and
computing.
Evolution of computers
Functional Units of Computer
 Program: The list of instructions that performs a task is called a program.
 Data: Numbers/Encoded characters that are used as operand by the
Instruction
 Object Program: Compiling a high level language Source program into a list
of machine Instruction Constituting a machine language program called object
program.
 The program is stored in the memory.
 The processor then fetches the instruction that makes up the program from
the memory one after another and performs the desire operations.
Input Unit: The input unit consists of input devices that are
attached to the computer. These devices take input and convert it
into binary language that the computer understands. Some of the
common input devices are keyboard, mouse, joystick, scanner etc.
Central Processing Unit (CPU): The CPU is called the brain of the
computer because it is the control center of the computer. It first
fetches instructions from memory or input device and then
computes them and finally, stores the output or displays on the
output device.
The CPU has three main components which are responsible for
different functions – Arithmetic Logic Unit (ALU), Control Unit (CU)
and Memory registers
Arithmetic and Logic Unit (ALU) : The ALU, as its name suggests performs
mathematical calculations and takes logical decisions. Arithmetic calculations include
addition, subtraction, multiplication and division. Logical decisions involve comparison
of two data items to see which one is larger or smaller or equal.

Control Unit : The Control unit coordinates and controls the data flow in and out of
CPU and also controls all the operations of ALU, memory registers and also
input/output units. It is also responsible for carrying out all the instructions stored in
the program. It decodes the fetched instruction, interprets it and sends control signals
to input/output devices until the required operation is done properly by ALU and
memory.
Memory Registers : A register is a temporary unit of memory in the CPU. These are used to
store the data which is directly used by the processor.

Registers can be of different sizes(16 bit, 32 bit, 64 bit and so on) and each register inside the CPU
has a specific function like storing data, storing an instruction, storing address of a location in
memory etc.
The user registers can be used by an assembly language programmer for storing operands,
intermediate results etc.

Accumulator (ACC) is the main register in the ALU and contains important operands of an
operation to be performed in the ALU.
MEMORY UNIT: It stores the programs and data.

There are 2 Primary

types of storage
classes Secondary

Primary Responsible for temporarily holding the data and instruction that CPU
Storage: needs to process

Memory in which any location can be reached in short and fixed amount
RAM: of time after specifying its address is called RAM.
Time required to access 1 word is called Memory Access Time.
The small, fast, RAM units are called Cache. They are tightly coupled with
Cache
processor and are often contained on the same integrated circuit chip to
Memory:
achieve high performance.

Main Memory: The largest and the slowest unit is called the main memory.

Secondary
Magnetic disks, optical disks are secondary storage devices
Storage:
Bus Structures
 The term "bus" refers to a communication system that allows various
components within a computer system to exchange data. It serves as a
pathway for information flow between the different parts of a computer,
enabling seamless communication and coordination.
 A “bus structure” refers to the arrangement and organization of buses
within a computer system. The bus structure defines how these buses are
interconnected and how they facilitate data transfer and control within the
system.
 There are many ways to connect different parts inside the computer
together. First way is Single Bus Structure and second is Multi-Bus
structure.
Functions of Bus Structure:
1. Data Transfer
2. Addressing
3. Control and Coordination
4. Peripheral Communication
Single Bus Structure:

 In this architecture, a single shared bus is used to connect

various hardware components like CPU, Memory I/O devices etc
within the computer system.
Common Bus System
Load (LD) − During the next clock pulse transition the information from the bus is transmitted to the
register whose load (LD) input is enabled.
Memory Unit − When the write input of the memory is activated, it holds the content of the bus.
When the read input is activated, the memory places the 16-bit output onto the bus.
Increment (INR) and Clear (CLR) − When the INR signal is enabled, the contents of the specified
register are incremented. The contents are cleared when the CLR signal is enabled.
Address Registers (AR) − The address of the memory for the next read and write operation is
determined. It receives or sends an address from or to the bus when selection inputs S 2S1 S0=001
is used and the load is enabled. With inputs INR and CLR, the address gets incremented or
cleared.
Program Counter (PC) − The address of the next instruction that is to be read from the memory
is saved. It receives or sends an address from or to the bus when selection inputs S 2S1 S0 = 010 is
applied and the load input is enabled. With inputs INR and CLR, the address gets incremented or
cleared.
Data Register (DR) − The data register includes the data to be written into memory or data that is
to be read from the memory. It receives or sends an address from or to the bus when selection
inputs are S2S1 S0 = 011 applied and the load input is enabled. With inputs INR and CLR, the
address gets incremented or cleared.
Accumulator (AC) − Accumulators are beneficial in executing the register micro-operations including
arithmetic, logical etc. The results acquired are again sent to the accumulator. An accumulator stores
the intermediate arithmetic and logic results. S2S1 S0 = 101
Instruction Registers (IR) − The IR stores the copy of the instruction that the processor has to
implement. The instruction that is read from the memory is stored in the IR. It receives or sends
instruction code from or to the bus when selection inputs S2S1 S0 = 111 are applied and the load input
is enabled.
Temporary Register (TR) − The temporary storage for variables or results is supported by the
temporary register. It receives or sends the temporary data from or to the bus when selection inputs
S2S1 S0 = 011 are applied and the load input is enabled. With inputs INR and CLR, the address gets
incremented or cleared.
Input Registers (INPR) − It includes 8 bits to hold the alphanumeric input information. Input device
shifts its serial data into the 8-bit register. The data is moved to AC via the adder/logic circuit with load
enabled. S2S1 S0 = 110
Output Registers (OUTPR) − The data is received from AC and moved to the output device.
Advantages of Single Bus Structure:
1. Simplicity: Single bus architectures are relatively simple to design and
implement, making them cost-effective for many applications.
2. Cost-Efficiency: The use of a single bus reduces the complexity and
cost of the hardware compared to more elaborate bus structures.
Disadvantages of Single Bus Structure:
3. Limited Bandwidth: A single bus structure can become a bottleneck in
terms of data transfer bandwidth, as all components share the same
bus. This can limit the overall performance of the system.
4. Scalability: As computer systems become more complex and require
higher bandwidth for data transfer, a single bus structure may struggle
to scale efficiently.
5. Contention: Contention for the bus can occur when multiple
components attempt to access it simultaneously, leading to delays and
potential performance issues.
Single bus architectures are commonly found in simple and cost-effective
computer systems, such as small embedded systems.
Multi-Bus Structure:

 Multi-bus structure is used to enhance the performance and

scalability of a computer system.
Data Bus:
 The data bus is responsible for transmitting data between the CPU,
memory, and input/output devices.
 It is bidirectional, allowing data to flow in both directions.
 The width of the data bus determines the amount of data that can be
transmitted simultaneously. For example, a 32-bit data bus can transmit 32
bits of data at a time.

Address Bus:
 The address bus carries information about the memory location or I/O port
where data needs to be read from or written to.
 Its width determines the maximum addressable memory space. A wider
address bus can access a larger memory.
Control Bus:
 The control bus carries control signals that coordinate and
regulate the activities of various components.
 Control signals include read and write signals, interrupt requests,
clock signals, and bus control signals.

System Bus:
 The system bus encompasses the data, address, and control
buses, providing a comprehensive communication pathway for
the entire system.
Advantages of Multi-Bus Structure:
1. Improved Performance: By segmenting the buses, a multi-bus
structure can increase the data transfer bandwidth and reduce
contention, improving overall system performance.
2. Scalability: Multi-bus architectures are more scalable than
single bus architectures. As the system’s complexity grows,
additional buses can be added to accommodate more devices
and higher data transfer rates.
3. Reduced Bus Contention: With dedicated buses for specific
purposes or peripheral devices, bus contention is minimized,
resulting in smoother and more efficient data transfers.
4. Specialized Communication: I/O buses allow for specialized
communication between the CPU and peripheral devices,
optimizing data exchange for specific tasks like graphics
rendering or data storage.
Disadvantages of Multi-Bus Structure:
1. Complexity: Multi-bus structures are more complex to design
and implement than single bus structures, which can increase
system cost and complexity.
2. Higher Hardware Costs: The use of multiple buses may require
additional hardware components, increasing the overall cost of
the computer system.
Multi-bus structures are often found in high-performance computing
systems, workstations, and servers.
 Fixed Point and Floating-Point Operation

 There are two major approaches to store real numbers

 These are (i) Fixed Point Notation and (ii) Floating Point Notation.
 In fixed point notation, there are a fixed number of digits after the decimal point,
whereas floating point number allows for a varying number of digits after the
decimal point.
Fixed-Point Representation
 For example, if given fixed-point representation is IIII.FFFF, then you can store
minimum value is 0000.0001 and maximum value is 9999.9999.
 There are three parts of a fixed-point number representation: the sign field, integer
field, and fractional field.
 2’s complementation representation is preferred in computer system because of
unambiguous property and easier for arithmetic operations.
 Assume number is using 32-bit format which reserve 1 bit for the sign, 15 bits
for the integer part and 16 bits for the fractional part.
 Then, -43.625 is represented as following:
 where, 0 is used to represent + and 1 is used to represent. 000000000101011 is
15 bit binary value for decimal 43 and 1010000000000000 is 16 bit binary value
for fractional 0.625.
To find the 1's and 2's complements of a decimal number like 2234.3144, you first need to
convert it into its binary representation. Then you can perform the complement operations.
Converting Decimal to Binary
1. Convert the integer part (2234) to binary:
 Divide 2234 by 2 and keep track of the remainders:
 2234 ÷ 2 = 1117, remainder = 0
 1117 ÷ 2 = 558, remainder = 1
 558 ÷ 2 = 279, remainder = 0
 279 ÷ 2 = 139, remainder = 1
 139 ÷ 2 = 69, remainder = 1
 69 ÷ 2 = 34, remainder = 1
 34 ÷ 2 = 17, remainder = 0
 17 ÷ 2 = 8, remainder = 1
 8 ÷ 2 = 4, remainder = 0
 4 ÷ 2 = 2, remainder = 0
 2 ÷ 2 = 1, remainder = 0
 1 ÷ 2 = 0, remainder = 1

 Reading the remainders from bottom to top, the binary representation of 2234 is
100010110010.
2) Convert the fractional part (0.3144) to binary:
Multiply the fractional part by 2, and take the integer part as the next binary digit.
Repeat with the fractional part:
0.3144 × 2 = 0.6288 (integer part: 0)
0.6288 × 2 = 1.2576 (integer part: 1)
0.2576 × 2 = 0.5152 (integer part: 0)
0.5152 × 2 = 1.0304 (integer part: 1)
0.0304 × 2 = 0.0608 (integer part: 0)
0.0608 × 2 = 0.1216 (integer part: 0)
0.1216 × 2 = 0.2432 (integer part: 0)
0.2432 × 2 = 0.4864 (integer part: 0)
0.4864 × 2 = 0.9728 (integer part: 0)
0.9728 × 2 = 1.9456 (integer part: 1)

Thus, the binary representation of the fractional part is approximately 0.0101.

3) Combine the results:

Finding the 1's and 2's Complements
1's Complement:

Invert all the bits of the binary number:

Original: 100010110010.0101
1's Complement: 011101001101.1010
2's Complement
011101001101.1010
+ 1
___________________
011101001101.1011
Finally: For the number 2234.3144
Binary Representation: 100010110010.0101
1's Complement: 011101001101.1010
2's Complement: 011101001101.1011

This representation assumes a fixed number of bits for the integer and fractional
parts. In practice, the binary representation and complements might be handled
differently depending on the precision and format used.
Booth's Algorithm
1. Efficient Multiplication: It reduces the number of required
additions/subtractions by identifying patterns of consecutive ones or zeros.
2. Signed Number Multiplication: It correctly handles multiplication of both
positive and negative numbers in two's complement form.
3. Optimized Hardware Implementation: It helps in simplifying hardware
multipliers by reducing unnecessary additions, making it faster and more
efficient.
How Booth's Algorithm Works

Booth's algorithm uses two bits at a time from the multiplier to

determine whether to perform an addition, subtraction, or no
operation. The two bits are:
• The current bit of the multiplier.
• The previous bit of the multiplier (initially assumed to be 0).
• 00 or 11: No operation (because the bit pattern represents no
change in the magnitude of the product).
• 01: Add the multiplicand to the current partial product.
• 10: Subtract the multiplicand from the current partial product.
Booth's Algorithm Steps

1. Initialize the multiplicand and multiplier, as well as an accumulator (partial

product) initialized to 0.
2. Check the two bits (current and previous bit) and decide whether to add,
subtract, or do nothing.
3. Shift both the partial product and the multiplier to the right to prepare for
the next bit.
4. Repeat the process for all bits in the multiplier.
Booth’s Algorithm -Flowchart
Multiplication of -8 and 12
Floating-Point Representation
 This representation does not reserve a specific number of bits for the
integer part or the fractional part. A number is represented in the form
of M x BE

 M= Mantissa, B= Base, E= Exponent

 6 ×103= Mantissa, 10= Base, 3= Exponent

 4364.784, 4364784= Mantissa, 10= Base, -3= Exponent

 (-1)s × M × (B)E-Bias
 Normalization

 Normalization is the process of standardizing floating-point

numbers into a consistent format.
 There are two types of normalization. Implicit and Explicit. Both
refer to how the leading bit (or digit) of the mantissa is handled.
 Implicit Normalization : (-1)s × 1.M × (2)E-Bias
Saves a bit of storage, allowing more precision.
 Explicit Normalization : (-1)s × 0.M × (2)E-Bias
Allows flexibility for very small numbers (where the MSB can be
0).
Bias
 The bias is used to allow for both positive and negative
exponents to be represented without needing a sign bit in the
exponent field.
 If you wanted to store both 105 and 10-3, a signed exponent
would be needed to distinguish between positive and negative
values.
 E - Bias, Here assume Exponent can has store 4-bits, it can store
numbers 0 to 15 or -8 to 7. Therefore, bias is 8 in this case.
 E = -3 +8 =5
E = 5 + 8 =13
IEEE 754 Floating Point Number Representation
IEEE 754 standardizes the format for representing floating-point
numbers
 Single-Precision (32-bit):
1 bit for the sign (S).
8 bits for the exponent with a bias of 127.
23 bits for the mantissa (with an implicit leading 1 in normalized
form).
 Double-Precision (64-bit):
1 bit for the sign (S).
11 bits for the exponent with a bias of 1023.
52 bits for the mantissa (with an implicit leading 1 in normalized
form).
 Bias: The exponent is stored with a bias (127 for single-precision,
1023 for double-precision).
IEEE 754 Floating Point Number Representation

1) Single Precision Format---- If the register size is 32 bit

2) Double Precision Format--- If the register size is 64 bit

Ex: Represent “1259.125” into single precision and double precision.
Convert “1259.125” into binary format. 1259(Integer part), 0.125(fractional part).
Step 2: Normalize the Number (Where N is the mantissa)

Step 3: Single Precision Format

E -127 = 10
E = 137, Next Convert the 137 into binary using LCM method
E = (10001001)2
Sign = 0(1 bit), Mantissa =00111000110010000000000(23 bit), Exponent =
10001001(8 bit)
Step 4: Double Precision Format
(1.N) 2E-1023 = 1.0011100011001 x 210
E-1023 = 10 , So E = 1033
Convert 1033 into binary using the LCM method
1033 = (10000001001)2
Sign = 0(1 bit), Mantissa =0011100011001……(52 bit), Exponent =
10000001001(11 bit)
Double Precision Format
0 10000001001 0011100011001……

Single Precision Format

0 10001001 0011100011001000000000
0
Special Cases

 The IEEE 754 standard defines several special cases for floating-
point numbers beyond just the regular values
Floating Point Arithmatic
Addtion:

 Convert numbers to IEEE 754 format.

 Align exponents by shifting the mantissa of the smaller number to the right
until both exponents match.
 Add the mantissas together.
 Normalize the result if necessary (shift the result and adjust the exponent).

Subtraction:

 Convert numbers to IEEE 754 format.

 Align exponents by shifting the mantissa of the smaller number to the right
until both exponents match.
 Subtract the mantissas (larger minus smaller).
 Normalize the result if necessary (shift the result and adjust the exponent).
Multiplication:

 Convert numbers to IEEE 754 format.

 Add the exponents of both numbers, subtracting the bias (127 for single
precision).
 Multiply the mantissas of the two numbers.
 Normalize the result if necessary (shift the result and adjust the exponent).
Division:

 Convert numbers to IEEE 754 format.

 Subtract the exponents of both numbers, subtracting the bias (127 for
single precision).
 Divide the mantissas of the two numbers.
 Normalize the result if necessary (shift the result and adjust the exponent).
Arithmetic Logic Unit
Design
Arithmetic Logic Unit Design

Introduction to ALU
Definition: An ALU is a digital circuit within the CPU that performs
arithmetic and logical operations. It's a crucial component of the
processor, enabling it to perform calculations and make logical
decisions.

Importance: The ALU is essential for executing instructions in a

program, as it handles the mathematical and logical computations
required by most instructions.
ALU (Arithmetic Logic Unit)
Perform Arithmetic and Logic Operation
• A fundamental building block of CPU
• Implementing using simple combinational logic circuits(e.g. Adder,
Multiplexer, Logic Gates etc.)
• Brain of CPU
• Basically handles integer operations
• FPUs and GPUs in modern system
• Supercomputer’s processer can have separate FPU and Integer ALU.
• CPU loads the data from input register to an ALU
• CU of process tells ALU what operation to be perform on that data.
After the operation CU transfer the result of ALU into O/P register
Principle of ALU Design

• ALU can be designed with the help of simple logic gates, multiplexer
and adder etc.
• Divide and Conquer strategy
• Once the functions of AU and LU are identified the next thing is to
prepare the function table.
• Once the function table is prepared, Arithmetic and Logical units are
implemented logically.
• Then this function table is mapped such a way that arithmetic and
logic unit can be integrated together.
Principle of ALU Design

• First, simple 1-bit ALU is designed then it is extended for designing

of
4-bit ALU
• Like this, once 4-bit ALU is designed then further, n-bit ALU can be
designed.
• Hence we can learn how to design 1 bit to n bit ALU.
Basic Operations of the ALU
The ALU performs several key types of operations:

Arithmetic Operations:
 Addition: Adds two binary numbers.
 Subtraction: Subtracts one binary number from another.
 Multiplication: Multiplies two binary numbers (basic ALUs may not include this).
 Division: Divides one binary number by another (basic ALUs may not include
this).

Logical Operations:
 AND: Performs a bitwise AND operation.
 OR: Performs a bitwise OR operation.
 XOR: Performs a bitwise XOR operation.
 NOT: Performs a bitwise NOT operation (inverting bits).
Shift Operations:
 Logical Shift: Shifts bits left or right, filling with zeros.
 Arithmetic Shift: Shifts bits left or right, preserving the sign bit.
 Rotate: Rotates bits left or right, wrapping around the bits that
fall off.

Comparison Operations:
 Equality: Checks if two numbers are equal.
 Less Than/Greater Than: Compares two numbers to determine
their relative magnitude.
Components of an ALU:
An ALU typically consists of the following components:

 Adder/Subtractor:
 Implements addition and subtraction operations.
 Subtraction is often implemented using two's complement arithmetic.

Logic Unit:
 Implements logical operations like AND, OR, XOR, and NOT.

Shifter:
 Implements shift and rotate operations.

Multiplexer (MUX):
 Selects the output from different units (adder, logic unit, shifter) based on control
signals.
ALU Design
ALU Design(1-bit ALU Design)
ALU Design(1-bit ALU Design)
Let's design a simple 4-bit ALU that can perform basic arithmetic and logic operations.

Components:
 Inputs: Two 4-bit operands (A and B), operation selection control signals, and carry-in.
 Outputs: 4-bit result, carry-out, and zero flag.

Operation Selection:
 Use control signals to select the operation (e.g., 00 for addition, 01 for subtraction, 10 for AND, 11 for OR).

Adder/Subtractor:
 Implement a 4-bit adder using full adders.
 For subtraction, use the two's complement method by inverting the bits of B and adding 1.

Logic Unit:
 Use basic logic gates to implement AND, OR, and XOR operations.

Multiplexer:
 Use multiplexers to select the appropriate output from the adder/subtractor or logic unit based on the
operation selection control signals.
Division
 Binary division follows the same long division process as decimal division, but with
binary digits (0 and 1)
 Divide 1011 (11) by 11 (3).
 Restoring division algorithm

 Restoring division is a hardware method of binary division used in computers. It

involves shifting and subtraction, with the possibility of restoring the previous value if
subtraction results in a negative value.
 Steps:
1. Initialize: register A will contain value 0, register M will contain Divisor, register Q will
contain Dividend, and N is used to specify the number of bits in dividend.
2. Shift: Shift the remainder and quotient left by one bit.
3. Subtract: Subtract the divisor from the remainder.
4. Now, check the most significant bit of register A. If this bit of register A is 0, then the
least significant bit of register Q will be set with a value 1. If the most significant bit of A
is 1, then the least significant bit of register Q will be set to with value 0, and restore
the value of A that means it will restore the value of register A before subtraction with
M.
5. Decrement N
6. Repeat: Continue until N will be 0.
 Example 11/3
Dividend = 11
Divisor = 3
Non-Restoring
division
algorithm
 Avoids the restoration step,
making it faster in practice.
It is more efficient for
hardware implementation.