Chapter 5( Comp.arch)

Computer Architecture & Organization
ELE5361
Chapter 5: Basic Computer
Organization and Design
Computer Arch. & Org.

Basic Computer Organization & Design 1
BASIC COMPUTER ORGANIZATION AND DESIGN

• Instruction Codes
• Computer Registers
• Computer Instructions
• Timing and Control
• Instruction Cycle
• Memory Reference Instructions
• Input-Output and Interrupt
• Complete Computer Description
• Design of Basic Computer
• Design of Accumulator Logic

INTRODUCTION
• Every different processor type has its own design (different
registers, buses, microoperations, machine instructions,
etc)
• Modern processor is a very complex device
• It contains
– Many registers
– Multiple arithmetic units, for both integer and floating point calculations
– The ability to pipeline several consecutive instructions to speed
execution
– Etc.
• However, to understand how processors work, we will start
with a simplified processor model
• This is similar to what real processors were like ~25 years ago
• M. Morris Mano introduces a simple processor model he calls
the Basic Computer
• We will use this to introduce processor organization and
the relationship of the RTL model to the higher level
computer processor
THE BASIC COMPUTER
• The Basic Computer has two components, a processor

and memory
• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long
CPU
0
RAM
15 0
4095

INSTRUCTIONS
• Program
– A sequence of (machine) instructions
• (Machine) Instruction
– A group of bits that tell the computer to perform a specific operation
(a sequence of micro-operation)
• The instructions of a program, along with any needed
data are stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates
the instruction into the sequence of
microoperations necessary to implement it

INSTRUCTION FORMAT
• A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for that
instruction
– An address that specifies the registers and/or locations in memory to
use for that operation
• In the Basic Computer, since the memory contains 4096 (=
212) words, we needs 12 bit to specify which memory
address this instruction will use
• In the Basic Computer, bit 15 of the instruction specifies
the addressing mode (0: direct addressing, 1: indirect
addressing)
• Since the memory words, and hence the instructions, are
16 bits long, that leaves 3 bits for the instruction’s opcode
Instruction Format
15 14 12 11 0
I Opcode Address
Addressing
mode

ADDRESSING MODES
• The address field of an instruction can represent either
– Direct address: the address in memory of the data to use (the address of the
operand), or
– Indirect address: the address in memory of the address in memory of the data
to use
Direct addressing Indirect addressing
22 0 ADD 457 35 1 ADD 300
300 1350
457 Operand
1350 Operand
+ +
AC AC
• Effective Address (EA)

– The (final) address, that can be directly used without further modification.

PROCESSOR REGISTERS
• A processor has many registers to hold instructions,
addresses, data, etc
• The processor has a register, the Program Counter (PC) that
holds the memory address of the next instruction to get
– Since the memory in the Basic Computer only has 4096 locations, the PC
only needs 12 bits
• In a direct or indirect addressing, the processor needs to
keep track of what locations in memory it is addressing: The
Address Register (AR) is used for this
– The AR is a 12 bit register in the Basic Computer
• When an operand is found, using either direct or
indirect addressing, it is placed in the Data Register
(DR). The processor then uses this value as data for its
operation
• The Basic Computer has a single general purpose register –
the Accumulator (AC)

PROCESSOR REGISTERS
• The significance of a general purpose register is that it can
be referred to in instructions
– e.g. load AC with the contents of a specific memory location; store the
contents of AC into a specified memory location
• Often a processor will need a scratch register to store
intermediate results or other temporary data; in the
Basic Computer this is the Temporary Register (TR)
• The Basic Computer uses a very simple model of input/output
(I/O) operations
– Input devices are considered to send 8 bits of character data to the
processor
– The processor can send 8 bits of character data to output devices
• The Input Register (INPR) holds an 8 bit character gotten from
an input device
• The Output Register (OUTR) holds an 8 bit character to be
send to an output device

BASIC COMPUTER REGISTERS

Registers in the Basic Computer
11 0
PC
Memory
11 0
AR
4096 x 16
15 0
IR
CPU
15 0
15
0
TR DR
7 0 7 0
15 0
OUTR INPR AC
List of BC Registers
DR 16 Data Register Holds memory operand

Computer Arch.
AR& Org. 12 Address Register Holds address for
COMMON BUS
SYSTEM
• The registers in the Basic Computer are connected using

a bus
• This gives a savings in circuitry over complete
connections between registers

COMMON
S2
BUS S1
S0
Bus
Memory unit 7
SYSTEM4096 x 16 Address
Write Read
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR
E
ALU AC 4
LD INR CLR
INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus

COMMON BUS SYSTEM
Read INPR
Memory Write
4096 x 16
Address E
ALU
AC
L I C
L I C L
L I C DR IR L I C
PC TR
AR OUTR LD
L I C
7 1 2 3 5 6
4
16-bit Common Bus
S0 S1
S2
COMMON BUS
SYSTEM
• Three control lines, S2, S1, and S0 control which register the
bus selects as its input
S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory
• Either one of the registers will have its load signal

activated, or the memory will have its write signal activated
– Will determine where the data from the bus gets loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto the
bus in the high order 4 bit positions
• When the 8-bit register OUTR is loaded from the bus,
the data comes from the low order 8 bits on the bus

BASIC COMPUTER INSTRUCTIONS
• Basic Computer Instruction Format
Memory-Reference Instructions (OP-code = 000 ~

110)
I Opcode Address
15 14 12 11 0
Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation
Input-Output Instructions (OP-code =111, I = 1)

15 0
1 1 1 1 I/O operation
12 11

BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol Description
I=0 I=1
AND 0xxx 8xxx AND memory word to AC

1xxx 9xxx Add memory word to AC
ADD 2xxx Axxx Load AC from memory
3xxx Bxxx Store content of AC into memory
LDA 4xxx Cxxx Branch unconditionally
STA 5xxx Dxxx Branch and save return address
6xxx Exxx Increment and skip if zero
BUN
BSA
ISZ
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer
INP F800 Input character to AC

OUT F400 Output character from AC
Computer SKI
Arch. & Org. F200 Skip on input flag
INSTRUCTION SET COMPLETENESS
A computer should have a set of instructions so that the user
can construct machine language programs to evaluate any
function that is known to be computable.
• Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main
memory and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT

CONTROL UNIT
• Control unit (CU) of a processor translates from machine

instructions to the control signals for the
microoperations that implement them
• Control units are implemented in one of two ways

• Hardwired Control
– CU is made up of sequential and combinational circuits to generate the
control signals
• Microprogrammed Control
– A control memory on the processor contains microprograms that
activate the necessary control signals
• We will consider a hardwired implementation of the control

unit for the Basic Computer

TIMING AND CONTROL
Control unit of Basic Computer
Instruction register (IR)

15 14 13 11 - 0 Other inputs
12
3x8
decoder
76543
210
D0
I Combinational
D7 Control
Control
logic signals
T15
T0
15 14 . . . . 2 1 0
4 x 16
decoder
4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.
- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC  0
T0 T1 T2
T3 T4
T0
Clock
T0
T1
T2
T3
T4
D3
CLR
SC
INSTRUCTION CYCLE
• In Basic Computer, a machine instruction is executed in the

following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an
indirect address
4. Execute the instruction
• After an instruction is executed, the cycle starts again at

step 1, for the next instruction
• Note: Every different processor has its own

(different) instruction cycle

FETCH and DECODE
• Fetch and Decode T0: AR  PC
T1: IR  M [AR], PC  PC + 1
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)
T1 S2
T0
S1 Bus
S0
Memory
7
unit
Address
Read
AR 1
LD
PC 2
INR
IR 5
LD Clock
Common bus

DETERMINE THE TYPE OF INSTRUCTION

Start
SC  
T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I
 IR(15)
(Register or I/O) =1 D7 = 0 (Memory-reference)
(indirect) = 1 = 0 (direct)
(I/O) = 1 I = 0 (register) I
T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instructi
SC  0 on Execute T4
SC  0 memory-reference
instructi
on
SC  0
D7IT3: Execute an input-output instr.

D7I'T3: Execute a register-reference instr.
D'7IT3: AR  M[AR]
D'7I'T3: Nothing
REGISTER REFERENCE INSTRUCTIONS

Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3
r = D7I’T3=> Register Reference Instruction Bi

= IR(i) , i=0,1,2,...,11
r: SC  0
CLA rB11: AC  0
E0
rB10:
CLE rB9:
AC  AC’
CMA rB8:
E  E’
rB7:
CME rB6:
rB5: AC  shr AC, AC(15)  E, E  AC(0)
CIR rB4:
rB3: AC  shl AC, AC(0)  E, E  AC(15)
CIL rB2:
rB1:
Computer Arch. & Org. AC  AC + 1
MEMORY REFERENCE INSTRUCTIONS

Symbol Operation Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
AC  AC + M[AR], E  Cout
ADD D1 AC  M[AR]
M[AR]  AC
LDA D2 PC  AR
STA M[AR] 
D3 PC, PC  AR
BUN +1
D4 M[AR] 
- The effective address
BSA M[AR]of theif instruction is in AR and was placed there during
+ 1,
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory Dcycle
ISZ 5 M[AR] + 1 =
is assumed to be short enough to complete in a CPU cycle
- The execution of0 MR PC 
theninstruction starts with T4
D6 PC+1
AND to AC
D0T4: DR  M[AR] Read operand
AC  AC  DR, SC  0 AND with AC
D0T5:
ADD to AC DR  M[AR] Read operand
D1T4: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E


LDA: Load to AC
D2T4: DR 
M[AR] D2T5: AC  DR,
SC  0
STA: Store AC
D3T4: M[AR] 
AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC 
0 Memory, PC after execution
BSA: Branch and Save 20 Return
0 BSA 135 20 0 BSA 135
Address PC = 21 Next instruction 21 Next instruction
M[AR]  PC, PC  AR +
1
Memory, PC, AR at time T4
AR = 135 135 21
136 Subroutine PC = 136 Subroutine
1 BUN 135 1 BUN 135

Memory Memory
BSA:
D5T4: M[AR]  PC, AR 
AR + 1 D5T5: PC  AR, SC  0
ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR] 
DR, if (DR =
0) then (PC  PC + 1),
SC  0

FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS
Memory-reference instruction
AND ADD LDA STA
D0 T4 D1 T4 D3 T4
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0
D2T4
D0 T5 D1 T5 D2 T5
AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0
BUN BSA ISZ
D4 T4 D5 T4 D6 T4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1
D5 T5 D6 T5
PC  AR DR  DR + 1
SC  0
D6 T6
M[AR]  DR
If (DR = 0)
then (PC 
PC + 1)
SC  0
INPUT-OUTPUT AND INTERRUPT

A Terminal with a keyboard and a Printer
• Input-Output Configuration
Serial Computer
Input-output communica tion
terminal interface registers and
flip-flops
Receiver
Printer OUTR FGO
interface
AC
Transmitter
Keyboard interface INPR FGI
INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1
bit
- The terminal sends and receives serial information
- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the
computer
PROGRAM CONTROLLED DATA

TRANSFER
-- CPU -- -- I/O Device --
/* Input */ /* Initially FGI = 0 */ loop: If FGI = 1 goto loop
loop: If FGI = 0 goto loop INPR  new data, FGI  1
AC  INPR, FGI  0
/* Output */ /* Initially FGO = 1 */ loop: If FGO = 1 goto
loop
loop: If FGO = 0 goto loop consume OUTR, FGO  1 OUTR  AC, FGO 
0
FGI=0
FGO=1
Start Input
Start Output
FGI  0 OUTR  AC
AC  Data
FGO  0
yes yes
FGI=0 FGO=0
no
no
Computer Arch. & Org.AC  INPR

INPUT-OUTPUT INSTRUCTIONS
D7IT3 = p
IR(i) = Bi, i = 6, …, 11
p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off

PROGRAM-CONTROLLED INPUT/OUTPUT
Input
LOOP, SKI
BUN LOOP
INP
Output
LOOP, LDA DATA
LOP, SKO
BUN LOP
OUT
• Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware

INTERRUPT INITIATED INPUT/OUTPUT

- Open communication only when some data has to be passed --> interrupt.
- The I/O interface, instead of the CPU, monitors the I/O device.
- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU
- Upon detecting an interrupt, the CPU stops momentarily the task

it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.
* IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions
- when cleared, the computer cannot be interrupted

FLOWCHART FOR INTERRUPT CYCLE

R = Interrupt f/f
Instruction cycle =0 =1 Interrupt cycle
R
Fetch and decode Store return address

instructions in location 0
M[0]  PC
Execute =0
IEN
instructions
=1 Branch to location 1
PC  1
=1
FGI
=0
=1 IEN  0
FGO R0
=0
R
1
- The interrupt cycle is a HW implementation of a branch

and save return address operation.
- At the beginning of the next instruction cycle, the
instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction
that sends the control to an interrupt service routine
- The instruction that returns the control to the original
program is "indirect BUN 0"

REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE
Memory
Before interrupt After interrupt cycle
0 0 256
1 0 BUN 1120 PC = 0 BUN 1120
1
Main Main
255 Program 255 Program
PC = 256 256
1120 1120
I/O I/O
Program Program
1 BUN 0 1 BUN 0
- The fetch and decode phases of the instruction cycle

must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0: AR  0, TR  PC
M[AR]  TR, PC  0
RT1: PC  PC + 1, IEN 
0,
- Register Transfer Statements for Interrupt Cycle
- RRTF/F
2: R1 0,ifSC 0 + FGO ) T0 T1 T2
IEN(FGI
 (IEN)(FGI + FGO):
FURTHER QUESTIONS ON INTERRUPT
How can the CPU recognize the device

requesting an interrupt ?
Since different devices are likely to require

different interrupt service routines, how
can the CPU obtain the starting address of
the appropriate routine in each case ?
Should any device be allowed to interrupt the

CPU while another interrupt is being
serviced ?
How can the situation be handled when two or

more interrupt requests occur simultaneously ?

COMPLETE COMPUTER DESCRIPTION
Flowchart of Operations
start
SC  0, IEN  0, R  0
=0(Instruction =1(Interrupt
R
Cycle) Cycle)
R’T0 RT0
AR  PC AR  0, TR  PC
R’T1 RT1
IR  M[AR], PC  PC + 1 M[AR]  TR, PC  0
R’T2 RT2
AR  IR(0~11), I  IR(15) PC  PC + 1, IEN  0
D0...D7  Decode IR(12 ~ 14) R  0, SC  0
=1(Register or I/O) D7 =0(Memory Ref)
=0 (Register) =1(Indir) =0(Dir)

=1 (I/O) I
I
D7IT3 D7I’T3 D7’IT3 D7’I’T3

Execute Execute AR <- M[AR] Idle
I/O RR
Instruction Instruction
Execute MR D7’T4
Instruction

Microoperations
Fetch RT0: AR  PC
IR  M[AR], PC  PC + 1
Decode RT1: D0, ..., D7  Decode IR(12 ~ 14),
AR  IR(0 ~ 11), I  IR(15)
Indirect RT2: AR  M[AR]
Interrupt
T0 T1 T2 ( IEN
D7)IT
(F G I + R1
FGO): 3:
AR  0, TR  PC
RT0: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN 
Memory-ReferenceRT1: 0, R  0, SC  0
AND D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
ADD DR  M[AR]
D1T4: AC  AC + DR, E  Cout, SC  0
LDA DR  M[AR]
D1T5: AC  DR, SC  0
STA M[AR]  AC, SC  0
BUN D2T4: PC  AR, SC  0
M[AR]  PC, AR  AR + 1
BSA D2T5: PC  AR, SC  0
ISZ DR  M[AR]
D3T4: DR  DR + 1
M[AR]  DR, if(DR=0) then (PC  PC + 1),
D4T4: SC  0
D5T4:
D5T5:
Microoperations
Register-Reference
D7 I  T 3= (Common to all register-reference instr)
r IR(i) = (i = 0,1,2, ..., 11)
Bi SC  0
CLA rB
r: 11: AC  0
CLE E 0
CMA rB10: AC  AC’
rB9: E  E’
CME rB8: AC  shr
CIR rB7: AC,
CIL rB6: AC(15) 
INC rB5: E, E 
SPA rB4: AC(0)
SNA rB3: AC  shl AC, AC(0)  E, E  AC(15)
SZA rB2: AC  AC + 1
SZE rB1: If(AC(15) =0) then (PC  PC + 1)
HLT rB0: If(AC(15) =1) then (PC  PC + 1)
Input-Output If(AC
(Common= 0) then
to all(PC  PC + 1) instructions)
input-output
D7IT3 = p If(E=0) then (PC
(i = 6,7,8,9,10,11)  PC + 1)
IR(i) = S
SC0 0
INP B i AC(0-7)  INPR, FGI  0
OUT p: OUTR  AC(0-7), FGO  0
SKI pB11: If(FGI=1) then (PC  PC + 1)
SKO If(FGO=1) then (PC  PC + 1)
ION pB10: IEN  1
IOF pB9: IEN  0
pB8:
pB7:
pB6:
DESIGN OF BASIC COMPUTER(BC)

Hardware Components of BC
A memory unit:
4096 x 16. Registers:
AR, PC, DR, AC, IR,
TR, OUTR, INPR, and
SC
Flip-Flops:
I, S, E, R, IEN, FGI,
and FGO
Decoders: a 3x8
Opcode decoder
a 4x16 timing decoder
Common bus: 16 bits
Control logic gates:
Adder and Logic
circuit:
Connected to AC
Control Logic Gates

- Input Controls of the nine
registers
- Read
Computer Arch. and Write Controls of
& Org.
CONTROL OF REGISTERS AND MEMORY

Address Register; AR
Scan all of the register transfer statements that change the content of AR:
R’T0: AR  PC LD(AR)
R’T2: AR  IR(0-11) LD(AR)
D’7IT3: AR  M[AR] LD(AR)
RT0: AR  0 CLR(AR)
D5T4: AR  AR + 1 INR(AR)
LD(AR) = R'T0 + R'T2 + D'7IT3

CLR(AR) = RT0
INR(AR) = D5T4
12 12
From bus AR To bus
D'7
LD Clock
TI 3 INR
T2
CLR
R
T0
D
5
Computer Arch. &TOrg.
CONTROL OF FLAGS
IEN: Interrupt Enable Flag
pB7: IEN  1 (I/O Instruction)
pB6: IEN  0 (I/O Instruction)
RT2: IEN  0 (Interrupt)
p = D7IT3 (Input/Output
Instruction)
D7 p
J Q IEN
B7
I
T3 B6
K
R
T
2

CONTROL OF COMMON BUS

x1
x2 S2
x3 Encoder
Multiplexer S 1
x4
bus select
x5
inputs
selected
x6 x1 x2 x3 x4 x5 x6 x7 S2 S1 SS00 register
0 0 0 0 0 0 0 0 0 0 none
x7 1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 0 0 0 0 0 1 1 1 1 Memory
For AR D4T4: PC  AR
D5T5: PC  AR
x1 = D4T4 + D5T5

DESIGN OF ACCUMULATOR LOGIC

Circuits associated with AC 16
Adder and
16 16 16
From DR logic AC
circuit To bus
From INPR 8
LD INR CLR Clock
Control
gates
All the statements that change the content of AC

D0T5: AC  AC  DR AND with DR
AC  AC + DR Add with DR
D1T5: AC  DR Transfer from DR
AC(0-7)  Transfer from INPR
D2T5: INPR Complement
AC  AC’ Shift right
pB11: AC  shr AC, Shift left
rB9: AC(15)  E Clear
rB7 : AC  shl AC, AC(0)  E Increment
rB6 : AC  0
AC  AC + 1
rB11 : & Org.
Computer Arch.
CONTROL OF AC REGISTER
Gate structures for controlling

the LD, INR, and CLR of AC
16 To bus
From Adder 16 AC
and Logic
D0 LD Clock
INR
AND CLR
T5
D1
ADD
D2
DR
T5
p
INPR
B11
r COM
B9
Computer Arch. & Org. SHR
ALU (ADDER AND LOGIC CIRCUIT)
One stage of Adder and Logic circuit

DR(i)
AC(i)
AND
Ci ADD LD
J Q
FA Ii AC(i)
C
DR
i+1
From
INPR INPR K
bit(i)
COM
SH
R
AC(i+1)
SH
L
AC(i-1)

Chapter 5( Comp.arch)

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Computer Architecture & Organization

Chapter 5: Basic Computer

Organization and Design

Computer Arch. & Org.

BASIC COMPUTER ORGANIZATION AND DESIGN

• Timing and Control

• Memory Reference Instructions

• Input-Output and Interrupt

• Complete Computer Description

• Design of Basic Computer

• Design of Accumulator Logic

Computer Arch. & Org.

• The Basic Computer has two components, a processor

Computer Arch. & Org.

Computer Arch. & Org.

Computer Arch. & Org.

22 0 ADD 457 35 1 ADD 300

• Effective Address (EA)

Computer Arch. & Org.

Computer Arch. & Org.

Computer Arch. & Org.

BASIC COMPUTER REGISTERS

DR 16 Data Register Holds memory operand

• The registers in the Basic Computer are connected using

Computer Arch. & Org.

Computer Arch. & Org.

COMMON BUS SYSTEM

• Either one of the registers will have its load signal

Computer Arch. & Org.

• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~

Register-Reference Instructions (OP-code = 111, I = 0)

Input-Output Instructions (OP-code =111, I = 1)

Computer Arch. & Org.

AND 0xxx 8xxx AND memory word to AC

INP F800 Input character to AC

Computer Arch. & Org.

• Control unit (CU) of a processor translates from machine

• Control units are implemented in one of two ways

• We will consider a hardwired implementation of the control

Computer Arch. & Org.

Control unit of Basic Computer

Instruction register (IR)

4-bit Increment (INR)

Computer Arch. & Org.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

• In Basic Computer, a machine instruction is executed in the

• After an instruction is executed, the cycle starts again at

• Note: Every different processor has its own

Computer Arch. & Org.

Computer Arch. & Org.

DETERMINE THE TYPE OF INSTRUCTION

(Register or I/O) =1 D7 = 0 (Memory-reference)

D7IT3: Execute an input-output instr.

REGISTER REFERENCE INSTRUCTIONS

r = D7I’T3=> Register Reference Instruction Bi

MEMORY REFERENCE INSTRUCTIONS

Computer Arch. & Org.

MEMORY REFERENCE INSTRUCTIONS

1 BUN 135 1 BUN 135