Second Order Effects

Presented by
Madhu Sudhan
 • What is meant by Second Order
Effects ?
• How it Causes damage to our
Introducti Mosfet ?
on • Remedies to overcome these
Effects ?
Moore's
law
• Moore's law is the observation that the number of transistors in an integrated circuit (IC)
doubles & The gate lengths also get reduced by a half about every two years.
• We have encountered some challenges when we began reducing the gate length of the
Mosfet during its operation.
• There are two Types of Effects Such as
• First Order Effects.
• Second Order Effects.
Introduction To First Order
Effects
• The First Order Effects are the immediate consequences when they come into picture the operation of the
MOSFET will get damage or changes rapidly into undesired state.
Such as :
• Oxide breakdown (Thickness Variation)
• Doping Concentration(Change in Vth)
• Device Parameters :Change in device Resistance and Capacitance .
Introduction To Second Order
Effects
• These effects become apparent when the channel length decreases So these are different
from the first order effects .The Second Order effects are categorized accordingly.
• Channel Length Modulation
• Velocity Saturation
• Hot Carrier Effect
• Impact Ionization
• Body Effect
• DIBL
• Drain Punch Through
• Sub threshold current
• Gate tunnel current
Channel Length Modulation
• In lower technologies the channel length decreases, which results in a shorter distance
between the source and drain regions.
• When we operate the mosfet, in the Saturation region the current (Id) remains constant.
The drain current (Id) is influenced by the Electric Field (Vds) and width of the depletion
region of drain terminal.
• As Vds increases furtherly at particular potential the channel gets pinch off
• That implies that there is no connection, between the channel and drain region of a MOSFET.
When the Vds (drain, to source voltage) increases the charge carriers move into the
depletion region. Eventually enter the drain region. As a result the Id (drain current
increases).
• While we are increasing the Vds the depletion region width of drain also increases
and dominates the change in the Id current and finally we get constant Id in higher nodes
• But in the lower technologies the Vds get dominates the depletion region width of drain so
the more Id current flows which was explained in above point
• As we are increasing the Vds the channel
length get decreases because the width of
depletion regions starts increases these
are inversely proportional
• Here the change in channel length can be
called as "Channel length modulation
factor" indicated by lambda (λ)
• So In the lower technologies the designer
used to prefer the much larger devices
than the shorter length devices for the
critical devices
Long Channel Devices Short Channel Devices
Velocity
Saturation
• The Velocity Saturation means "The Charge Carries reaches the max velocity in the
presence of high Electric Field ,when this happens the semiconductor is said to be in
velocity Saturation State".
• The Charge Carriers moves with average drift Velocity which is directly proportional
to the applied electric field intensity .
• The proportionality constant is known as mobility which is a material property,
generally the conductor have higher mobility compared to other materials
• Before the device reaches the pinch off region the charges move freely when the
channel gets into pinch off region the width of the channel decreases

• V=µE here V is Velocity saturation and µ is mobility and E is Electric field.

• As the channel width gets narrower the charge carries
can't move freely , If the applied electric field
continues to increase the velocity of the carriers will
no longer increase because they lose energy through
collisions, with other charge carriers hence the Id gets
constant.
• Typical values of saturation velocity may vary greatly
for different materials, for example for Si it is in the
order of 1×107 cm/s, for GaAs 1.2×107 cm/s, while for
6H-SiC, it is near 2×107cm/s.
• The problem with the velocity saturation is when the
vds not reaches to the vgs–vt the device undergoes
to the saturation due to the material functionality or
property .
• So, to overcome this problem the foundry prefer the
p-sub and n-well for the GaAs & 6H-SiC materials to
support for more velocity.
Hot Carrier
Effect
• This Effect comes when we apply a more drain voltage in short channel devices .More drain voltage creates the more
electric field which attracts the more charge carries from the source region these charge carries gets more velocity and
also more kinetic energy.
• The charge carries will reach the maximum velocity and it gets more kinetic energy are said to be "Hot Electrons"
• When the Electric Field (Vds) is increases then more no .of charges carries will be attracted towards the drain region
Since the drain region is heavily doped ,it has already free electrons inside it .So it has less space to collect the
electrons.
• So, the hot carrier is having very less space to get fill into the drain region . These hot carriers having high kinetic energy
due to some collisions at edges of drain region the hot carriers will enter into gate region and damages the gate oxide
• If the gate oxide is damaged completely, then unwanted currents will flow between the substrate and gate they both get
shorted and mosfet works in undesired state .This is called as Hot Carrier Effect.
• To avoid this effect foundry prefers the high K dielectric medium materials (high dielectric constant materials) it has
ability to withstand the hot carrier effect.
• The foundry also designed some devices that are lightly doped drain region mos(DEMOS) So they have extra space to
collect the hot electrons.
Hot Carrier
Effect

The above figures represents Hot Carrier

Injection
 Impact
•
Ionization
It is a part hot carrier effect as the electron attains kinetic energy. The hot carriers will get reflected the drain region
and some hot electron will break the covalent bond of depletion region of drain, so the hot electron will break the
covalent bond, So a free hole and electron will be created that electron will be attracted by the drain and fewer holes
will be enter into the substrate
• If a greater number of covalent bonds breaks, then more electron and hole pair creates, and the electron will be get
collected by the drain and the holes will enter into the substrate and the unwanted currents will flow into it
• If the leakage flows continuously then it may have a chance to create the potential drop 0.7v and it triggers on the
parasitic transistors.
• Once it happens, we cannot control the current between them by the gate .This is called as the Impact Ionization
• If we able to control or decrease the hot carrier effect, the impact ionization effect will be got controlled or
decreases
Body
Effect
• Body effect is a phenomenon that occurs in MOSFETs in which the threshold voltage of the device changes due to a
difference between the substrate (body) and source voltages. The body effect is also known as the back-gate effect
because the body can be thought of as a second gate.
• The Body Effect can be explained by three cases such as
• When the VB is tied to the positive potential
• When the VB is tied to the negative potential
• When the VB is tied to the VS potential
• First Case : When the body is tied to the positive potential then the parasitic diodes will get turn on and creates a latch
up. So, this case cannot be used for operating the mosfet.
• Second Case :When the body is tied to the negative potential then holes which are present in the substrate will be
attracted towards the negative terminal by leaving negative charges (it may be negative immobile Ions) so the electrons
should cross the these negative immobile ions and enters into the channel so for crossing they need more attraction
force this can be provided by the increases the "VT"
• If the more negative potential is applied, then more depletion region forms hence we require more Vt to cross this
region .
So by solving above equation, we can understand the body effect by tying the source and bulk to
the same potential we can get no variation in the VT of MOSFET devices.
DIBL(Drain Induced Barrier
Lowering)
• The DIBL comes when more drain voltage is applied than the bulk potential due to it reverse biased depletion region will get
increases and occupies some space in the channel .So, we need less voltage which is required the turn on the mosfet .
• Basically, this kind of problem comes even in long channel devices that too very small variation of VT change. But In short
channel devices since its length is very small, VT change is considerable (more)
• The DIBL is also called as the VT rolloff that means the thershold voltage is changed due to the increasing of the
depletion
region of drain and occupying the space in the channel.
• In general, there are two categories of DIBL such as
• Surface DIBL
• Bulk DIBL
• Surface DIBL : The depletion region of the drain has increased towards the channel can be called as Surface DIBL.
• Bulk DIBL : The depletion region of the drain will also encrochment into the bulk of the MOSFET
• Since the drain depletion region increases more into channel and bulk and decreasing the channel length and finally changing
the Vt of the mosfet.
• To overcome this problem, foundry people has designed mosfet such that there will be lesser depletion region form between
drain and bulk even it is high reverse biased. Basically, we can achieve this by increase doping concentration of either drain
or bulk
The above figures represents Drain
Induced Barrier Lowering
Drain Punch
Through
• Drain punch-through refers as a phenomenon that occurs in MOSFET It occurs when the drain voltage is high enough
with respect to the source voltage, causing the depletion region around the drain to extend towards the source. This
extension of the depletion region leads to a current flow, regardless of the gate voltage.
• Since the gap between the source and drain is very less, the depletion region of drain will touch with the source
depletion region If this happen once, the drain current between source and drain can't be control by the gate
• Drain punch-through in MOSFETs can significantly affect their performance in the following ways :
• Increased power consumption: The punch-through effect can lead to an increase in the subthreshold leakage current,
which adds to the drain current and results in higher power consumption
• Rapid increase in drain-to-source current: When the depletion region around the drain extends towards the source, it
causes a rapid increase in drain-to-source current, which affects the device's performance.
• To prevent this issue, the foundry will adjust the doping levels of the source, drain, and bulk regions. This will result in
smaller depletion widths in lower channel devices, even at higher source/drain voltages. As a result, the punch through
effect can be minimized.
The above figures represents Drain
punch Through
Sub Threshold
Current
• Subthreshold conduction or subthreshold leakage or subthreshold drain current is the current between the source
and drain of a MOSFET when the transistor is in subthreshold region, or weak-inversion region, that is, for gate-to-
source voltages below the threshold voltage.
• Ideally Mosfet drain current has to be 0 when mosfet is in OFF state. But In Mosfet, current will flow from source to
drain even when VGS is less than the threshold voltage due to weak inversion. We call it as sub threshold current.
Basically, this type of current will flow even in long channel devices, but it is very minor and in terms of picoamps (pA)
• So, in long channel devices that leakages wont effect the working functionality of mosfet But in lower channel devices,
due to space between the source and drain is less, there is more drift current(electric field current by drain) flows
under the gate, and it is significant amount and in terms of micro amps(uA). Gradually this subthreshold current will
increase if we go for lower channel devices. And it is inversely proportion to channel length and proportional to the
drain voltage and temperature.
• This type of leakage current (or off state current) has decreased in SOI & FIN FET technology by its different
construction. That leakage are get minimized in further technologies.
The above figure represents Subthreshold Current
Gate Tunnel
Current
• Gate tunneling current mechanism: Gate tunneling current occurs when carriers (electrons or holes) tunnel through the
energy barrier of the gate oxide. This tunneling process is a quantum mechanical phenomenon that allows carriers to
pass through the energy barrier even though they do not have enough energy .
• As we are going to lower technology, since device size is decreased, each and every thing size has to be decreased.
Those
are like source/drain depths & its area and metal widths & spacing and same way gate oxide thickness also decreased.
• Since gate oxide thickness has decreased, if we use same gate oxide material as used in long channel devices, since there
is a less gap between the gate and substrate, due to gate voltage vertically more electrical field will appear at gate to
channel. Basically, at the inversion (positive gate voltage) attracts the electros to form a channel. Due its vertical
attraction field and due to its thin oxide, there is a chances of flow of electrons from the substrate (or channel) to the
gate. This we call it as gate tunnel current. And this tunnel current flows gate to substrate when it is in accumulation (-ve
gate voltage)
• As we are going to lower technology, since device size is decreased, each and every thing size has to be decreased. Those
are like source/drain depths & its area and metal widths & spacing and same way gate oxide thickness also decreased.
• The Gate Tunnel Current which impacts on device performance such as
• Degradation of threshold voltage
• Reliability concerns
 Damaging of gate oxide due to
gate tunneling

Above fig represents Gate Tunneling in

MOSFET
Remedi
es
• All these effects are minimized by various techniques like Finfet, SOI, DEMOSFET
etc.

Figures which represents the FINFET & SOI

3D View of FIN FET
THANK YOU