DDCO - Module 2

4 bit binary adder

 Binary Adder - Subtractor When M = 0, the circuit is an adder,
M = 1, the circuit is a subtractor

Overflow.
4 bit binary adder-subtractor with overflow detection
 Carry Lookahead Logic
• A carry-look ahead adder (CLA) or fast adder is a type of
adder used in digital logic.
• A carry-look ahead adder improves speed by reducing the
amount of time required to determine carry bits.
• It carry look ahead adder calculates one or more carries
before the sum, which reduces the wait time to calculate
the result of the larger value bits of the adder.
• Carry look-ahead adder has just two levels of gate delay
from any input to any output. the time delay
is independent of the number of bits in the operand. But it
depends on the number of operands, propagation delay.
• Advantages
• The propagation delay is reduced.
• It provides the fastest addition logic.
• Disadvantages
• The Carry Look-ahead adder circuit gets complicated as the number
of variables increase.
• The circuit is costlier as it involves more number of hardware.
 Full adder with P and G

Gi : Gi = AiBi Garry Generate, Produces a carry of 1 when both Ai and Bi are 1, regardless of the input carry Ci.
Pi : Pi = Ai Bi Carry Propagate, determines whether a carry into stage i will propagate into stage i + 1

The output sum and carry can respectively be expressed as

S i = P i Ci
Ci+1 = Gi + PiCi
 Logic diagram of carry look
ahead generator

• C0 = input carry
• C 1 = G 0 + P 0C 0
• C2 = G1 + P1C1 = G1 + P1G0 + P0C0 = G1 + P1G0 + P1P0C0
• C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 = P2P1P0C0
Full adder
using look
ahead
generator
BCD
Adder
using 4
bit full
adder
Multiplexers
• Combinational circuit that selects binary
information from one of many input
lines and directs the information to a
single output line. The selection of a
particular input line is controlled by a set
of input variables, called selection
inputs.
4 to 1 mux
 8 to 1 Mux

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+
S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .A6+S0.S1.S3.A7
8 to 1 mux
using
two 4 to 1 and
one 2 to 1 mux
8 to 1 mux
using
four 2 to 1 and

one 4 to 1 mux
16 to 1
mux
using
4 to 1
mux
Realize Y=A'B + B'C' + ABC using an 8-to-1
multiplexer.

• Express Y as a function of minterms of three variables

Y = A'B + B'C' + ABC
= A'B(C' + C)+B'C'(A' + A)+ ABC [As,X+X'= I]
= A'B'C' + A'BC' + A'BC + AB'C' + ABC
• Comparing this with equation of 8 to 1 multiplexer,
• substituting D0 = D2 = D3 =D4 = D7 = 1 and D1 = D5 = D6 = 0.
Can it be realized Y =A'B + B'C‘ + ABC
equation with a 4-to-1 multiplexer?
• The 4-to-1 multiplexer generates 4 minterms for different combinations of AB.
Y = A'B + B'C' + ABC
= A'B + B'C'(A' +A) + ABC [As,X +X' = I]
= A'B'.C' + A'B.1 +AB'.C' + AB.C
• Compare above with equation of a 4-to-1 multiplexer.
D0 = C', D1 = 1, D2 = C' and D3 = C generate the given logic function.
Full adder using 8: 1

A B C A B C
De-multiplexer
• Combinational circuit has only 1 input line and 2N output lines.
• The information is received from the single input lines and directed to
the output line.
• On the basis of the values of the selection lines, the input will be
connected to one of these outputs.
• De-multiplexer is opposite to the multiplexer.
• There are n selection lines and 2n outputs. So, there is a total of
2n possible combinations of inputs.
1 to 2 de-mux

Input Output
S0 Y1 Y0
0 0 A
1 A 0

Y0=S0'A
Y1=S0A
 1x4 de-mux

Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A
1×8 De-multiplexer using 1×4 and 1×2
de-mux
Decoder
• A decoder is similar to a demultiplexer, with one exception-
there is no data input.
• Also called binary-to-decimal decoder.
• The name decoder means translating of coded information from
one format into another.
• A binary decoder is a multi-input, multi-output combinational
circuit that converts a binary code of n input lines into a one out
of 2n output code.
• Depending on the number of input lines, the inputs of a binary
code can be 2-bit or 3-bit or 4-bit codes. Upon the availability of
2n lines, it activates the one of its output by deactivating (making
logic 0) all other input whenever it receives n inputs.
• The most commonly used practical binary decoders are 2-to-4
decoder, 3-to-8 decoder and 4-to-16 line binary decoder.
• 2-to-4 decoder also called 1 of 4
• 3-to-8 decoder also called 1 of 8
• 4-to-16 line binary decoder also called 1 of 16
2-to-4 Binary Decoder (1 of 4 Decoder)

Input Output
A B Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
3-to-8 Binary Decoder (1 of 8
Decoder)

A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
A 4-to-10 Line Decoder
 A 4-to-10 Line Decoder
BCD Input Decimal Output
A B C D 0 1 2 3 4 5 6 7 8 9
0 0 0 0 0 1 1 1 1 1 1 1 1 1
• This decoder has inverted outputs (indicated by the small circles). 0 0 0 1 1 0 1 1 1 1 1 1 1 1
• For each combination of the values of the inputs, exactly one of the 0 0 1 0 1 1 0 1 1 1 1 1 1 1
output lines will be 0. 0 0 1 1 1 1 1 0 1 1 1 1 1 1
• When a binary-coded-decimal (BCD) digit is used as an input to this
0 1 0 0 1 1 1 1 0 1 1 1 1 1
decoder, one of the output lines will go low to indicate which of the
0 1 0 1 1 1 1 1 1 0 1 1 1 1
10 decimal digits is present.
0 1 1 0 1 1 1 1 1 1 0 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
1 0 1 0 1 1 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1
1 1 0 0 1 1 1 1 1 1 1 1 1 1
1 1 0 1 1 1 1 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
 Applications of Decoders
• Decoders are greatly used in applications where the particular output or group of outputs to
be activated only on the occurrence of a specific combination of input levels.
• Binary to Decimal Decoder
• Decoders are used to get the decimal digit corresponding to a specific input combination. A BCD number needs 4
binary digits to represent the 0 to 9 decimal digits, thus it consists of 4 input lines. It consists of 10 output lines
corresponding to 0 to 9 decimal digits. (1 of 10 line decoder)
• Address Decoders
• Amongst its many uses, a decoder is widely used to decode the particular memory location in the computer memory
system. Decoders accept the address code generated by the CPU which is a combination of address bits for a specific
location in the memory. In a memory system, there are several memory ICs are combined and each one has their
unique address to distinguish from other memory locations. In such cases a decoder built in the memory ICs circuitry,
is used to select a memory IC in response to a range of addresses by decoding the most significant bits of the systems
address, thereby a particular memory location or IC is selected.
• Instruction Decoder
• Another application of the decoder can be found in the control unit of the central processing unit. This decoder is used
to decode the program instructions in order to activate the specific control lines such that different operations in the
ALU of the CPU are carried out.
 Realize f1(a, b, c, d) = m1 + m2 + m4 and
f2(a, b, c, d) = m4 + m7 + m9 using the 4 to
10 line decoder.
Show how using a 3-to-8 decoder and multi-input OR
gates following Boolean expressions can be realized
simultaneously.
F1 (A, B, C) = ∑m(0, 4, 6);
F2(A, B, C) = ∑m(0, 5);
F3(A, B, C) = ∑m(1, 2, 3, 7)
Implement a full adder circuit using a 3-to-8 line
decoder.
Sum output S = ∑m(1 2 4 7)
Carry output Co= ∑m(3 5 6 7)
Seven Segment decoder

7 output equation(Equation for segment a, b, c,....)

Boolean equation for segment a,
and b

a= AB’C’ + A’BD + AD’ + A’C + BC + B’D’. b = A’C’D’ + A’CD + AC’D + B’C’ + B’D’
Encoders
• An encoder converts an active input signal into a coded output signal.
• An encoder is a device which converts familiar numbers or characters
or symbols into a coded format. It accepts the alphabetic characters
and decimal numbers as inputs and produces the outputs as a coded
representation of the inputs.
• It is a combinational circuit that performs the opposite function of a
decoder.
• These are mainly used to reduce the number of bits needed to
represent given information.
• Depending on the number of input lines,
digital or binary encoders produce the output
codes in the form of 2 or 3 or 4 bit codes.
• An encoder is a multiplexer without its single
output line.
• It is a combinational logic function that has 2n
(or fewer) input lines and n output lines, which
correspond to n selection lines in a multiplexer.
• The n output lines generate the binary code
for the possible 2n input lines.
4 – to – 2 Bit Binary Encoder
An 8-to-3 Priority Encoder
8-to-3 Priority Encoder
• 8-to-3 priority encoder with inputs y0 through y7.
• If input yi is 1 and the other inputs are 0, then the a, b, c outputs represent a binary
number equal to i.
• For example, if y3 = 1, then abc = 011.
• If more than one input can be 1 at the same time, the output can be defined using a
priority scheme.

• The truth table uses the following scheme:

• If more than one input is 1, the highest numbered input determines the output.
• For example, if inputs y1, y4, and y5 are 1, the output is abc = 101.

• The X’s in the table are don’t-cares; for example, if y5 is 1, inputs y0 through y4 are neglected.

• Output d is 1 if any input is 1, otherwise, d is 0.

• This signal is needed to distinguish the case of all 0 inputs from the case where only y0 is 1.
 Decimal-to-BCD Encoder

• Y3 = D8 + D9
• Y2 = D4 + D5 + D6 + D7
• Y1 = D2 + D3 + D6 + D7
• Y0 = D1 + D3 + D5 + D7 + D9
Variable Entered Map
Implement using multiplexer F (A, B, C, D) =
(1, 3, 4, 11, 12, 13, 14, 15) using single 8 to 1
Multiplexer
Variable Entered Map
• Step 1: Treat all variables in the cells as '0' and get SOP term

• Step 2: Make one variable of cell as 1 with previous 1s as don't cares and get
SOP term

• Step 3: Multiply term with variable

• Step 4: Repeat step 2 and 3 until all variables are covered.

• Step 5: SOP of VEM is sum of all VEM's obtained earlier

A B C D Y VEM
CD
0 0 0 0 0
D
00 01 11 10

0 0 0 1 1 00 0 1 1 0
0 0 1 0 0
0 0 1 1 1
D 01 X X 1 1
AB
0 1 0 0 X
X 11 0 0 0 1
0 1 0 1 X
0 1 1 0 1
10 0 0 0 0
0 1 1 1 1
1
1 0 0 0 0
0
𝒀 = 𝑨 𝑫+ 𝑩 𝑪 𝑫
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
0
BC
1 1 0 0 0
0
00 01 11 10

1 1 0 1 0
A 0 D D 1 X
1 1 1 0 1
1 1 1 1 0
D’ 1
0 0 D’ 0

K map for VEM

Example 1
BC 2
00 01 11 10
A
0 D D 1 X
1 0 0 D’ 0
1

Group 1 : A’B
Group 2: A’D
Group 3: BCD’

SOP : A’B + A’D + BCD’

Shortcut Method
Loop/group the cells having
1. 1s and 1s
2. Ds and Ds
3. 1's and Ds or 1's and D's
4. D's and D's

Multiply above point 2, 3, 4's with Variable

 F(A, B, C, D) = ∑ (0,3,4,8,9,12,13,15)
A B C D Y VEM
CD
0 0 0 0 1 00 01 11 10

0 0 0 1 0 00 1 1
0 0 1 0 0
01 1
0 0 1 1 1 AB

0 1 0 0 1 11 1 1 1
0 1 0 1 0 10 1 1
0 1 1 0 0
0 1 1 1 0 𝒀 = 𝑨 𝑩 𝑪𝑫+ 𝑨𝑩𝑫 +𝑪 𝑫 + 𝑨 𝑪
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
Example 2 - VEM
3

BC
00 01 11 10 1
A
0 D’ D 0 D’
1 1 0 D 1 2

Group 1 : C’D’
Group 2: ABD
Group 3: A’B’CD
Group 4: AC’

Y : C’D’ + ABD + A’B’CD + AC’

End