EE1701 EMBEDDED SYSTEMS

UNIT I INTRODUCTION TO EMBEDDED SYSTEMS

Introduction to Embedded Systems –Structural units in Embedded processor ,

selection of processor & memory devices- DMA – Memory management
methods- Timer and Counting devices, Watchdog Timer, Real Time Clock, In
circuit emulator, Target Hardware Debugging.

UNIT II EMBEDDED NETWORKING

Embedded Networking: Introduction, I/O Device Ports & Buses– Serial Bus
communication protocols RS232 standard – RS422 – RS 485 - CAN Bus -Serial
Peripheral Interface (SPI) – Inter Integrated Circuits (I2C) –need for device
drivers.
 What is Embedded System?
Embedded System
any device that includes a computer but is not itself a
general purpose computer
h/w and s/w - part of some larger systems and
expected to function without human intervention
respond, monitor, control external environment using
sensors and actuators
embedding a computer - but not for general purpose
Applied Computer System
Includes analog interface to the external world
 Characteristics of Embedded System

 sophisticated functionality - differ by appliances

 RT operation (not always necessary)
 low manufacturing cost
 application dependent processor and not GPP
 Restricted memory
 low power
 critical in battery operated devices
 excessive power consumption increases system cost even in wall powered
devices
 Manufacturing cost
 Non-Recurring Engineering cost (NRE) – cost for design and development
 cost of production and marketing each unit
 production cost should be taken care when targeting mass market
 Ex: AU Versus low cost cell phone
 Technology choice depends on no of units plan to produce
 Characteristics of Embedded System

 RT operation
 finish operations by deadlines

 HRTS - missing deadline is catastrophic

 automated missile launch system

 SRTS - missing deadline degrades performance

 playing video - missed decoded frame

 many systems are multi rate - inputs from external world comes at different rates
 Constraints in Embedded Systems
Tightly constrained than traditional software systems
• Cost
• Cannot have high end or fast processor
• Cannot have more memory – processor footprint should be less
• Size
• Processor footprint should be less
• Ex: gun stabilization control for Arjuna Tank in Defence
• Cooling requirements + Processor should take less space
• Performance
• Ex: Digital camera snaps, Mobile phone address book contact list etc.,
• Power
• Battery power products – Mobile phones
• Optimized power saving algorithms and operating modes – reduce power dissipation
• SW Program size + # of instructions – affect processor’s energy consumption
• Available System Memory and Processor Speed
• Limited power dissipation when running system continuously
• Reactive and Real Time – Adaptive cruise control and radar missile detection systems
 Types of Embedded System
similar to general computing
PDA, video games, STP box, ATM
Since the functionalities is subset of PC functionalities
i/0 based
no sensing of ext environment and no control of actuators
more like general purpose
respond to users input

Control systems
sensing and actuating - is a specific job
feed back control of RT systems
vehicle engines - fuel injection control
flight control
nuclear reactors
 Types of Embedded System
signal processing
core job is processing of signals
radar
sonar
DVD players

communication and networking

cellular phones,
internet appliances
web enabled vending m/c
Structural units in processor
• Processor is the heart of an embedded system.
• It is the basic unit that takes inputs and produces an output after
processing the data.
• For an embedded system designer, it is necessary to have the
knowledge of both microprocessors and microcontrollers.

Processors in a System
Program Flow Control Unit (CU)
Execution Unit (EU)
Buses• Internal and external buses interconnect the processor internal units
with the external system memories, I/O devices and all other system
elements
• Address, data and control buses
• Address bus carries the address from the MAR to memory as well as
to the IO devices and the other units
• Data bus carries the bytes of an instruction or data from or to an
address. Address is determined by the MAR.
• Control bus carries the control signals to or between the processor
and memory
• Bus Interface Unit interface the processor’s internal units with
external buses
 MDR, MAR
• MDR - holds the byte or word to be fetched from external memories or IO
address.
• MAR - holds the address of the byte or word to be fetched from ext.
memories.
• Processor issues the address of instruction or data to MAR before it initiates a
fetch cycle
PROGRAM COUNTER

This is a 16-bit register accessible to the user. It is a special purpose register

and it always contains the address of the next instruction to be fetched from
the program memory and executed by the CPU in a program sequence.
Thus the program counter keeps the track of the program execution in which
instructions are to be executed next.
 STACK POINTER
• The stack is a storage area of the processor.
• It consists of number of sequential and RWM locations in which microprocessor
saves the internal register contents during subroutine calls and interrupts so
that they will not be changed or destroyed by a subroutine.
STACK POINTER REGISTER
1.The stack pointer always points to the top of the stack up to which it is full with
relevant data.
2. Storing or saving the data from the registers on stack is known as PUSH
operation.
3. The restoring or reading data from the stack onto certain internal registers is
known as POP operation.
4. The stack operates on Last-in-first-out (LIFO) basis.
5. The stack pointer can be initialized to the bottom of the stack but bottom of the
stack cannot be utilized to store any useful data.
6. It is for the user to see that the program area does not overlap with stack area.
MMU, PFCU
• MMU - Manages the memories such that the
instruction and data are readily available for
processing
• Pre Fetch Control Unit – Controls the fetching of data
into the I cache and D cache in advance from the
memory units. The instructions and data are delivered
when needed to the processor’s execution units. The
processor does not have to fetch data just before
executing the instruction
Registers
• ARS (Application Register Set): Set of on-chip registers for use in the
application program. Register set ─ also called file and associates an
ALU or FLPU
• Register window- a subset of registers with each subset storing static
variables and status words of a task or program thread. Changing
windows help in fast context-switching in a program.

ALU, FLPU
ALU and FLPU (Arithmetic and Logic operations Unit and
Floating Points operations Unit). FLPU associates a FLP register
set for operations.
 Caches
• Instruction, Data and Branch Target Caches and associated PFCU (Prefetch
control unit) for pre-fetching the instructions, data and next branch target
instructions, respectively.
• Multi-way Cache – Example- 16 kB, 32-way Instruction cache with 32 byte block
for data and 16 kB in ARM
• Cache block – Enables simultaneous caching of several memory locations of a
set of instructions
AOU (Atomic Operations Unit )
An instruction is broken into number of processor-instructions called
atomic operations (AOs), AOU finishes the AOs before an interrupt of
the process occurs - Prevents problems arising out of incomplete
processor operations on the shared data in the programs
Features in advanced architectures
• Instruction, Branch Target and Data Cache
• Memory-Management unit (MMU)
• Floating Point Processing unit
• System Register Set

Features in advanced architectures

• Floating Point Register Set
• Pre-fetch Control Unit for data into the Iand D-caches
• Instruction level parallelism units (i) multistage pipeline (ii) Multi-line
superscalar processing
RISC architecture
• Executing most instructions on in a single clock cycle execution per
instruction (by hardwired implementation of instructions)
• Using multiple register-sets or register windows or files and
• Greatly reducing ALU dependency on the external memory accesses
for data due to the reduced number of addressing modes provided for
the ALU instructions.

RISC Load and store architecture

• Before ALU operations, the operands are loaded into the registers and
similarly the write back result is in the register and then stored at the
external memory addresses
 Memory Management
Frame A fixed-length block of main memory.

A fixed-length block of data that resides in secondary

Page memory (such as disk). A page of data may temporarily be
copied into a frame of main memory.

A variable-length block of data that resides in secondary

memory.
An entire sessgment may temporarily be copied into an
Segment available region of main memory (segmentation) or the
segment may be divided into pages which can be individually
copied into main memory (combined segmentation and paging).
Memory
Management
Requirements
 Memory management is intended to
satisfy the following requirements:
 Relocation
 Protection
 Sharing
 Logical organization
 Physical organization
 Relocati
on
 Programmers typically do not know in advance which
other programs will be resident in main memory at the
time of execution of their program
 Active processes need to be able to be swapped in and
out of main memory in order to maximize processor
utilization
 Specifying that a process must be placed in the
same memory region when it is swapped back in
would be limiting
 may need to relocate the process to a
different area of memory
Process control
Process Control Block
information Entry point
to
program
Branch
Program instruction

Increasing
address
values
Reference
to data

Data

Current top
of stack
Stack

Figure 7.1 Addressing Requirements for a Process

 Protecti
on
 Processes need to acquire permission to reference memory
locations for reading or writing purposes
 Location of a program in main memory is unpredictable
 Memory references generated by a process must be
checked at run time
 Mechanisms that support relocation also support protection
 Shari
ng
 Advantageous to allow each process access to the
same copy of the program rather than have their
own separate copy
 Memory management must allow controlled access
to shared
areas of memory without compromising protection
 Mechanisms used to support relocation
support sharing capabilities
 Logical
Organization
 Memory is organized as
linear
Programs are written in modules
• modules can be written and compiled independently
• different degrees of protection given to modules
(read-only,
execute-only)
• sharing on a module level corresponds to the
user’s way of viewing the problem
 Segmentation is the tool that most readily
satisfies
requirements
 Physical
Organization

Cannot leave the Memory available Programmer does

programmer with for a program plus not know how
the responsibility its data may be much space will
to manage insufficient be available
memory

overlaying allows
various modules to
be assigned the
same region of
memory but is time
consuming to
program
DMA
• During any given bus cycle, one of the system
components connected to the system bus is given
control of the bus.
• This component is said to be the master during that
cycle and the component it is communicating with is
said to be the slave.
• The CPU with its bus control logic is normally the master,
but other specially designed components can gain
control of the bus by sending a bus request to the CPU.
• After the current bus cycle is completed the CPU will
return a bus grant signal and the component sending
the request will become the master.
DMA
• Taking control of the bus for a bus cycle is called cycle stealing.
• Just like the bus control logic, a master must be capable of placing
addresses on the address bus and directing the bus activity during a
bus cycle.
• The components capable of becoming masters are processors (and
their bus control logic) and DMA controllers.
• Sometimes a DMA controller is associated with a single interface, but
they are often designed to accommodate more than one interface.
DMA
• The 8086 microprocessor receives bus requests through its HOLD
pin and issues grants from the hold acknowledge (HLDA) pin.
• A request is made when a potential master sends a 1 to the
HOLD pin.
• Normally, after the current bus cycle is complete the 8086 will
respond by putting a 1 on the HLDA pin.
• When the requesting device receives this grant signal it becomes
the master.
• It will remain master until it drops the signal to the HOLD pin, at
which time the 8086 will drop the grant on the HLDA pin.
• ne exception to the normal sequence is that if a word, which
begins at an odd address is being accessed, then two bus cycles
are required to complete the transfer and a grant will not be
issued until after the second bus cycle.
DMA
• When a DMA controller becomes master it places an
address on the address bus and sends the interface the
necessary signals to cause it to put data on, or receive
data from, the data bus.
• Since the DMA controller determines when the bus
request is dropped, it can return control to the CPU
after each data byte is transferred and then request
control again when the next data byte is ready, or it
can retain control until the entire block is moved.
• The former is the usual case because this allows the
CPU to continue its work until the next data byte is
available.
DMA
DMA
1. The interface sends the DMA controller a request for DMA service.
2. A Bus request is made to the HOLD pin (active High) on the 8086 microprocessor and
the controller gains control of the bus.
3. A Bus grant is returned to the DMA controller from the Hold Acknowledge (HLDA) pin
(active High) on the 8086 microprocessor.
4. The DMA controller places contents of the address register onto the address bus.
5. The controller sends the interface a DMA acknowledgment, which tells the interface to
put data on the data bus. (For an output it signals the interface to latch the next data
placed on the bus.)
6. The data byte is transferred to the memory location indicated by the address bus.
7. The interface latches the data.
8. The Bus request is dropped, the HOLD pin goes Low, and the controller relinquishes the
bus.
9. The Bus grant from the 8086 microprocessor is dropped and the HLDA pin goes Low.
10. The address register is incremented by 1.
11. The byte count is decremented by 1.
12. If the byte count is non-zero, return to step 1, otherwise stop.
Direct Memory Access Controller (DMAC) options for data
transfer

1) Cycle Steal:
A read or write signal is generated by the DMAC, and the I/O device either generates
or latches the data. The DMAC effectively steals cycles from the processor in order to
transfer the byte, so single byte transfer is also known as cycle stealing.
2) Burst Transfer:
To achieve block transfers, some DMAC's incorporate an automatic sequencing of the
value presented on the address bus. A register is used as a byte count, being
decremented for each byte transfer, and upon the byte count reaching zero, the DMAC
will release the bus. When the DMAC operates in burst mode, the CPU is halted for the
duration of the data transfer.
3) Hidden DMA:
It is possible to perform hidden DMA, which is transparent to the normal operation of
the CPU. In other words, the bus is grabbed by the DMAC when the processor is not
using it. The DMAC monitors the execution of the processor, and when it recognises
the processor executing an instruction which has sufficient empty clock cycles to
perform a byte transfer, it waits till the processor is decoding the op code, then grabs
the bus during this time. The processor is not slowed down, but continues processing
normally. Naturally, the data transfer by the DMAC must be completed before the
processor starts
Timer

• Timer is nothing but a simple binary

counter that can be configured to count
clock pulses(Internal/External).
• Once it reaches the Max value, it will roll
back to zero setting up an OverFlow flag
and generates the interrupt if enabled.
• Timer enable – To activate a timer
• Timer stop – To stop timer
• Timer start – To start timer
• Prescaler - electronic counting circuit used to reduce
a high frequency electrical signal to a lower frequency
by integer division. The prescaler takes the basic timer
clock frequency and divides it by some value before
feeding it to the timer, according to how the prescaler
register(s) are configured. The prescaler values that
may be configured from 1 to 2^P, where P is the
number of prescaler bits.
• Up count – Increment
• Down count – Decrement
• Load enable – To enable loading of a value at a reg into memory
• Time out – To enable a signal when the timer overlows

Timer Block diagram

Modes of operation (8051)
 Watch Dog Timer (WDT)

A Watch Dog Timer is an additional timer that does

a monitoring job resets the system.
“Self- Reliant System”
 WDT
• A Watch Dog Timer is an additional timer that does a
monitoring job resets the system.“Self- Reliant System”
• Software getting stuck in infinite loop.
• Dead lock
• Noise Voltage is some pin leads to – Wrong triggering
• it can be loaded with a count which decrements down to
zero.
• 8051 doesn't have inbuilt WDT but PIC ,ARM
microcontrollers have WDT.
• Reset by WDT is called as “Soft Reset or Warm Boot”
 Real Time Clock
• A real-time clock (RTC) is a computer clock (most often in the form of an integrated circuit)
that keeps track of the current time.
• A common RTC used in single-board computers is the Maxim Integrated DS1307.
• RTCs often have an alternate source of power, so they can continue to keep time while the
primary source of power is off or unavailable.
• This alternate source of power is normally a lithium battery in older systems, but some newer
systems use a supercapacitor, because they are rechargeable and can be soldered.
• The alternate power source can also supply power to battery backed RAM.
• Most RTCs use a crystal oscillator, but some have the option of using the power line frequency
. In many cases, the oscillator's frequency is 32.768 kHz. This is the same frequency used in
quartz clocks and watches, and for the same reasons, namely that the frequency is exactly 215
cycles per second, is a convenient rate to use with simple binary counter circuits.
• Many commercial RTC ICs are accurate to less than 5 parts per million. In practical terms, this
is good enough to perform celestial navigation, the classic task of a chronometer. In 2011,
Chip-scale atomic clocks were invented. Although more expensive, they keep time within 100
nanoseconds.
DS 1307
 RTC
• Pin 1, 2: Connections for standard 32.768 kHz quartz crystal. The internal
oscillator circuitry is intended for operation with a crystal having a specified
load capacitance of 12.5pF. X1 is the input to the oscillator and can
alternatively be connected to an external 32.768 kHz oscillator. The output of
the internal oscillator, X2 is drifted if an external oscillator is connected to X1.
• Pin 3: Battery input for any standard 3V lithium cell or other energy source.
Battery voltage should be between 2V and 3.5V for suitable operation. The
nominal write protect trip point voltage at which access to the RTC and user
RAM is denied is set by the internal circuitry as 1.25 x VBAT nominal. A
lithium battery with 48mAhr or greater will backup the DS1307 for more than
10 years in the absence of power at 25ºC.
 RTC
• Pin 4: Ground.
• Pin 5: Serial data input/output. The input/output for the I2C serial interface is the SDA,
which is open drain and requires a pull up resistor, allowing a pull up voltage upto 5.5V.
Regardless of the voltage on VCC.
• Pin 6: Serial clock input. It is the I2C interface clock input and is used in data
synchronization.
• Pin 7: Square wave/output driver. When enabled, the SQWE bit set to 1, the SQW/OUT
pin outputs one of four square-wave frequencies (1Hz, 4 kHz, 8 kHz, and 32 kHz). This is
also open drain and requires an external pull-up resistor. It requires application of either
Vcc or Vb at to operate SQW/OUT, with an allowable pull up voltage of 5.5V and can be
left floating, if not used.
• Pin 8: Primary power supply. When voltage is applied within normal limits, the device is
fully accessible and data can be written and read. When a backup supply is connected to
the device and VCC is below VTP, read and writes are inhibited. However at low voltages,
the timekeeping function still functions.
 In circuit emulator (ICE)
• hardware interface that allows a programmer to change or debug the
software in an embedded system.
• To alter the contents of a register, memory, or the state of your I/O
• ICE is a debugging tool that allows you to access a target MCU for in-
depth debugging.
• temporarily installed between the embedded system and an external
terminal or personal computer so that the programmer can observe and
alter what takes place in the embedded system, which has no display or
keyboard of its own.
• The ICE usually has a connector that fits the CPU socket in the system.
• If the connector provided with the ICE does not match the socket in the
system, a suitable adapter can usually be found.
 ICE
• An ICE can assist design engineers in product development, and also
assist programmers or end users in product upgrading, modification,
or maintenance.
• Using an ICE, technicians can test new, revised, or modified
programming elements on an embedded system's hardware
without committing to the change.
 ICE
• ICE consists of a hardware board with accompanying software for the host
computer.
• The ICE is physically connected between the host computer and the target
MCU.
• The debugger on the host establishes a connection to the MCU via the ICE.
• ICE allows a developer to see data and signals that are internal to the MCU,
and to step through the source code (e.g., C/C++ on the host) or set
breakpoints; the immediate ramifications of executed software are observed
during run time.
Advantages

ICE can always maintain control of the program

- Interrupt cannot be masked


Works even if system ROM is broken


Generally the best solution
 Disadvantage
• The ICE hardware must be physically connected to the MCU. As chips get
smaller, adapters can help in connecting tiny surface mounted chips to the
ICE.
• ICE devices come with a learning curve, especially if there will be complex
debugging functions, for example, flagging when a register holds a specific
value after a conditional branch is taken, etc.
• As high-performance chips have come down in price, the accessibility for
debugging with ICE has faded to the point where ICE hardware has become
rare for anyone who is not still using an 8051-era MCU.
• ICE require fast connectivity and loads of memory, so lower level MCUs (8-,
-16-bit and MHz, not GHz) are more likely to have an ICE option available.
• highly integrated chips may create fewer bugs versus off-chip, board-
mounted EEPROMS and interfaces, for example.
 Target Hardware Debugging
Software debugging:
HW debugging tools
• Lens

• Multimeter
• Digital CRO

• Logic Analyzer
• Function generator