Text3 Chap4

• The basic strategy of power gating is to
provide two power modes:

• a low power mode and an active mode.
• The goal is to switch between these modes at
the appropriate time and in the appropriate
manner to maximize power savings while
minimizing the impact to performance
• power gating is more invasive than clock-
gating in that it affects inter-block interface
communication and adds significant time
delays to safely enter and exit power gated
modes
• the amount of leakage power savings that is
possible
• the entry and exit time penalties incurred
• the energy dissipated entering and leaving
such leakage saving modes
• the activity profile (proportion and frequency
of times asleep or active)
• SLEEP events initiate entry to the low power
mode
• WAKE events initiate return to active mode
Power gating design
The critical issues in power gating include
•the design of the switching network

•the power gating controller.
•We also need to determine when and where to insert retention
flops and isolation cells.
Switching Fabric Design
• The first architectural issue is whether to switch VDD (with a
“header” switch) or to switch VSS (with a “footer” switch) or
both.
• A number of academic papers have been published on this
subject.
• Some authors advocate both P-channel “Header” switches
gating the VDD supply and N-channel “Footer” switches gating
the VSS ground.
• two such high-VT power switches in series with the gate cause
a more significant IR voltage drop in the supply as seen by the
gate. This drop in turn causes increased delays for the gates in
the design.
External power gating (switching a power supply external to the chip) is only practical
for switching VDD. VSS is usually common on the board for a variety of reasons,
including providing a conduction path for ESD
The arguments in favor of the footer cell approach – that is, switching VSS – are
based in the electrical characteristics of the switches themselves
• With a header-style switch fabric, the internal nodes
and outputs of a power gated block collapse down
towards the ground rail when the switch is turned off.
• With a footer-style switch fabric the internal nodes
and outputs all charge towards the supply rail when
the switch is turned off.
• Note that here is no guarantee that the power gated
nodes will ever fully discharge to ground or fully
charge to the supply.
• Instead, an equilibrium is reached when the leak-age
current through the switches is balanced by the sub-
threshold leakage of the switched cells. This is one of
the reasons why isolation cells are required on outputs
of power gated blocks
Recommendations:
• Switch the supply rail or ground, rather than both, in order to minimize the IR drop.
• Decide early on in the design phase whether header or footer switches most naturally
fit with the system design.
• Header switches may be the most appropriate choice for switches if external power
gating will also be used on the chip.
• Header switches may be the most appropriate choice for switches if multiple power rails
and/or voltage scaling will be used on the chip.
Controlling the Switching Fabric
A key concern in controlling the switching fabric is to limit the
in-rush current when power to the block is switched on.
Excessive in-rush current can cause voltage spikes on the supply, possibly
corrupting registers in the always-on blocks, as well as retention
registers in the power gated block
Controlling the Switching Fabric
Signal Isolation
• need to be sure that powering down the
region will not result in crowbar current in any
inputs of poweredup blocks.
• Also need to be sure than none of the floating
outputs of the powerdown block will result in
spurious behavior in the power-up blocks.
Signal Isolation Techniques
• The basic approach to controlling the outputs
of powered down blocks is to use an isolation
cell to clamp the output to a specific, legal
value.
• There are three basic types of isolation cell:
those that clamp the signal to “0”;
• those that clamp it to “1”;
• and those that latch it to the most recent value.
Signal Isolation Techniques
These clamp gates add delay to the signals

they are isolating. For some critical paths this
added delay may not be acceptable – for
example on cache memory interfaces
Output or Input Isolation
Recommendations and Pitfalls for Isolation
Power Control Sequencing
Power Control Sequencing Without
Retention
Power Control Sequencing WithRetention
A Power Gating Example
The SALT technology demonstrator project

provided a platform for testing the approaches
to power gating and state retention
The SALT chip is implemented in 90nm generic technology and contains an
ARM processor,
an AMBA bus
set of peripherals,
and a Synopsys USB OTG digital core and PHY.
The ARM core and the USB core are independently power gated.
The ARM core uses full state retention; the USB uses partial state retention. Both the ARM
core and the USB use switching fabrics of header switches; thus they switch VDD and use a
common ground
For the SALT project, the processor uses four
low-power modes.
In all modes, the power controller generates a
SLEEP signal to enter the low power mode and
the WAKE signal to exit.
In order of increasing leakage savings – and
increasing time to power up and power down
– the modes are:
Design Partitioning

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• The basic strategy of power gating is to

provide two power modes:

•the design of the switching network

These clamp gates add delay to the signals

The SALT technology demonstrator project

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