7.troublesht Low Cov

Tessent: Scan and ATPG
Module 7
Troubleshooting Low
Test Coverage
Objectives
Upon completion of this module, you will be able to:
 Use the REPort STAtistics command to:

 List untestable fault categories.
 Determine untestable fault classifications.
 Use the Browser to locate instances within the design.
 Use the REPort STatistics -Hierarchy command to
identify blocks of low coverage.
 Determine the cause of ATPG Untestable (AU) faults.
 Address aborted faults.
7-2 • Tessent: Scan and ATPG: Troubleshooting Low Test Coverage Copyright © 1999-2009 Mentor Graphics Corporation
Sources of Low Coverage
 A fault site must be
 Controlled
 Observed
 Differences must be seen between Good and Fault
simulations.
 Too many AU (Atpg_untestable), UC (Uncontrolled), UO
(Unobserved), and AAB (Atpg_aborted) faults cause coverage
losses.
Troubleshooting Areas of Low Coverage
 Troubleshoot areas of low coverage:
 Assess the problem.
– Determine the larger design blocks.
– Determine which blocks are reporting low coverage.
– Determine untestable fault categories.
 Determine why ATPG classified faults as untestable.
– Determine why faults are classified ATPG Untestable (AU).
– Determine why faults are classified as Unobserved (UO) and
Uncontrolled (UC).
 Analyze the design fault by fault.
– Use DFTVisualizer or applicable commands and options.
 Debug the design.
Use DFTVisualizer to Troubleshoot Low Coverage
DFTVisualizer Browser Window
Browser controls
 The Browser window is used to:

 Display design hierarchy from the top level to
the lowest gate.
 Select specific instances and pins.
 View fault types.
 View DRCs.
 View coverage data:
– Test.
– Fault.
– ATPG Effectiveness.
 Display library models.
Hierarchy, Library, and Clocks tabs
 Display clocks in the design.
 Command:
open visualizer –display browser
Displaying Test Coverage in the Browser Window:
Hierarchy Tab
Click the tc button
in the toolbar.
Click the tc button int the toolbar or choose Data > Coverage Data > Test Coverage from the menu.
Coverage Metrics in the Browser Window: Hierarchy Tab
Total Undetected Faults by

faults faults category
Coverage Metrics in the Browser Window: Hierarchy Tab
(Cont.)
Coverage
DRC by Test Loss Fault ATPG
category Coverage Coverage Effectiveness
Coverage Metrics in the Browser Window: Library Tab
Coverage Metrics in the Browser Window: Clocks Tab
Clocks are displayed in
descending order of test
coverage.
Signals Window
 The Signals window lets you

view ports and signals for
selected instances in the
Browser window.
 Access by selecting Windows >
Signals from the menu.
Assessing the Problem
 Determine which blocks are reporting low coverage.
 Use REPort STAtistics command
SETUP>REPort STAtistics –Hierarchy -LEVel integer
TOP/
90% 20%
99% 60% 80%
Assessing the Problem (Cont.)
Instance Pathname
Determine blocks with coverage issues. Use the Browser to

display the instance inside the hierarchy.
Assessing the Problem (Cont.)
 Use the REPort STAtistics command to determine instance
coverage and number of faults and their classification.
Fault Grouping
Faults Classified as ATPG Untestable
 ATPG untestable faults (AU) are caused by any one of the
following:
 Constraints (pin, cell and ATPG).
– Constraints prevent Tessent FastScan from generating a pattern to
detect the fault.
 Non-scan flip-flop and insufficient clock sequential depth.
 Blocking conditions from black boxes, other tied or constrained
logic.
 Insufficient processing resources given to ATPG with the abort
limit.
 An AU fault is testable because it has not been proven
untestable—only undetected.
Faults Classified as Undetectable
 Undetected faults cannot be proven untestable or AU:
 Uncontrollable (UC).
– Faults sites that cannot be set to a known value (0,1).
 Unobservable (UO).
– Faults effects that cannot be propagated to an observe point.
Aborted Faults
 Belong to the Undetected (UD) fault class.
 May be caused by a high number of UC or UO faults.
 Tessent FastScan terminates effort to find patterns after a certain
amount of iterations.
 Certain faults may be detected if abort limit is increased.
– Use the SET Abort Limit command to increase abort limit OR
– Use ‘create pattern’ to increase the abort limit automatically.
 Use REPort ABorted Faults to display and identify the
cause of aborted faults.
Addressing Aborted Faults
 Addressing aborted faults:

 View the statistics report to
determine if many aborted
faults exist.
Addressing Aborted Faults (Cont.)
 Use REPort ABorted Faults to generate a summary of

the aborted faults.
Use REPort ABorted Faults

format_type to display a specific
type of aborted fault.
Addressing Aborted Faults (Cont.)
 Set a higher abort limit if there are many aborted faults.
SETUP> SET ABort Limit 300
Use the number of reported

ATPG> create patterns
aborted faults as the benchmark
No faults in fault list. Adding all faults... to determine abort limit.
// ------------------------------------------------------------------------
// Simulation performed for #gates = 35 #faults = 52
// system mode = ATPG pattern source = internal patterns
// ------------------------------------------------------------------------
// #patterns test #faults #faults # eff. # test process RE/AU/abort
// simulated coverage in list detected patterns patterns CPU time
// deterministic ATPG invoked with abort limit = 30
// --- ------ --- --- --- --- 0.01 sec 5/6/3
// --- ------ --- --- --- --- 0.01 sec 5/6/3
The three additional fields are cumulative and broken down as follows:
5/6/3
Aborted Faults
Redundant Faults
ATPG Untestable Faults
Bus Contention
 Bus contention causes uncontrollable (UC) faults.
 Tessent FastScan generates patterns to detect UC faults.
 If pattern simulates effectively, the fault becomes detected by simulation (DS).
 If pattern is rejected, the fault remains UC and other patterns may detect it.
 By default, patterns will be rejected if pattern simulation results in bus
contention.
// Warning: There were 1 BUS gates which may have possible contention. (E10)
// ATPG bus checking results: pass=0, bidi=0, fail=1, abort=0, CPU time=0.00.
// command: rep drc rule E10
// Warning: BUS gate /Y (9) has possible contention on drivers 8 and 7. (E10-1)
ATPG> create patterns

No faults in fault list. Adding all faults...
// ------------------------------------------------------------------------
// Simulation performed for #gates = 35 #faults = 52
// system mode = ATPG pattern source = internal patterns
// ------------------------------------------------------------------------
// #patterns test #faults #faults # eff. # test process RE/AU/abort
// simulated coverage in list detected patterns patterns CPU time
// deterministic ATPG invoked with abort limit = 30
// --- ------ --- --- --- --- 0.01 sec 0/6/0
// --- ------ --- --- --- --- 0.01 sec 0/6/0
// Warning: Contention on (9), number patterns rejected = 1.
// 32 93.48% 0 52 5 5 0.01 sec
Addressing Bus Contention
 Avoid contention during pattern generation:
 SETUP> SET COntention Check ON -ATPG
– Tessent FastScan generates patterns that force buses to non-
contention.
– If pattern does not detect fault, it becomes AU.
– Tessent FastScan stops the pattern generation process if there is a
contention that cannot be fixed.
– Note: You do not need to use the –ATPG switch if using ATPG Expert
to create patterns.
 Use create patterns and let the tool choose the best
contention check for your design.
 Analyze what caused the contention:
 SETUP> ANAlyze BUs <gate_id#> -Prevention |
-Exclusivity | -Zstate
– Prevention—ability of the tool to attain a state of non-contention.
– Exclusivity—allows only one driver to force a signal onto a bus.
This is the default.
– Zstate—Specifies to the tool to analyze the bus gate for its ability to
attain a high-impedance (Z) state.
Addressing Bus Contention (Cont.)
 Specify to the tool to perform contention checking:
SET COntention Check CAPture_clock –CATpg
–VVerbose -Error
 Stops ATPG process on a 32 bit or 64 bit pattern.
 Displays patterns failing due to contention.
 CAPture_clock performs bus contention checking for the
complete cycle
 -CATpg tells the tool to use additional ATPG effort during
pattern generation.
– Must use with CAPture_Clock.
 -VVerbose reports every reason for each pattern rejected.
 -Error enables you to debug contention by displaying an error
message and stopping the simulation if contention occurs.
 Note: You do not need to use the -CATpg switch if using ATPG
Expert to create patterns.
Types of Bus Contention
 Determine type of contention:
 E4 violations:
– Contention during procedures.
– Often due to unknown values at bidi pins.
– Usually fixed by force <bus> Z in test_setup and load_unload at event
0.
 E10 violations are contention after the scan chain is loaded.
 Use the SET DRc Handling E10 Atpg_analysis command:
– Determines buses that do not cause contention.
– Simplifies pattern generation to avoid bus contention.
Debugging Bus Contention
 The following transcript is an example of a dofile used for
debugging bus contention:
ATPG> REPort DRC Rule E10
ATPG> ANAlyze Bus <gate_id#>
( Use various arguments with this command to determine
source of E4 or E10 contentions.)
ATPG> SET GAte Report CONstrain_value
ATPG> REPort Gates <gate_id#>
(Select gate violating E4 or E10 rule.)
Debugging Bus Contention With DFTVisualizer
The problem lies with the two tri-state
drivers (TSD), which can be enabled
simultaneously, thus enabling the
possibility of driving different values.
SETUP> analyze drc violation e10-1
Debugging Bus Contention With DFTVisualizer (Cont.)
Use DFTVisualizer to help trace
to the source of the E10 violation.
TieX, Tie0, Tie1 (D5)
 A D5 violation occurs when memory elements are not
identified as part of a scan chain.
 Non-scan elements are modeled as tie-X, unless set to a
stable value (Tie0, Tie1).
 If too many TieX gates, increase the clock sequential depth.
 SETUP> SET PAttern Type -Sequential 2
– The nonscan elements will then be treated as TieX, Tie0, Tie1, Init-X,
Init-0, or Init-1. Refer to DRC rule check D5.
// ---------------------------------------------------------------------------
// 143 non-scan memory elements are identified.
// ---------------------------------------------------------------------------
// 8 non-scan memory elements are identified as TIE-0. (D5)
// 10 non-scan memory elements are identified as TIE-1. (D5)
// 1 non-scan memory element is identified as TIE-X. (D5)
// 3 non-scan memory elements are identified as INIT-0. (D5)
// 3 non-scan memory elements are identified as INIT-1. (D5)
// 118 non-scan memory elements are identified as INIT-X. (D5)
// ---------------------------------------------------------------------------
 ATPG> create patterns

– The tool will increase the depth automatically to increase coverage.
Fault-By-Fault AU Debugging: Set Gate Report Command
 Use the SET GAte Report COnstrain_value command to
display constrained and forbidden values.
 The constrained value report provides three fields:
 CV
 FV
 B
“B” blocked no path to propagate fault, “-” not blocked
CV/FV/B
Constrained Value
Forbidden Value
Set Gate Report Constrain_Value Command in
DFTVisualizer
constrained value/forbidden value/blocked value
Fault-By-Fault Debugging: Report Faults Command
 Use the Report Faults -Class class_type command to
narrow focus of the report to the fault type you want.
 Can be used with any fault type.
 Use it as a starting point to analyzing faults.
ATPG> REPort Faults –Class UC
1 UC /p1/fpu1/u4/U2711/Y
0 EQ /p1/fpu1/u4/U2711/A1
0 EQ /p1/fpu1/u4/U2711/A0
0 EQ /p1/fpu1/u4/U3534/Y
1 EQ /p1/fpu1/u4/U3534/A1
1 EQ /p1/fpu1/u4/U3534/A0
1 EQ /p1/fpu1/u4/U1302/Y
1 EQ /p1/fpu1/u4/U1302/A1
1 EQ /p1/fpu1/u4/U1302/A0
1 EQ /p1/fpu1/u4/U3536/Y
0 EQ /p1/fpu1/u4/U3536/A
0 EQ /p1/fpu1/u4/U3535/Y
Fault-By-Fault UC Debugging: Analyze Fault Command
 Use the ANAlyze FAult command to identify why a fault is not

detected.
 Performs fault analysis and displays circuitry in DFTVisualizer
(-Display).
 Will generate and fault simulate a pattern trying to detect a
specific fault.
ATPG> analyze fault /p1/fpu1/u5/mul_69/FS/U307/A1 -stuck_at 1

// ---------------------------------------------------------------------------
// Fault analysis for /p1/fpu1/u5/mul_69/FS/U307 (45061) input A1 (1) stuck at 1
// ---------------------------------------------------------------------------
// Current fault classification = UC (uncontrolled)
// Fault site sequential depth: Control_0 = 0, Control_1 = 0, Observe = 0.
// 2 potential observation points were identified:
// Potential observe point: MASTER-data /p1/fpu1/u5/prod1_reg[43] (47332).
// Potential observe point: MASTER-data /p1/fpu1/u5/prod1_reg[45] (47334).
// Controllability justification was not successful - fault status = abort.
Analyze Faults in DFTVisualizer
Click the Analyze Faults button in the Task Manager window.
This action loads the DFTVisualizer Fault Analysis dialog box.
Show Statistics in DFTVisualizer
1. Enter the path to the instance for which you want to obtain a report.
2. Click the Show Statistics button.
Report Faults in DFTVisualizer
1. Enter a specific instance or obtain information on the entire design.

2. Choose a fault class from the drop down list.
3. (Optional) Display fault class for equivalent faults (just the fault class and not the equivalent.)
4. Click Report Faults to obtain a report on the faults.
Report Faults in DFTVisualizer (Cont.)
Outputs the analysis to the Transcript window.
1. Click on a specific instance to obtain a textual analysis.

2. Click either the Stuck-at-0 or Stuck-at-1 radial button.
3. Click the Analyze (Textual) button.
Report Faults in DFTVisualizer (Cont.)
Outputs the instance to the Debug window.
1. Click on a specific instance to obtain an analysis.

2. Click either the Stuck-at-0 or Stuck-at-1 radial button.
3. Click the Analyze (Graphical) button.
4. Click Data > Fault from the menu to report faults on pin sites.
Fault-By-Fault UC Debugging: Report Test Stimulus
Command
 The REPort TEst Stimulus command displays stimulus
necessary for specified conditions:
 Set
 Write
 Read
 Identifies how to sensitize scan chains blockage points
 Direct control in DFTVisualizer
ATPG> report test stimulus -set /p1/cordic1/U101/A0 0

// Time = 0
// Load 0 /p1/cordic1/X_reg[9] (46932), chain5 0
// Load 0 /p1/cordic1/Y_reg[9] (46927), chain5 5
Lab 7: Troubleshooting Areas of Low Test Coverage
During this lab, you will
 Identify and troubleshoot blocks of design with low test

coverage.
 Determine untestable fault classifications
 Use DFTVisualizer to locate instances in the design.
 Determine the cause of ATPG Untestable (AU) faults.
 Run the tool from a shell script.

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Tessent: Scan and ATPG

Upon completion of this module, you will be able to:

 Use the REPort STAtistics command to:

 The Browser window is used to:

Total Undetected Faults by

 The Signals window lets you

99% 60% 80%

Determine blocks with coverage issues. Use the Browser to

 Addressing aborted faults:

 Use REPort ABorted Faults to generate a summary of

Use REPort ABorted Faults

Use the number of reported

ATPG Untestable Faults

ATPG> create patterns

SETUP> analyze drc violation e10-1

 ATPG> create patterns

constrained value/forbidden value/blocked value

ATPG> REPort Faults –Class UC

 Use the ANAlyze FAult command to identify why a fault is not

ATPG> analyze fault /p1/fpu1/u5/mul_69/FS/U307/A1 -stuck_at 1

This action loads the DFTVisualizer Fault Analysis dialog box.

1. Enter a specific instance or obtain information on the entire design.

Outputs the analysis to the Transcript window.

1. Click on a specific instance to obtain a textual analysis.

Outputs the instance to the Debug window.

1. Click on a specific instance to obtain an analysis.

ATPG> report test stimulus -set /p1/cordic1/U101/A0 0

During this lab, you will

 Identify and troubleshoot blocks of design with low test

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