Floor Planning

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FLOOR

PLANNING
Outlines
• Physical design --- Overall Flow
• Sanity Checks
• Partitioning
• Introduction to floorplan
• Floor Plan Techniques
• Floor Plan Flowchart
• Terminologies and Definitions
• FloorPlan Inputs
• FloorPlan Steps
• FloorPlan Issues
• FloorPlan Checks
• FloorPlan Outputs
What is Physical Design (PD)?
• The physical design transforms a circuit description into the physical layout, which describes the
position of cells and routes for the interconnections between them.
• The main concern in the physical design of VLSI chips is to find a layout with better PPA(Power,
performance, Area).

Physical Layout
PD and ASIC Flow
PD Inputs
• Netlist(.v)
• Libraries
• Physical Library(.lef)
• Timing Library(.lib)
• SDC (Synopsys Design Constraints)
• DEF(Design Exchange Format)
• Scan Def
• UPF(Unified Power Format)
• Spec File
• MMMC(Multi-Mode-Multi-Corner)
• TLU+
 Netlist
• It consists of the logical connectivity of the design.
 Scan Def
• It consists of flip-flop connectivity.
• In Test mode by bypassing the combinational logic, we check for the flip-flop connectivity using scan
chains.
 UPF
• UPF indicates a design's power intent at a high level which includes power distribution
architecture, power strategy, and usage of special cells i.e. isolation cells, level shifters, power
switches, and retention registers.
 Spec file
• It contains Skew & latency target values, reference cell list, DRVs, clock exceptions, NDR rules,
CTS tree type, and other constraints.
 MMC file
• It contains Modes, Corners & Scenarios related information.
• Mode: A mode is defined by a set of clocks, supply voltages, timing constraints, and libraries.
Like test mode, func mode,etc.
• Corner: A corner is defined as a set of libraries characterized by process, voltage, temperature,
and variations.
• Scenario: It is defined as the combination of modes & corners.
 TLU+
• TLU+ file is in the form of binary format.
• The file contains metal resistance & capacitance at different spacing and widths in the form of a
lookup table, providing high accuracy and run-time.
• It contains only the complete details of net delay in the forms of combined Resistance and
Capacitance.
Library contents
Contents of Library

General Combinational Sequential


• Lib. name & • Footprint of the cell • Along with Combinational
Technology • Functionality Cell info, It has:
• Units (I, R, C, P, V, T) • Area • Synchronous
• Operating conditions • Leakage Power w.r.t • Setup w.r.t clock Tran
(PVT) I/P Pins • Hold & Input Tran
• Max_tran • Pin Direction • Asynchronous
• Max_cap • Pin Capacitance • Recovery
w.r.t Reset &
• Max_Fanout • Timing (Propagation, • Removal
Input Tran
Tran, Cap)
SDC Contents
Clock Definitions
• creare_clock
• create_generated_clk -source
• create_clock –name virtual_clock
Design Rule Constraints (DRC)
• set_max_transition
• set_max_capacitance
Port Constraints
• set_input_delay
• set_output_delay
Modeling Drive Strength
• set_drive (or)
• set_driving_cell (or)
• Set_input_transistion
Capacitive Load
• set_load
Timing Exceptions
• set_case_analysis
• set_disable_timing
• set_false_path
• set_multicycle_path
Other Constraints
• set_clock_uncertainity
• set_clock_latency
Library Exchange Format(LEF)
• Lef is a specification for representing physical layout information in the form of ASCII format(human-
readable).
• It can be divided into
• Cell LEF
• Technology LEF
 Cell LEF
• It contains the information related to each cell i.e. Std cells & Macros present in the library in
separate sections.
• It contains
• Cell Name
• Size(width X height)
• Symmetry(XY,X,Y etc.)
• Pin Information
• Pin Name
• Direction(like input, output, inout etc.)
• Use(like signal, Clock, Power etc.)
• Shape
• Layer(M1,M2….)
• Rectangular Coordinates(llx, lly, urx, ury)
 Technology LEF(Tech LEF)
• It contains information regarding all the metal interconnects, via information and related design
rules.
• It contains:
• Metal-related info
• Layer Name(like Poly, metal, via etc.)
• Pitch
• Minimum Width
• Spacing
• Direction(Horizontal or Vertical)
• Metal Resistance
• Minimum Area
• Via related info
• Top-level metal
• Bottom-level metal
• Enclosure Rule
• Antenna ratio
Sanity Checks
• Sanity checks are an important step for physical design engineers to make sure that the inputs
received for physical design are correct and consistent.

Sanity Checks before Floorplan

Library Check Netlist Check SDC Check

• Physical Library • Floating Inputs & nets • Clock definition missing


• Timing Library • Multi-driven nets • Unconstrained ports
• Combinational Loops • Multi-clock-driven
• Empty Modules registers
• Assignment • Unconstrained endpoints
Statements • Port IO delays missing
• Unique ness
Commands to check Sanity Checks
• Library Checks: • SDC Checks:
 Innovus Commands  Innovus Commands
• checkDesign –physicalLibrary • check_timing
• checkDesign –timingLibrary  ICC Commands
• checkDesign -all • check_timing
 ICC Commands
• check_library

• Netlist Checks:
 Innovus Commands
• checkDesign –netlist
 ICC Commands
• check_design
Terminologies and Definitions
 Manufacturing Grid:
• The smallest geometry that the semiconductor foundry can process or the smallest resolution of our
design technology process.
 Standard Cell:
• Standard cells are well-defined and pre-characterized cells used in ASIC Design flow as basic building
blocks.
 Standard Cell Site:
• The minimum Width and Height a Cell can occupy in the design.
 Standard Cell Rows:
• Rows are the locations where cells get placed. Rows are created at the floorplan stage.
 Placement Grid:
• Placement grid is multiples of manufacturing grid.
 Routing Grid or Routing Track:
• Horizontal and Vertical lines drawn on the layout area which will guide for making interconnections
(routing).
 Fly-line/Flight-line:
• Virtual connection between Macros to Macros or Macros to IOs.
Macro:
• Macro cells are the memory cells, and intellectual property(IP) that an analog design team has
designed. Ex: processor core, PLL, etc.
• Two types of macros are there
• Soft Macros: Soft macros are used in SOC implementations. Soft macros are
synthesizable RTL forms and are more flexible than hard macros in terms of
reconfigurability.
• Hard Macros: Hard macros are targeted for specific IC manufacturing technology. They
are block-level designs that are optimized for power or area or timing.
Partitioning
• Decomposition of a complex system into smaller subsystems.

Styles of Implementation:
• Flat
• Small to medium ASIC.
• Better area usage since no reserved space around
each sub-system for power/ground.
• Hierarchical
• For very large designs.
• When sub-systems are designed individually.
• Possible only if the design hierarchy exists.
• The hierarchical partitioning is done before
• the floor plan.
Floor Planning?
• Floor planning involves determining the locations, shape, and size of modules in a chip,
and as such it estimates the chip area, delay, and wiring congestion, thereby providing
the groundwork for layout.
• It is the one critical & important step in physical design.
• A good floor plan can be made implementation process (place, cts, route & timing
closure) cakewalk.
Inputs Of FloorPlan
• Netlist (.v)
• Physical library (.lef)
• Timing library files(.lib)
• Synopsys design constraints (.sdc)
• TLU+
• UPF (Unified Power Format)
Types Of FloorPlan Techniques
There are 3 types of Techniques:
• Abutted floorplan: There is no channel(gap) between the blocks.
• Non-abutted floorplan: There is a channel(gap) between the blocks. The connection between
the blocks is done through the routing nets.
• Mix of both: This design is a combination of abutted and non-abutted.
Floorplan Flowchart
Synthesis Netlist

Create Initial Core & Row


IO ports Placement
Place the Macros & Physical_only cells
Create Placement Blockages
Create Power Rings
Create Power & ground Nets
Route Power & ground Nets

Check violations in the Floorplan

Bad Is
Floorplan
Good
Placement
Steps In FloorPlan
• Initialize with Chip & Core Aspect Ratio (AR)
• Initialize with Core Utilization
• Initialize with Row configuration & Cell Orientation
• Provide the Core to Pad/ IO spacing(Core to IO Clearance)
• IO Placement (or) Pin/Pad Placement
• Macro Placement
• Physical-only cells
• Blockages and Keep-Out Margins
Die Size Estimation
Design can become:
 Core Limited Design
• The size of the chip is decided based on the size of the core region(logic). The number of pads
is less so that the pads can be placed around the core.
 Pad Limited Design
• Size of the chip is decided based on the number of pads because the core region is very small.
• The size of the die is decided based on
• Core Limited/pad Limited Die
• Number of IOs
• Area of the Standard Cells
• Macros Area
Aspect Ratio
Aspect Ratio
• Or simlpy we can say Height/width
• Aspect ratio decides the shape of the
block
Utilization
• The area of the core that is used by placed Standard cells and Macros expressed in percentage.

Utilization
Row Configuration & Cell Orientation
• Slanting lines in the side of the cell rows denote the cell orientation.
Core to Pad /IO Spacing
• IO Area is used for IO Ports placement.
• Channel between Core to IO Area used
for placing Power rings.
• Die to Core clearance(Block-Level)
IO Placement
• Chip level its IO pads block level its IO pins.
• Pin is a logical entity and is a property of the port.
• Port is a physical entity and a port has only 1 pin associated with it.
• Netlist will have pins and the layout will have ports.
• Unplaced port is not represented in the layout.

• Different types of IOs


• Signal pads/pins
• Core power pads/pins
• IO power pads/pins
• Corner pads (Doesn’t have any logic, provides IO power Ring connectivity)
• Filler pads (Fills the gap between the IO pads to get Ring connectivity)
Pin/Pad Placement
IO Ports Placement (Block-Level)
Select Unassigned ports

Select edge to place ports

Select Preferred layers

Specify min. width & space

Select the Exact location for the


placement of the ports

Select Appropriate pattern

Click Apply

Bad Is Ports
Placement
Good
Macro Placement
• IO port placement is done using Pin Editor Option in the Floorplan tool.
• It has Various Patterns, In that we are using
• Full Track: IO Ports are aligned to tracks without any gap in the Specified location.
• Checker board: IO Ports are aligned to alternate tracks in the specified location.
Macro Placement
Guidelines to place Macros in the core area:
1. Macros should be placed around the boundaries Because:
 If Macros places middle of the core
 IR Drop is high because macros are usually, power-hungry cells.
 They will create roundabout routing paths.
2. Communicating macros should be placed together.
 To avoid routing Issues and delays.
3. Macro pins should face toward the center of the core area.
 To route the high number of pins of macros we have
enough space in the Core area compared to the Die area.
4. 0/180 degrees rotation is only allowed.
 To avoid breakage in oxide layers.
Horizontal Rotation: X-axis rotation ( 0 to 180 )
Right  left or left  right
Vertical Rotation: Y – axis rotation (0 to 180)
Top  Bottom or Bottom  Top

5. Proper channel spacing has to maintain. Horizontal Rotation


 The channel is used to route the pins of the macros. Vertical rotation
Channel Spacing

No Channel
Channel Spacing
6. Do not abode ports with macros.
 If we place macros at the ports
 Chance to get Congestion due to macro ports and IO ports
 Detouring is happening due less available tracks
 If we don’t have any choice then we can go for macros placement at
the IO ports. There we can use Hard Placement Blockage near the ports.
 Avoid notches while placing macros.
 The main issue due to the notch would be
 causes Timing violations & Congestion if the cells communicate with
macros placed in the notch.
 Avoid crisscross connections between the macros. Notch
 To avoid congestion near the macro ports.
 Proper Halo should be there around the macro
 Halos around the Macros to avoid congestion at the macros pins.
Criss-Cross
connections
Macro Grouping
Physical-only Cells
• The cells which don’t have any functionality are called physical-only cells.
• Physical-only cells are placed before the placement.
There are various kinds of Physical-Only Cells:
 Tap Cells
• Well-tap cells (or Tap cells) are used to prevent the latch-up issue in the CMOS
design.
• Latch-up: it is the condition when a low impedance path gets formed between
VDD and GND terminal and there is direct current flow from VDD to GND which
might result in a complete failure of the chip.
• Well tap cells connect the n-well to VDD and p-substrate to VSS in order to
prevent the latch-up issue.
• Well tap cells are generally placed in a straight column in the alternate row such a pattern is called a
checkerboard pattern to provide maximum coverage for well tap.
 End Cap Cells
• End Cap Cells are used to prevent the Well-Proximity effect in the design
• Well-Proximity Effect: There is a high chance to get damaged the gate of standard cells placed
at the boundary during the manufacturing of the chip.
• To prevent such damages at the boundary we have a special kind of cells called an end cap
cell or boundary cell.
• The end cap cell or boundary cell is placed at both ends of each placement row to terminate
the row.
 Filler Cells
• Filler cell does not have any functionality or no logical connectivity but it is used to fill the space
between the standard cells.
• these cells are used to provide n-well and substrate continuity.
• why we need continuity for n-well and implantation :
• If n-well is discontinuous there may be chances of
• Latch-up issue
• DRC violations
• If n-well continues mask preparation is easy.
 Decap Cells
• Decap cells are basically charge-storing devices made of capacitors and used to support the
instant current requirement in the power delivery network.

Decap Schematic
Diagram
 Spare Cells
• Spare cells generally consist of a group of standard cells mainly inverter, buffer, nand, nor, and,
or, exor, mux, flip flops, and maybe some specially designed configurable spare cells.
• Ideally, spare cells do not perform any logical operation in the design and act as filler cells only.
Use of Spare Cells
• Spare cells enable us to modify/improve the functionality of a chip with minimal changes in the mask.
• We can use already placed spare cells from the nearby location and just need to modify the metal
interconnect.
• There is no need to make any changes in the base layers.
 Tie Cells
• The tie cell is a standard cell, designed specially to provide the high or low signal to the input
(gate terminal) of any logic gate.
• There are two types of tie cells:
• Tie-high: the tie-high cell’s output is always high.
• Tie-low: the tie-low cell’s output is always low.
Need of tie cells:
• In the lower technology node, the gate oxide under the poly gate is a very thin and the most
sensitive part of the transistor.
• It has been observed that if the polysilicon gate connects directly to VDD or VSS for a constant
high/low input signal, and in case any surge/glitch arises in the supply voltage it results in damage
to sensitive gate oxide.
• To avoid this damage we are using tie cells.
 Fiducial Cells or Markers
• A method for performing failure analysis, it comprises: observing a semiconductor die under
magnification, And using at least one fiducial marker in a spacer cell of the semiconductor die
for an indication of location.
Blockages
• Blockages are specific locations where the placing of cells is blocked.
• Blockages act like guidelines for the placement of std cells.
• Blockages are divided into:
• Placement Blockages
• Routing blockages
• Again Placement Blockages are divided into:
• Hard Blockage:
• It specifies a region where all std cells & buffers cannot be placed
• Std cell blockages are mostly used to
• Avoid routing congestion at macro corners
• Restrict std cells to certain regions in the design
• Control power rails generation at macro cells
• Soft Blockage:
• It specifies a region where only buffers can be placed
• They are Non-Buffering Blockages, Only buffers can be placed and standard cells cannot
be placed.
• Partial Blockage:
• It specifies a region where some percentage of the area unavailable for placement
• It is a Partial Standard Cell Blockages and is used to avoid congestion
• We can Block Standard Cells as per the requirement percentage value
• Routing Blockage
• Used to prevent the route in a particular area for the specific metal layer for all nets or only
signal nets or power/ground nets.
Types Of Blockages
Keepout Margins
• A keepout margin is a region around the boundary of fixed cells in a block in which no other cells
are placed.
• There are Three types of keepout margins:
• Outer keepout Margin: It is a region outside the cell boundary.
• Inner keepout Margin: It is a region inside the cell boundary.
• Outer & Inner keepout margins are used for std cells. They are fixed, they don’t move w.r.t std cells.
• Halo: It is the region around the boundary of fixed macro in the design in which no other macros or
std cells can be placed.
• Halo will obey the macro, which means If the macros are moved from one place to another place, Halos
will also be moved.
Issues arise due to bad Floor Plan
• Congestion near Macro Pins/ Corners due to insufficient Placement Blockage
• Std. Cell placement in narrow channels led to congestion
• Macros of the same group which are placed far apart can cause Timing violation
• It creates routing issues while routing the cells
• It will create more IR drops due to bad placement of macros
Floorplan Checks
 Utilization should be under control after floor planning is done.
 There should not be any overlaps between the ports.
 All I/O ports should be connected to the Die area and have a fixed attribute
 Ports should be aligned to tracks with proper width, depth & spacing.
 There should not be any overlapping between the macros-to-macro & macro to Physical-only cells.
 Make sure that all macros have proper halo & have fixed attributes
 Proper row alignment for macros to get power & ground.
 Make sure Macro ports are aligned with tracks
 Check for physical-only cells are placed and have fixed attribute
 Make sure Blockages are placed properly
FloorPlan Outputs
• IO ports placement
• Cell rows creation
• Final macro placement
• Core boundary and area
• Pin position
• Floorplan def
POWER

PLANNING
Outlines
• Power Estimation
• Types of Power
• Power Planning
• Low-Power Cells
• Power Planning Issues & Fixes
• Flip Chip
• Power Plan Checks
Power Estimation
Power Estimation:
• Power Estimation is based on Total Power consumed by the Chip
Types of power
Internal Power(Static)
• Power dissipated due to cell internal loads and short circuit current, current flowing from VDD to
VSS when both PMOS and NMOS are completely/partially ON.
Switching power(Dynamic)
• Power dissipated due to standard cells, pads, and macros charging
and discharging the output load (interconnect + fanout loads).
Leakage Power
• The power consumed by the sub-threshold currents and by reverse-biased diodes in a CMOS
transistor is considered leakage power.
• Due to the leakage current in MOS Designs can have as high as 40% leakage contributions.
Power Planning
• Power planning is to supply power across the blocks
without any drop in the IR.
• It includes:
• Powe Rings: VDD and VSS rings are formed around
the core and macro.
• Power Straps: They are created in the Core Area to
tap
power from Core Rings to the core area.
• Power Mesh: Each of these stripes runs both vertically
and horizontally at a regular interval then this is called
power mesh.
• Row-Flip: Row flipping is allowed to flip rows to avoid
shorts
between the power & ground.
• Global Net Connectivity: Used to define the power/ground
nets to be connected to various power/ground pins of std
cells/macros IO pads etc in our design.
Why do we create a mesh kind of structure?
• In general, the top two layers are used for Power Mesh creation. Because Higher layers have larger
widths which will result in a low IR drop.
• Distribute the power from power pads/pins to all elements of the chip.
• Provides multiple paths from PG sources to destination.
• Uniform distribution of power with less voltage drop.
• To meet IR/EM targets
• Simultaneous Switching
Low-Power Cells
• These cells are used in low-power applications.
• These cells are placed after power rails are created.
Switch Cells
• These cells are used to switch off the power domain when blocks are not in active state thus
reducing leakage current.
• There are two types of power switches:
• Header: The header switch is implemented by the PMOS transistor to control the VDD supply.
Daisy • Footer: The footer switch is implemented by an NMOS transistor to control the VSS supply.
chain
fashion

Power Switches
 Isolation Cells
• Powered-off domains do not drive outputs anymore and these outputs become
floating nodes.
• This could be a problem when other active domains get these floating nodes as
inputs.
• To avoid this problem Isolation cells (also called “clamps”) keep the turned-off sub-
block output at a predefined value.
• Isolation cells are powered by constant supply and drive 0(clamp 0),1(clamp 1), or
latch the old value of the turned-off domain.
 Level-Shifter Cells
• A level shifter converts a logic signal from one voltage swing to another, with the goal
of having the smallest possible delay from input to output.
• Necessary as most low-power designs have multi-voltage domains and/or employ
dynamic voltage scaling.
• It has the minimal functionality of a buffer.
 Retention Registers
• In order to reduce power consumption, memories are shut down where their power is switched
off or when they are not in use.
• Retention registers save state information before a power domain is switched off and restore it
when the power is turned back on.
• A retention register specifies the power pins and the input signals that control the saving and
restoring of data.
Power Planning Issue?
IR Drop
• Reduction in voltage that occurs on power supply networks (VDD).
• In reality, localized voltage drops within the power grid
• Increasing current/area on the die
• Narrower metal line widths (increases power grid resistance).
• Results in decreased power supply voltage at cells/transistors.
• Decreases the operating voltage of the chip, resulting in timing and functional failures.
Ground bounce
• Increase in voltage that occurs on the ground networks(VSS or GND) in ICs.
• Increase in ground voltage decreases the operating voltage of the chip, resulting in timing and
functional problems.
Electro Migration
• Flow/moment of atoms along with the electrons in a metal due to the high current density is
known as Electro Migration.
• This may create voids in the place where atoms are displaced and hillocks in the place where
atoms are accumulated.

Direction of Current flow


Fixes for Power Planning issues
• To reduce IR drop:
• Routing should be from the top layer
• By adding some more power stripes
• By increasing the width of the metal
• By adding Decaps(Dcap cells)
• By using some low-power techniques
• To reduce EM Effect:
• Decrease Driver’s drive strength
• NonDefault(wider) rule-based routing
• Use multi-Cut Via
• Use wider metals
• Route with higher metal layers
What is a Flip Chip?
Based on packaging, Chips can be classified as :
 Wire Bond Chip:
 This conventional technique involves the mounting of a chip
onto a substrate, back-side down. Then, peripheral pads on the
chip are bounded to the substrate via wires.
 The main advantage of this approach is that it is very cost-effective.
 Flip Chip:
 The bonding process is characterized by the soldering of
silicon devices directly to a substrate.
 The chip faces the substrate, as opposed to wire bonding,
hence the name flip-chip bounding.
Power plan checks?
• There should not be any open connections
• All the Macros should be hooked up with power/ground
• IR/EM target should be met
• Missing Vias should be taken care
• Presence of Global net connectivity for the cells & macros
• There should not be any power & ground shorts
Thank You…….

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