Interfacing Serial Converters to a

programmable DSP device

Arvind Vishnubhatla
• In a DSP system, in addition to the parallel
interface, there is provision to interface serial
peripherals.
• In the serial interfacing mode, data transfer
takes place bit by bit.
• The serial data transfer may be synchronous or
asynchronous.
• Synchronous serial transfer allows faster data
communication but requires a clock signal as the
timing reference.
 Synchronous serial interface as
provided in the TMS320C5416
DSP
• This device provides three multichannel
buffered serial ports (McBSP).
 AGENDA
• A multichannel buffered serial port
(McBSP)
• McBSP programming
• A CODEC interface circuit
• CODEC programming
• A CODEC-DSP interface example
Synchronous Serial Interface
• The synchronous serial interface of the
C54xx DSP allows it to communicate with
the serial peripherals.
• Such an interface is shown in Figure 10.1
for a device called an analog input/output
CODEC. The CODEC consists of A/D and
D/A converters.
Figure 10.1 Synchronous serial interface (SSI) between the
C54xx and a CODEC device
• On the DSP device the DX data line
transmits the serial data to the CODEC,
and the DR receives it from the CODEC.
• The receive data is timed with reference to
the clock signal CLKR, and the transmit
data with respect to the clock signal CLKX.
• The start of the respective data (the first
bit) is synchronized to the frame sync
signals FSR and FSX.
• Similar to the DSP device, the
corresponding signal pins are provided on
the CODEC device.
• Figure 10.2(a) is the timing diagram for the
receive operation for the interface.
• Data reception starts with the FSR pulse.
• A bit is received for each clock pulse of the
CLKR.
• After receiving all bits, 8 in this case, the
processor generates a RRDY signal to
indicate that the word of data is ready in
the data receive register of the serial port.
• The status signal RRDY can be read by
the processor to determine if a word of
data has been received.
Figure 10.2(a) Receive operation timing for the SSI
(Courtesy of Texas Instruments Inc.)
• Similar to receive timing is the transmit
timing shown in Figure 10.2(b).
• Here the transmission starts with FSX and
the completion is indicated by XRDY
changing from logic 0 to logic 1.
• The XRDY indicates that the previously
placed data word has been transmitted
and the port is ready to transmit the next
word, if so desired.
Figure 10.2(b) Transmit operation timing for the SSI
(Courtesy of Texas Instruments Inc.)
 A Multichannel Buffered Serial
Port (McBSP)
• McBSP is a full-duplex synchronous serial
port.
• Three such ports are provided on the
TMS320C5416 DSP.
• McBSP can be used to interface
synchronous serial peripherals such as a
CODEC.
• The block diagram of Figure 10.3 shows
structure of this port.
Figure 10.3 Block diagram of the McBSP of C54xx
(Courtesy of Texas Instruments Inc.)
• The incoming data enters the port through
the DR line into the receive shift register,
RSR, where it is assembled into a word
that is transferred to Receive buffer
register, RBR.
• From the buffer register it is transferred to
the data receive register, DRR.
• The DSP processor reads the data from
the memory-mapped register DRR using
an internal peripheral data bus.
• The port informs the processor about the
data in DRR using receive interrupt
request, RINT, or using the DMA signals.
• The DRR status is recorded in the serial port
control register 1, as the RRDY bit, so that the
processor can determine when the data is ready
for transfer.
• The DSP can send the data to the outside world
using the memory-mapped data transmit
register, DXR. The data written to DXR is
transferred to the transmit shift register, XSR, for
shifting out 1 bit at a time.
• The port informs the processor about the
data in DXR using transmit interrupt
request, XINT, or using the DMA signals.
• The DXR status is recorded in the serial
port control register 2, as the XRDY bit, so
that the processor can determine when the
data has been transmitted.
• There are six memory-mapped registers
associated with each port. These registers
with their addresses are shown in the table
of peripheral memory-mapped registers.
Figure A.6 Memory-Mapped Registers
(Courtesy of Texas Instruments Inc.)
Figure A.7 Peripheral Memory-Mapped Registers
(Courtesy Texas Instruments Inc.)
Figure A.7 Continued
• Each register is of 16-bit length. There are
two receive registers to enable received
data lengths up to 32 bits.
• Similarly, there are two transmit registers
for each port.
• There are two more registers— SPSA for
address and SPSD for data—associated
with each port.
• It is by using these two registers that we
can access subbank control registers for
programming the serial port.
• The control registers are shown in the
table for McBSP control registers and
subaddresses.
Figure A.8 McBSP Control Registers and
Subaddresses (Courtesy of Texas Instruments Inc.)
Figure A.8 Continued
• For instance, to write data to receive
control register 2 (RCR22) of McBSP2
whose subaddress is 0x0003h, we write
0x0003h to register SPSA2 at memory
address 0x0034h and the data to memory-
mapped register SPSD2 at address
0x0035h.
• A similar sequence must be used while
reading a subbank register.
 McBSP Programming
• In order to configure the McBSP, one
needs to write appropriate data to the
control registers.
• The functions of the bits of these registers
are described in the manual which should
be consulted to program the port.
• A sample program is shown in Figure
10.4.
• This program configures the McBSP2 to
work with serial 20-bit input data and serial
20-bit output data.
• We can see that the control register SPCR12
enables or disables the receiver.
• Similarly, SPCR22 serves to enable or disable
the transmitter function.
• The control register RCR12 selects the 20-bit
data mode for the receiver, and RCR22 specifies
that FSR will be used to start receiving the data
bits.
• Similarly, the control registers XCR12 and
XCR22 select the corresponding functions for
the transmitter.
• Finally, the PCR2 defines clocks and
frame sync pulses to be external and
active high. This register also specifies
other functions of the pins of the serial
port, as indicated in the program.
Figure 10.4 A program to initialize the McBSP2
Figure 10.4 Continued
Figure 10.4 Continued
Figure 10.4 Continued
Figure 10.4 Continued
 A CODEC Interface Circuit
• The PCM3002 is a device that can be
directly connected to the synchronous
serial port of the DSP. It provides 16/20-bit
oversampling sigma- delta A/D and D/A
converters.
• The maximum sampling rate that can be
implemented with this device is 48 KHz.
• Figure 10.5(a) shows the building blocks
of the CODEC device.
• The detailed block diagram of Figure
10.5(b) shows the internal architecture of
the PCM3002.
Figure 10.5(a) Block diagram for the PCM3002
CODEC (Courtesy of Burr–Brown Corporation)
Figure 10.5(b) Details of the PCM3002 CODEC
(Courtesy of Burr–Brown Corporation)
• The device provides stereo ADC and DAC
with single-ended voltage input and output
for the left and right channels.
• The CODEC can be programmed for
digital de-emphasis, digital attenuation,
soft mute, digital loop-back, and the
power-down mode for the ADC and the
DAC.
• An analog signal is applied to the
combination of a delta- sigma modulator
and a decimation filter to convert it to a
corresponding digital signal.
• The input signal is sampled at a 64X
oversampling rate, eliminating the need for
a sample-and-hold circuit and also
simplifying the need for an antialiasing
filter.
• A decimation filter is used to reduce the
digital data rate to the sampling rate
before generating the output bitstream.
• A highpass filter removes the dc
components of the signal.
• The delta-sigma modulator in conjunction
with an interpolation filter forms the DAC,
which converts the serial digital signal to
the corresponding analog signal.
• The interpolation filter is used to increase
the sampling rate to the one needed by
the modulator. The converted signal is
filtered with an analog lowpass filter to
generate the analog output.
• As shown in the Figure 10.5(b), there are
two distinct parts of the CODEC device:
one to handle the serial data transfers,
and the other for its initialization and to set
it to work in the desired mode.
• The two blocks, the serial data interface
and the mode control interface, handle
these two functions.
• A block diagram of how the PCM3002
CODEC device is used in the C5416 DSK
board is shown in Figure 10.6.
• The CPLD on the DSK provides the
system clock and the other timing signals
for the mode control interface.
 Figure 10.6 Block diagram showing the PCM3002 interface
to the TMS320VC5416 in the DSK (Courtesy of Spectrum Digital Inc.)
• It also controls the choice of using the
McBSP2 port on the DSP for connection
either to the host PC (HPI) or to the
PCM3002.
• The CPLD has user-accessible registers
that can be loaded to define the various
parameters of the CODEC data and
control interfaces.
• The system clock for generating various
timing signals for the CODEC is its
SYSCLK. This clock must be 256 fs or 384
fs or 512 fs, where fs is the sampling
frequency.
• The CODEC detects the system clock and
uses it to generate the internal clock at
256 fs for the digital filters and delta-sigma
modulators.
• In the C5416 DSK board, the SYSCLK is
supplied by the CPLD-generated clock
CODEC_SYSCLK, which is generated
from the 12.288 MHz CODEC_CLK.
• The data interface of the CODEC and the
DSP is by way of DIN for data input,
DOUT for data output, BCKIN for data bit
clock, and LRCIN for frame sync signal for
the left and right channels.
• The data bit clock and the frame sync
signals are generated by the CPLD from
the CODEC_CLK and applied to the
CODEC and the DSP.
• The timing for the data input and output is
shown in Figure 10.7 for the four possible
data formats.
 Figure 10.7 Data transmission formats for the
PCM3002 CODEC (Courtesy of Burr–Brown Corporation)
Figure 10.7 Continued
Figure 10.7 Continued
Figure 10.7 Continued
• The frequency of the LRCIN signal is the
ADC/DAC sampling frequency.
• The bits are transferred using the bit clock
BCLKIN.
• In the CPLD, the BCKIN and LRCIN are
generated from the 12.228-MHz oscillator
clock called the CODEC_CLK, which is
also the default CODEC_SYSCLK, applied
to the CODEC device
• The corresponding default bit clock BCLKIN
frequency is 3.0122 MHz (or one-fourth of the
CODEC_SYSCLK), and the sampling frequency
is 48 KHz.
• The default frequencies can be changed by
dividing the CODEC_CLK by 2, 4, 6, or 8.
• This provides the capability to change the
sampling rate to one of five rates, the smallest
being 6 KHz and the largest 48 KHz.
• Example 10.1 Determine the timing
parameters for a 16-bit data
communication in a DSK configured for a
clock divisor of 6. The oscillator clock
(CODEC_CLK) is at 12.288 MHz.
• Solution CPLD input clock (CODEC_CLK) = 12.288
MHz
• Sampling frequency /, = 2.044 MHz/256 = 8 KHz.
• Sampling interval = 1/8K = 125 msec
• Bit clock frequency (BCLKIN) = 2.044 MHz/4 = 511 KHz
• Bit clock period = 1/51 IK = 1.96 usec
• 16 x 1.96u = 31.31 usec
• Thus, in each 125 msec of time, the data is
communicated just for 2 x 31.31 usec for both channels.
 CODEC Programming
• To configure the CODEC we send control
data using the mode control interface
signals as shown in the timing diagram of
Figure 10.8.
• The mode bits represented by the signal
MD are sent using the mode clock signal
MC.
Figure 10.8 Mode control interface signal timing for
the PCM3002 CODEC (Courtesy of Burr–Brown Corporation)
• The mode load signal ML defines the start
and end of latching the bits into the
CODEC device.
• In the DSK these signals are generated in
the CPLD from the oscillator clock.
• The 16-bit mode control data that is
transferred comes from the CPLD and is
placed into one of the four registers of the
CODEC device to program it.
• The four program registers of the
PCM3002 are shown in Figure 10.9(a).
Figure 10.9(a) Program registers for the PCM3002 CODEC
(Courtesy of Burr–Brown Corporation)
• The description of the various bits of these
registers is shown in Figure 10.9(b).
Figure 10.9(b) Definition of the bits of the program registers
of the PCM3002 CODEC (Courtesy of Burr–Brown Corporation)
• In the program registers the two bits
indicated as A1A0 specify the register to
which the data in other bits refer.
• For instance, for register 0 these bits are
00. Register 0 can be loaded to control the
attenuation to be applied to the DAC for
the left channel.
• Similarly, register 1 can be loaded with the
attenuation data for the DAC of the right
channel.
• The number loaded in the 8 bits of either of
these two registers applies the attenuation to the
two channels according to the equation
• Attenuation = 20 log(ATT/255) where ATT is
the value represented by the 8 attenuation bits
in register 0 or register 1.
• Either the LDL bit in register 0 or the LDR in
register 1 can use the attenuation data to control
the two channels.
• The bits in register 2 are meant to select the
power down mode for the ADC and DAC, the
ADC highpass filter bypass control, DAC
attenuation channel control, DAC infinite zero
detection circuit control, DAC output enable
control, DAC deemphasis control, and the DAC
soft mute control.
To enable or select a mode, the
corresponding bit or bits are made 1.
• For the deemphasis control, the two bits
used are as follows:
• 00 selects deemphasis 44.1 KHz,
• 01 deselects deemphasis,
• 10 selects 48 KHz deemphasis, and
• 11 selects 32 KHz deemphasis.
• Register 3 provides ADC/DAC loopback
control, audio data format selection, and
polarity selection for the LRCIN signal.
• A 1 in the LOP bit enables the loopback.
• A 1 in the LRP bit selects the left channel
when LRCIN is low and the right channel
when it is high.
• The data format is selected by the two bits
FMT1 and FMT0.
• The 00 on these two bits selects the
format 0 for the data as received from the
ADC or applied to the DAC.
• These data formats are shown in Figure
10.7 and provide four different ways to
communicate data.
• The CPLD that provides data for the four
program registers and other controls on
the DSK board has eight registers
accessible from the DSP. These registers
are shown in Figure 10.1.
Figure 10.10 CPLD register definition in the DSK
• These registers are each 8 bits wide and are
located in the I/O space of the C5416.
• For instance, the registers at I/O addresses 2
and 3 hold the CODEC programming data.
• The most significant bit in the miscellaneous
register at the I/O address 6 must be checked
each time any new data is written to the CPLD
registers for programming the CODEC.
• The sampling frequency can be changed
by loading the divisor, for the CODEC
clock, to the CODEC-CLK register at the
I/O address 7.
• The sequence of steps that need to be followed
is: stop the clock, load the divisor, start the
clock, and select the divisor.
• The bits of the CODEC-CLK register need to be
loaded appropriately to accomplish these steps.
• The other CPLD registers are there for
configuring the memories and for communicating
with the user switches and the LEDs of the DSK.
A CODEC-DSP Interface Example
• In this section, we write a simple
application that involves configuring
McBSP2 and the PCM3002 on the DSK
board.
• The configured system is used to
implement a signal loopback by reading a
signal applied to the ADC and writing it to
the DAC.
• The application can be easily extended to
include any kind of processing on the
signal read from the ADC before sending it
to the DAC.
• The flow chart of the main program is
shown in Figure 10.11(a).
Figure 10.11(a) Main program flowchart for the
signal loopback program
• The main program starts by initializing the
stack pointer and disabling the interrupts.
Establishing the stack allows using
subroutines.
• The disabled interrupt system ensures that
during initialization interrupts will be
ignored.
• This is followed by three subroutines that
initialize the processor, the serial port, and
the PCM3002.
• After the initializations are done, the serial
port transmitter and the receiver are
enabled.
• Next, any pending interrupt is cleared and
the receive interrupt is unmasked before
enabling the interrupts.
• At the end, the processor waits for the
receive interrupt to occur.
• When a receive interrupt occurs, the
corresponding service routine is executed.
• In the service routine, the DRR registers
are read into the accumulator.
• The word so read is written back to the
DXR after formatting it for the DAC.
• The return from the service routine, with
interrupts enabled, makes the program
wait for the next interrupt, which occurs
after the ADC provides the next sample to
the port.
• It is in this routine that any signal
processing on the received signal can be
implemented.
• The receive interrupt service routine flow
chart is shown in Figure 10.11(b).
Figure 10.11(b) Receive interrupt service routine flowchart
• The entire program, shown in Figure
10.11(c), consists of the main module
signalLBmain.asm;
• interrupt vector module C5416vec.asm;
• initialization modules initC5416.asm,
initMcBSP2.asm, and initPCM3002.asm;
and
• the module regs.asm that defines various
constants used in the program.
• Notice that some of the definitions in the
regs.asm module are specific to the DSK-
implemented registers, such as
DSP_CPLD_CODEC_L.
Figure 10.11(c) A signal loopback implementation
program for the DSK5416
Figure 10.11(c)
Continued
Figure 10.11(c) Continued
Figure 10.11(c) Continued
Figure 10.11(c) Continued
Figure 10.11(c) Continued
Figure 10.11(c) Continued
Figure 10.11(c) Continued
Figure 10.11(c) Continued
Figure 10.11(c) Continued
Figure 10.11(c) Continued
Figure 10.11(c) Continued
Figure 10.11(c) Continued
Figure 10.11(d) The command file for the loopback program