Module 5 SRB

Department of Electronics &
Communication Engineering
(Accredited by NBA, New Delhi. Validity 01.07.2019 to 30.06.2022)
COMPUTER ORGANIZATION
AND ARCHITECTURE
18EC35
Module -1: Basic Structure of Computers: Computer Types, Functional Units,

Basic Operational Concepts, Bus Structures, Software, Performance –
Processor Clock, Basic Performance Equation (up to 1.6.2 of Chap 1 of Text).
Machine Instructions and Programs: Numbers, Arithmetic Operations and
Characters, IEEE standard for Floating point Numbers, Memory Location and
Addresses, Memory Operations, Instructions and Instruction Sequencing (up
to 2.4.6 of Chap 2 and 6.7.1 of Chap 6 of Text).
Module -2: Addressing Modes, Assembly Language, Basic Input and Output
Operations, Stacks and Queues, Subroutines, Additional Instructions (from
2.4.7 of Chap 2, except 2.9.3, 2.11 & 2.12 of Text).
Module -3: Input/ Output Organization: Accessing I/O Devices, Interrupts –

Interrupt Hardware, Enabling and Disabling Interrupts, Handling Multiple
Devices, Controlling Device Requests, Direct Memory Access (up to 4.2.4 and
4.4 except 4.4.1 of Chap 4 of Text).
03/22/2024 Dept. of ECE, ATMECE, Mysuru 2

Module-4: Memory System: Basic Concepts, Semiconductor RAM Memories

Internal organization of memory chips, Static memories, Asynchronous
DRAMS, Read Only Memories, Cache Memories, Virtual Memories, Secondary
Storage-Magnetic Hard Disks (5.1, 5.2, 5.2.1, 5.2.2, 5.2.3, 5.3, 5.5 (except 5.5.1
to 5.5.4), 5.7 (except 5.7.1), 5.9, 5.9.1 of Chap 5 of Text).
Module-5: Basic Processing Unit: Some Fundamental Concepts, Execution of a

Complete Instruction, Multiple Bus Organization, Hardwired Control, and
Micro programmed Control (up to 7.5 except 7.5.1 to 7.5.6 of Chap 7 of Text).

MODULE 5
Basic Processing Unit

Syllabus
• Some Fundamental Concepts

• Execution of a Complete Instruction
• Multiple Bus Organization
• Hardwired Control
• Micro programmed Control

Learning outcomes
 How a processor executes instructions
 The internal functional units of a processor& how they are
interconnected
 Hardware generating internal control signals
 The microprogramming approach

Preamble

Pipelining Method 1
Method 2


The fetch-decode-
execute cycle
A standard process describes
the steps needed for
processing to take place. It is
called the Fetch - Decode -
Execute cycle or sometimes
simply called the Fetch-Execute
Cycle.

1. FETCH
• The first step the CPU carries out is to fetch some data and instructions
(program) from main memory then store them in its own internal temporary
memory areas. These memory areas are called 'registers'.
• This is called the 'fetch' part of the cycle.
• For this to happen, the CPU makes use of a vital hardware path called the
'address bus'.
• The CPU places the address of the next item to be fetched on to the address
bus.
• Data from this address then moves from main memory into the CPU by
travelling along another hardware path called the 'data bus'.
2. DECODE
• The next step is for the CPU to make sense of the instruction it has just
fetched.
• This process is called 'decode'.
• The CPU is designed to understand a specific set of commands. These

are called the 'instruction set' of the CPU. Each make of CPU has a
different instruction set.
• The CPU decodes the instruction and prepares various areas within the
chip in readiness of the next step.

3. EXECUTE
• This is the part of the cycle when data processing actually
takes place. The instruction is carried out upon the data
(executed). The result of this processing is stored in yet
another register.
• Once the execute stage is complete, the CPU sets itself up to

begin another cycle once more .

Fundamental Concepts
• Processor fetches one instruction at
a time and perform the operation
specified.
• Instructions are fetched from
successive memory locations until a
branch or a jump instruction is
encountered.
• Processor keeps track of the address
of the memory location containing
the next instruction to be fetched AE00 MOV A(d),B(s) =3C
using Program Counter (PC). AE01 MOV R1, R2
• Instruction Register (IR)

Executing an Instruction
• Fetch the contents of the memory
location pointed to by the PC. The
contents of this location are
loaded into the IR (fetch phase).
IR ← [[PC]]
• Assuming that the memory is byte
addressable, increment the
contents of the PC by 4 (fetch
phase).
PC ← [PC] + 4
• Carry out the actions specified by
the instruction in the IR (execution
phase).
Processor Organization
Internal processor
bus
Control signals
PC
Instruction
Address
MDR HAS TWO lines
MAR
decoder and
control logic
INPUTS AND Memory
TWO OUTPUTS bus
MDR
Data
lines IR
Constant 4 R0
Select MUX
Add
A B
ALU Sub R n - 1 
control ALU
lines
Carry-in
XOR TEMP
Figure 7.1. Single-bus organization of the datapath inside a processor.

Internal processor
bus
MDR has 2 inputs and 2 outputs. Data may be Control signals
loaded PC
→ into MDR either from memory-bus Address

lines
Instruction
decoder and
(external) or MAR control logic
Memory
→ from processor-bus (internal). bus
MDR
• MAR’s input is connected to internal-bus; MAR’s Data

lines IR
output is connected to external-bus. Y
• Instruction Decoder & Control Unit is Constant 4 R0
responsible for Select MUX
Add
→ issuing the control-signals to all the units ALU Sub
A B
R n - 1 
control
inside the processor.
ALU
lines
Carry-in
XOR
→ implementing the actions specified by the
TEMP
instruction (loaded in the IR).

Z
• Register R0 through R(n-1) are the Processor

Registers. Figure 7.1. Single-bus organization of the datapath inside a processor.

Internal processor
bus
Control signals
The programmer can access these registers for general- PC
purpose use. Instruction
Address
Only processor can access 3 registers Y, Z &Temp for lines
MAR
decoder and
control logic
temporary storage during program-execution. The Memory
bus
programmer cannot access these 3registers. MDR
Data
lines IR
• In ALU, 1) A input gets the operand from the output of the Y
multiplexer(MUX). Constant 4 R0
2) B input gets the operand directly from the Select MUX
processor-bus. Add
• There are 2 options provided for A input of the ALU. ALU

control
Sub
A B
R n - 1 
ALU
• MUX is used to select one of the 2inputs. lines
Carry-in
XOR TEMP
Z
• MUX selects either
→ output of Y or
→ constant-value 4( which is used to increment PC Figure 7.1. Single-bus organization of the datapath inside a processor.
content).

Steps involved in the execution of an instruction

• Transfer a word of data from one processor register to
another or to the ALU.
• Perform an arithmetic or a logic operation and store the result
in a processor register.
• Fetch the contents of a given memory location and load them
into a processor register.
• Store a word of data from a processor register into a given
memory location.

Register Transfers
• Internal processor
•• bus
• •• Riin
Instruction execution involves a sequence of
steps in which data are transferred from one •• Ri
register to another. • •• Riout

For each register, two control-signals are •• Yin
used:
• Y
To place the contents of the register on the • Constant 4
bus • Select • MUX
or
To load the data on the bus into the register •
•
A •
ALU
B
•• Zin
Riin &Riout are called Gating Signals.
• Z
• Riin=1 data on bus is loaded into Ri.
Riout=1 content of Ri is placed on the bus. •• Zout
Riout=0, bus can be used for transferring • Figure 7.2. Input and output gating for the registers in Figure 7.1.
data from other registers.
•
5
5

Register Transfers • Internal processor

•• bus
Ex: • •• Riin
Move R1, R4; This transfers the contents of register
R1 to register R4. •• Ri
R1=25, R4=33 • •• Riout

Move R1, R4 •• Yin
R1=? R4=?
• Y
This can be accomplished as follows: • Constant 4
1) Enable the output of registers R1 by setting R1out• Select • MUX
to 1. This places the contents of R1 on processor-
bus. •
•
A •
ALU
B
2) Enable the input of register R4 by setting R4in

•• Zin
to1.This loads data from processor-bus into register
• Z
R4.
• All operations and data transfers within the •• Zout
processor take place within time-periods defined by • Figure 7.2. Input and output gating for the registers in Figure
the processor-clock.
• The control-signals that govern a particular transfer
are asserted at the start of the clock cycle.
Register Transfers
All operations and data transfers are controlled by the processor clock
Bus
D Q
1
Q
Riout
Ri in
Clock
Figure 7.3. Input and output gating for one register bit.

Performing an Arithmetic or Logic Operation

• The ALU is a combinational circuit
that has no internal storage.
• ALU gets the two operands from
MUX and bus. The result is
temporarily stored in register Z.
• What is the sequence of
operations to add the contents of
register R1 to those of R2 and
store the result in R3?
• ADD R1,R2, R3 R1=5, R2=3, R3=?
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in

Performing an Arithmetic or Logic Operation

• The ALU is a combinational circuit
that has no internal storage.
• ALU gets the two operands from
MUX and bus. The result is
temporarily stored in register Z.
• What is the sequence of operations
to add the contents of register R1 to
those of R2 and store the result in
R3?
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in

Fetching a Word from Memory

• Address into MAR; issue Read operation; data into MDR.
Memory-bus Internal processor

data lines MDRoutE MDRout bus
MDR
Three input MUX

MDR inE MDRin
External Internal
Figure 7.4. Connection and control signals for register MDR.

Fetching a Word from Memory

• The response time of each memory access varies (cache miss, memory-
mapped I/O,…).
• To accommodate this, the processor waits until it receives an indication
that the requested operation has been completed (Memory-Function-
Completed, MFC).
Move (R1), R2
1. MAR ← [R1]
2. Start a Read operation on the memory bus
3. Wait for the MFC response from the memory
4. Load MDR from the memory bus
5. R2 ← [MDR]

Timing of a memory read operation

Assume MAR is always available
on the address lines of the memory
bus.
1. MAR ← [R1]
Step 1 2 3
2. Start a Read operation on Clock
the memory bus MARin Memory-bus

data lines MDRoutE MDRout
Internal processor
bus
3. Wait for the MFC Address

response from the
memory Read
MDR
4. Load MDR from the MR
memory bus
5. R2 ← [MDR]
MDRinE
MDR inE MDRin
Data
Figure 7.4. Connection and control signals for register MDR.
1. R1out, MARin, Read MFC
2. MDRinE, WMFC MDR out
3. MDRout, R2in
Figure 7.5. Timing of a memory Read operation.

Storing a Word in Memory Step 1 2 3
Consider the instruction Clock
MARin
Move R2,(R1). Address
Read
This requires the following sequence: MR
MDRinE
1) R1out,MARin ;desired address is loaded

Data
into MAR.
2) R2out,MDRin,Write ;data to be written are MFC
loaded into MDR & Write MDR out
command is issued.
3) MDRoutE,WMFC ;load data into memory- Figure 7.5. Timing of a memory Read operation.
location pointed by R1 from

MDR.

Move (R4), R5

Storing a word in memory

• Address is loaded into MAR
• Data to be written loaded into MDR.
• Write command is issued.
Example : Move R2,(R1)
R1out,MARin
R2out,MDRin,Write
MDRoutE, WMFC

EXECUTION OF A COMPLETE INSTRUCTION

1000H Add (R3), R1
1004 Mov A, R3
• Fetch the instruction
• Fetch the first operand (the contents of the memory location
pointed to by R3)
• Perform the addition
• Load the result into R1

Internal processor
bus
Control signals
PC
Instruction
Address
Step Action lines
decoder and
MAR control logic
Memory
1 PC out , MAR in , Read, Select4, Add, Zin bus
2 Zout , PC in , Yin , WMF C MDR

Data
lines IR
3 MDR out , IR in
4 R3 out , MAR in , Read Y
R0
5 R1 out , Yin , WMF C Constant 4
6 MDR out , SelectY, Add, Zin Select MUX

7 Zout , R1 in , End
Add
A B
ALU Sub R n - 1 
control ALU
lines
Carry-in
XOR TEMP
Figure 7.6. Con trol sequence for execution of the instruction Add (R3),R1.
Z
Figure 7.1. Single-bus organization of the datapath inside a processor.

• A branch instruction replaces the contents of PC with the branch

target address, which is usually obtained by adding an offset X given
in the branch instruction.
• The offset X is usually the difference between the branch target
address and the address immediately following the branch
instruction.
• UnConditional branch


Instruction execution proceeds as follows:

Step1--> The instruction-fetch operation is initiated by
→ loading contents of PC into MAR &
→ sending a Read request to memory.
The Select signal is set to Select4, which causes the Mux to
select constant 4. This value is added to operand at input B
(PC’s content), and the result is stored in Z.
Step2--> Updated value in Z is moved to PC. This completes the PC
increment operation and PC will now point to next instruction.

Step3--> Fetched instruction is moved into MDR and then to IR. The
step 1 through 3 constitutes the Fetch Phase.
At the beginning of step 4, the instruction decoder interprets
the contents of the IR. This enables the control circuitry to
activate the control-signals for steps 4 through 7.
The step 4 through 7 constitutes the Execution Phase.
Step4--> Contents of R3 are loaded into MAR & a memory read signal
is issued. Step5--> Contents of R1 are transferred to Y to
prepare for addition.

Step6--> When Read operation is completed, memory-operand is
available in MDR, and the addition is performed.
Step7--> Sum is stored in Z, then transferred to R1.The End signal
causes a new instruction fetch cycle to begin by returning to
step1.


• Allow the contents of two different registers to be accessed

simultaneously and have their contents placed on buses A and B.
• Allow the data on bus C to be loaded into a third register during

the same clock cycle.
• Incrementer unit.
• ALU simply passes one of its two input operands unmodified to

bus C
 control signal: R=A or R=B

• General purpose registers are combined into a single block called

registers.
• 3 ports,2 output ports –access two different registers and have their
contents on buses A and B
• Third port allows data on bus c during same clock cycle.
• Bus A & B are used to transfer the source operands to A & B inputs
of the ALU.
• ALU operation is performed.
• The result is transferred to the destination over the bus C.

• ALU may simply pass one of its 2 input operands unmodified to

bus C.
• The ALU control signals for such an operation R=A or R=B.
• Incrementer unit is used to increment the PC by 4.
• Using the Incrementer eliminates the need to add the constant
value 4 to the PC using the main ALU.
• The source for the constant 4 at the ALU input multiplexer can be
used to increment other address such as load multiple & store
multiple

Multiple-Bus Organization
• Add R4, R5, R6
Step Action
1 PCout , R=B, MAR in , Read, IncPC

2 WMFC
3 MDR outB , R=B, IR in
4 R4outA , R5outB , SelectA, Add, R6 in , End
• Step 1:The contents of PC are passed
through the ALU using R=B control signal & loaded into MAR to
start a memory read operation
At the same time PC is Incrementer by 4
• Step 2:The processor waits for MFC
• Step 3: Loads the data ,received into MDR ,then transfers them to
IR.
• Step 4: The execution phase of the instruction requires only one
control step to complete.

HARDWIRED CONTROL
• To execute instructions, the processor must have some means of
generating the control signals needed in the proper sequence.
• Two categories: hardwired control and microprogrammed control
• Hardwired system can operate at high speed; but with little
flexibility.

HARDWIRED CONTROL UNIT

Detailed Block Description

Generating Zin
• Zin = T1 + T6 • ADD + T4 • BR + …
Branch Add
T4 T6
T1
Generating End
• End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…
Branch<0
Add Branch
N N
T7 T5 T4 T5
End
Figure 7.13. Generation of the End control signal.

A Complete Processor
Instruction Integer Floating-point

unit unit unit
Instruction Data
cache cache
Bus interface
Processor
System bus
Main Input/
memory Output
Figure 7.14. Block diagram of a complete processor.

MICROPROGRAMMED CONTROL
• Microprogramming is a method of control unit design.
• Control-signals are generated by a program similar to machine
language programs.
• Control Word(CW) is a word whose individual bits represent
various control-signals (like Add, PCin).
• Each of the control-steps in control sequence of an instruction

defines a unique combination of 1s & 0s in CW.

• Individual control-words in microroutine are referred to as

microinstructions.
• A sequence of CWs corresponding to control- sequence of a
machine instruction constitutes the microroutine.
• The microroutine for all instructions in the instruction-set of a
computer are stored in a special memory called the Control
Store(CS).
• Control-unit generates control-signals for any instruction by
sequentially reading CWs of corresponding microroutine from CS.

• µPC is used to read CWs sequentially from CS. (µpc  Microprogram

Counter).
• Every time new instruction is loaded into IR, o/p of Starting Address
Generator is loaded into µPC.
• Then, µPC is automatically incremented by clock; causing successive
microinstructions to be read from CS. Hence, control-signals are
delivered to various parts of processor in correct sequence.

Basic organization of a microprogrammed

control unit
Starting
IR address
generator
Clock P C
Control
store CW
Figure 7.16. Basic organization of a microprogrammed control unit.

WMFC
MDRout
MARin
Select
PCout
Read
R1out
R3out
Micro -
Add
End
PCin
R1in
Zout
IRin
Yin
Zin
instruction
1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
Figure 7.15 An example of microinstructions for Figure 7.6.


CONDITIONAL BRANCH
• The previous organization cannot handle the situation when the control unit is
required to check the status of the condition codes or external inputs to
choose between alternative courses of action.
• Use conditional branch microinstruction.
Address Microinstruction
0 PC out , MAR in , Read, Select4, Add, Z in

1 Z out , PC in , Y in , WMF C
2 MDR out , IR in
3 Branch to starting address of appropriate microroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25 If N=0, then branch to microinstruction 0
26 Offset-field-of-IR out , SelectY, Add, Z in
27 Z out , PC in , End
Microprogrammed Control
External
inputs
Starting and
branch address Condition
IR codes
generator
Clock m PC
Control
store CW
MICROINSTRUCTIONS
• A straightforward way to structure microinstructions is to assign

one bit position to each control signal.
• However, this is very inefficient.
• The length can be reduced: most signals are not needed
simultaneously, and many signals are mutually exclusive.
• All mutually exclusive signals are placed in the same group in binary
coding.

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Department of Electronics &

Module -1: Basic Structure of Computers: Computer Types, Functional Units,

Module -3: Input/ Output Organization: Accessing I/O Devices, Interrupts –

03/22/2024 Dept. of ECE, ATMECE, Mysuru 2

Module-4: Memory System: Basic Concepts, Semiconductor RAM Memories

Module-5: Basic Processing Unit: Some Fundamental Concepts, Execution of a

03/22/2024 Dept. of ECE, ATMECE, Mysuru 3

Basic Processing Unit

03/22/2024 Dept. of ECE, ATMECE, Mysuru 4

• Some Fundamental Concepts

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03/22/2024 Dept. of ECE, ATMECE, Mysuru 8

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• This process is called 'decode'.

• The CPU is designed to understand a specific set of commands. These

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• Once the execute stage is complete, the CPU sets itself up to

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Figure 7.1. Single-bus organization of the datapath inside a processor.

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MDR has 2 inputs and 2 outputs. Data may be Control signals

→ into MDR either from memory-bus Address

(external) or MAR control logic

→ from processor-bus (internal). bus

• MAR’s input is connected to internal-bus; MAR’s Data

output is connected to external-bus. Y

• Instruction Decoder & Control Unit is Constant 4 R0

responsible for Select MUX

instruction (loaded in the IR).

• Register R0 through R(n-1) are the Processor

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• In ALU, 1) A input gets the operand from the output of the Y

2) B input gets the operand directly from the Select MUX

• There are 2 options provided for A input of the ALU. ALU

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Steps involved in the execution of an instruction

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register to another. • •• Riout

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Register Transfers • Internal processor

R1=25, R4=33 • •• Riout

2) Enable the input of register R4 by setting R4in

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Performing an Arithmetic or Logic Operation

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Performing an Arithmetic or Logic Operation

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Fetching a Word from Memory

Memory-bus Internal processor

Three input MUX

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Fetching a Word from Memory

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Timing of a memory read operation

2. Start a Read operation on Clock