It is used to send data to the output device such as display from the microprocessor.

The
simplest form of output port is a latch. The output device is connected to the
microprocessor through latch, as shown in the fig.2. When microprocessor wants to send
data to the output device is puts the data on the data bus and activates the clock signal of
the latch, latching the data from the data bus at the output of latch. It is then available at
the output of latch for the output device.
Serial and Parallel Transmission: In telecommunications, serial transmission is
the sequential transmission of signal elements of a group representing a character or
other entity of data. Digital serial transmissions are bits sent over a single wire,
frequency or optical path sequentially. Because it requires less signal processing and
less chance for error than parallel transmission, the transfer rate of each individual
path may be faster. This can be used over longer distances as a check digit or parity
bit can be sent along it easily. In telecommunications, parallel transmission is the
simultaneous transmission of the signal elements of a character or other entity of
data. In digital communications, parallel transmission is the simultaneous
transmission of related signal elements over two or more separate paths. Multiple
electrical wires are used which can transmit multiple bits simultaneously, which
allows for higher data transfer rates than can be achieved with serial transmission.
This method is used internally within the computer, for example the internal buses,
and sometimes externally for such things as printers, The major issue with this is
"skewing" because the wires in parallel data transmission have slightly different
properties (not intentionally) so some bits may arrive before others, which may
corrupt the message. A parity bit can help to reduce this. However, electrical wire
parallel data transmission is therefore less reliable for long distances because corrupt
transmissions are far more likely
Modes of Transfer
We store the binary information received
through an external device in the memory unit.
The information transferred from the CPU to
external devices originates from the memory
unit. Although the CPU processes the data, the
target and source are always the memory unit.
We can transfer this information using three
different modes of transfer.
Programmed I/O
Interrupt- initiated I/O
Direct memory access( DMA)
Programmed I/O
Programmed I/O uses the I/O instructions written in the
computer program. The instructions in the program initiate every
data item transfer. Usually, the data transfer is from a memory
and CPU register. This case requires constant monitoring by the
peripheral device's CPU.
Advantages:
Programmed I/O is simple to implement.
It requires very little hardware support.
CPU checks status bits periodically.

Disadvantages:
The processor has to wait for a long time for the I/O module to be
ready for either transmission or reception of data.
The performance of the entire system is severely degraded.
Interrupt-initiated I/O
In the above section, we saw that the CPU is kept busy unnecessarily. We can
avoid this situation by using an interrupt-driven method for data transfer. The
interrupt facilities and special commands inform the interface for issuing an
interrupt request signal as soon as the data is available from any device. In the
meantime, the CPU can execute other programs, and the interface will keep
monitoring the i/O device. Whenever it determines that the device is ready for
transferring data interface initiates an interrupt request signal to the CPU. As soon
as the CPU detects an external interrupt signal, it stops the program it was already
executing, branches to the service program to process the I/O transfer, and
returns to the program it was initially running.
Working of CPU in terms of interrupts:
CPU issues read command.
It starts executing other programs.
Check for interruptions at the end of each instruction cycle.
On interruptions:-
Process interrupt by fetching data and storing it.
See operation system notes.
Starts working on the program it was executing.
Advantages:
It is faster and more efficient than Programmed I/O.
It requires very little hardware support.
CPU does not check status bits periodically.
Disadvantages:
It can be tricky to implement if using a low-level
language.
It can be tough to get various pieces of work well
together.
The hardware manufacturer / OS maker usually
implements it, e.g., Microsoft.
Direct Memory Access (DMA)
The data transfer between any fast storage media like a memory unit and a
magnetic disk gets limited with the speed of the CPU. Thus it will be best to
allow the peripherals to directly communicate with the storage using the
memory buses by removing the intervention of the CPU. This mode of
transfer of data technique is known as Direct Memory Access (DMA). During
Direct Memory Access, the CPU is idle and has no control over the memory
buses. The DMA controller takes over the buses and directly manages data
transfer between the memory unit and I/O devices.
CPU Bus Signal for DMA transfer
 
Bus Request - We use bus requests in the DMA controller to ask the CPU to
relinquish the control buses.
Bus Grant - CPU activates bus grant to inform the DMA controller that DMA
can take control of the control buses. Once the control is taken, it can transfer
data in many ways
Types of DMA transfer using DMA controller:
Burst Transfer: In this transfer, DMA will return the bus
control after the complete data transfer. A register is used as
a byte count, which decrements for every byte transfer, and
once it becomes zero, the DMA Controller will release the
control bus. When the DMA Controller operates in burst
mode, the CPU is halted for the duration of the data transfer.
Cyclic Stealing: It is an alternative method for data transfer
in which the DMA controller will transfer one word at a time.
After that, it will return the control of the buses to the CPU.
The CPU operation is only delayed for one memory cycle to
allow the data transfer to “steal” one memory cycle.
Programmable Peripheral Interface
B
C

C
Modes of Operation of 8255
These are two basic modes of operation of 8255.
I/O mode and Bit Set-Reset mode (BSR).
In I/O mode, the 8255 ports work as programmable I/O ports,
while in BSR mode only port C (PC0-PC7) can be used to set or
reset its individual port bits.
Under the I/O mode of operation, further there are three
modes of operation of 8255, so as to support different types of
applications, mode 0, mode 1 and mode 2.
BSR Mode: In this mode any of the 8-bits of port C can be set or
reset depending on D0 of the control word. The bit to be set or
reset is selected by bit select flags D3, D2 and D1 of the CWR as
given in table.
All these modes can be selected by
programming a register internal to
8255known as CWR.
The control word register has two formats:
•The first format is valid for I/O modes of
operation, i.e. modes 0, mode 1 and mode 2
while
•the second format is valid for bit set/reset
(BSR) mode of operation.
a) Mode 0 (Basic I/O mode): This mode is also called as basic input/output Mode. This
mode provides simple input and output capabilities using each of the three ports. Data
can be simply read from and written to the input and output ports respectively, after
appropriate initialization.

The salient features of this mode are as listed below:

1. Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper and
lower) are
available. The two 4-bit ports can be combined used as a third 8-bit port.
2. Any port can be used as an input or output port.
3. Output ports are latched. Input ports are not latched.
4. A maximum of four ports are available so that overall 16 I/O configurations
are possible.
All these modes can be selected by programming a register internal to
8255known as CWR.
The control word register has two formats. The first format is valid for I/O
modes of operation, i.e. modes 0, mode 1 and mode 2 while the second
format is valid for bit set/reset (BSR) mode of operation
Mode 1: (S t r o b e d input/output mode) in this mode the handshaking
control the input and output action of the specified port. Port C lines
PC0-PC2, provide strobe or handshake lines for port B. This group which
includes port B and PC0-PC2 is called as group B for Strobed data
input/output. Port C lines PC3-PC5 provides strobe lines for port A. This
group including port A and PC3-PC5 from group A. Thus port C is
utilized for generating handshake signals.
The salient features of mode 1 are listed as follows:
1. Two groups group A and group B are available for strobed data
transfer.
2. Each group contains one 8-bit data I/O port and one 4-bit
control/data port.
3. The 8-bit data port can be either used as input and output port. The
inputs and outputs both are latched.
4. Out of 8-bit port C, PC0-PC2 are used to generate control signals for
port B
andPC3-PC5 are used to generate control signals for port A. the lines
PC6, PC7
may be used as independent data lines.
The control signals for both the groups in input and output modes are explained as
follows:
Input control signal definitions (mode 1):
STB (Strobe input) If this lines falls to logic low level, the data available at 8-
bit input port is loaded into input latches.
IBF (Input buffer full) If this signal rises to logic 1, it indicates that data has
been loaded into latches, i.e. it works as an acknowledgement. IBF is set by a low
on STB and is reset by the rising edge of RD input.
INTR (Interrupt request) This active high output signal can be used to
interrupt the CPU whenever an input device requests the service. INTR is set by a
high STB pin and a high at IBF pin. INTE is an internal flag that can be
controlled by the bit set/reset mode of either PC4 (INTEA) or PC2 (INTEB) as
shown in fig.
INTR is reset by a falling edge of RD input. Thus an external input device can be
request the service of the processor by putting the data on the bus and
sending the strobe signal.
Output control signal definitions (mode 1):
OBF (Output buffer full) This status signal, whenever falls to low, indicates
that CPU has written data to the specified output port. The OBF flip- flop will
beset by a rising edge of WR signal and reset by a low going edge at the ACK
input.
ACK (Acknowledge input) ACK signal acts as an acknowledgement to be given
by an output device. ACK signal, whenever low, informs the CPU that the data
transferred by the CPU to the output device through the port is received by the
output device.
INTR (Interrupt request) Thus an output signal that can be used to interrupt
the CPU when an output device acknowledges the data received from the
CPU.INTR is set when ACK, OBF and INTE are 1. It is reset by a
Falling edge on WR input. The INTEA and INTEB flags are controlled by the bit setreset
mode ofPC6 and PC2 respectively.
B
Mode 2 (Strobed bidirectional I/O): This mode of operation of 8255 is also
called as strobed bidirectional I/O. This mode of operation provides 8255
with additional features for communicating with a peripheral device on an
8-bit data bus. Handshaking signals are provided to maintain proper data
flow and synchronization between the data transmitter and receiver. The
interrupt generation and other functions are similar to mode 1.

In this mode, 8255 is a bidirectional 8-bit port with handshake signals. The Rd
and WR
signals decide whether the 8255 is going to operate as an input port or output
port.
The Salient features of Mode 2 of 8255 are listed as follows:
1. The single 8-bit port in group A is available.
2. The 8-bit port is bidirectional and additionally a 5-bit control port is available.
3. Three I/O lines are available at port C.( PC2, PC1 and PC0 )
4. Inputs and outputs are both latched.
5. The 5-bit control port C (PC3-PC7) is used for generating / accepting
handshake signals for the 8-bit data transfer on port A.
Control signal definitions in mode 2:
INTR (Interrupt request) As in mode 1, this control signal is active
high and is used to interrupt the microprocessor to ask for transfer
of the next data byte to/from it. This signal is used for input (read)
as well as output (write) operations.
Control Signals for Output operations:
OBF (Output buffer full) This signal, when falls to low level,
indicates that the CPU has written data to port A.
ACK (Acknowledge) This control input, when falls to logic low level,
Acknowledges that the previous data byte is received by the
destination and next byte may be sent by the processor. This signal
enables the internal tristate buffers to send the next data byte on
port A.
INTE1 ( A flag associated with OBF ) This can be controlled by bit
set/reset mode
with PC6.
Control signals for input operations:
STB (Strobe input)a low on this line is used to strobe in the data
into the input Latches of 8255.
IBF (Input buffer full) when the data is loaded into input buffer,
this signal rises to logic . This can be used as an acknowledge
that the data has been received by the receiver.
The waveforms in fig show the operation in Mode 2 for output as
well as input port.
Note: WR must occur before ACK and STB must be activated
before RD.