Getting Started Design With FPAG (ZYNC-ZED)

Getting Started
Design with FPGA

(Zedboard)
October 19, 2015

Radar & Antenna Lab
Chung-Ang University
Purpose
Design of Radar Signal Processor

 Matlab
 Simulink
 System Generator
 Vivado
 Porting to Zedboard (ZYNQ)
 Design Verification
Zedboard
PS AXI PL
PC uart ARM A GPIO
Address
X IP Core
ARM I
Data (real &
imag)
(System
Generation
designed)
Simple Logic Design Example
 Signal generation
 Single Frequency Sine signal
 AWG
AWG (NLFM)
Matlab Program of NLFM
System Generator
Xilinx Memory Block
Vivado work  Bitstream file
Xilinx SDK  Porting to Zedboard
Zedboard Run  Data Capture (data.txt)
Matlab  Data Loading and Plotting

AWG (NLFM)
1 2 3 4
System Vivado Xilinx SDK Matlab
Generator
(Generate the (Modify the C (Plot the figure
(Design the bitstream file) program and after receiving
Logic Flow obtain the the data)
by using data)
Matlab file)
Matlab Programming (Signal Generation)
 After opening the m-file “nlfm_marine.m” given

previously, run it.
 And then we can see the NLFM signal intuitively.
 Parameters will be formed and saved automatically in
the workplace of Matlab.
Important parameters will be used later.

 Ts
 Nsample_signal
 Signal to be generated
= Complex Signal
= (Real, Imag)
System Generator (In Simulink Environment)
The main window in System Generator
Button: Simulink Library
Determine the path in which

the file is saved
M-file of NLFM
signal generation
• When opening the main window in System Generator, it is almost the same to the Matlab.
• However, you will find some more function blocks in Simulink libraries’ list after you click the
“Simulink Library” .
• Firstly, the m-file of NLFM signal generation have to be saved in one folder which you will use.
Logic Design for Data Loading (Writing)
ADDRS 1 Data 1
2 Data 2
Real Data of NLFM
3 Data 3
ROM .
.
.
.
. .
N Data N
1 Data 1
2 Data 2
Imag Data of NLFM
ROM 3
.
Data 3
.
. .
. .
N Data N
1 Data 1
2 Data 2
3 Data 3 Real Data of NLFM
. .
. .
. .
N Data N
Courter
1 Data 1
2 Data 2
3 Data 3 Imag Data of NLFM
. .
. .
. .
N Data N
The final design of our aim is shown as above in the Simulink.
Next let us find each block in the Simulink library and set each parameter step by step.
Detailed Steps for System Generator
Logic Design
Xilinx Token
Libraries  Xilinx Blockset  Basic Elements:

System Generator
Firstly of all, We have to set up the “Xilinx System Generator” environment.

• Double click the icon “System
Generator”.
• Let us set up the parameters.
Chung-Ang University Microwave & Antenna Lab

• Compilation  IP Catalog
• Port  Zynq  xc7z020  -1  clg484
Simulation system period (sec): Ts

Libraries  Xilinx Blockset  Memory:
ROM
“ROM” is the key block in this example, and widely used in FPGA design.
Here this block is added in the subsystem.
ROM Setting
Basic:
Depth: Nsample_signal
Initial value vector: real(xref_sp2)
Output:
Number of bits: 16
Binary points: 15
ROM Setting
ROM Setting
ROM Setting
Basic:
Depth: Nsample_signal
Initial value vector: imag(xref_sp2)
Output:
Number of bits: 16
Binary points: 15
Other Blocks Settings
The remained blocks are easily found and added in the design.

Convert, Reinterpret
Convert
The settings of Convert is

defaults, need not be
changed.
Reinterpret
Reinterpret:
Tick “Force Binary Point”
Verification
Libraries  Simulink  Sources:

Counter limited
Double
Click
Upper limit: Nsample_signal-1

Sample time: Ts
Every design element is picked up and all the parameters are set.
Gateway In Setting
Arithmetic type: Unsigned

Libraries  Xilinx Blockset  Basic Elements: Number of bits: 13
Gateway In Binary point: 0
Sample period: Ts
Gateway In Setting
Double
Click
Gateway Out Setting

Gateway out
Libraries  Simulink  Sinks  Scope
If we want to see and check the signals from m-fine by the

Simulink, Scope is added better.
Run this Simulink program, and the signals
can be checked by the scope.
Double Click
“System Generator”
Click “Generate”
The last step of this section is to generate the IP catalog which we

design and will be used in the next section.
The IP catalog is generated successful.
Flowchart
1 2 3 4
Generator
by using data)
Matlab file)

Next Section is coming…
Double click the icon

“Vivado 2014.2”
Double click “Create New

Project”

Create New Project

Create New Project

Create New Project

Click “Boards” Create New Project
Choose “ZedBoard Zynq Evaluation and

Development”

The main widow of Vivado 2014.2
Click “Create Block Design”

Name the new design

Add IP  ZNYQ

1. Input “ZNYQ”.
2. Choose the first one “ZNYQ7 Processing
System”, and click it.
3. Double click “ZNYQ” , and settings have

to be done.

1. Presets  Zedboard
2. Click “Peripheral I/O Pins”

1. Click “Peripheral I/O Pins”
2. Tick two parts:
 UART 1
 GPIO MIO
3. Click “OK”

1. Run Block Automation
 /Processing_System7_0
2. Click “OK”

Successfully the most important IP part has been set.

Add IP  GPIO
1. Input “GPIO”.
2. Choose “AXI GPIO”, and click
it.

Double Click “GPIO”, and settings have to
be done.

Re-customze IP :AXIO GPIO setting
Board:
 Generate board based on IO Constraints
Re-customze IP :AXIO GPIO setting

IP Configuration:
 All Outputs
GPIO Width: 13
 Enable Dual Channel
 All Inputs
GPIO Width: 32

Add IP  Concat
1. Input “Concat”.
2. Choose “Concat”, and click it.
3. There are not any other
settings for “Concat”,all are
defaulted.

Add IP  IP Catalog
IP Settings
Repository Manager  Add Repository

1. Click “/NLFM_TEST  netlist  IP”
2. Click “Select”

Click “Add IP…”

Click “OK”

Click “OK”, and the IP we designed is added successfully.

The added IP which we designed could be checked here.

Open Block Design once more.
Add IP we designed previously.

1. Click “Add IP”
2. Input “nlfm_test1”.
3. Choose “nlfm_test1”, and click it.

All IPs in this block design are
presented here, next let us
connect them.

Connection
3 2
4

Connection
Run Connection Automation /axi_gpio_0/S_AXI

Click
“OK”

Run Connection Automation /GPIO

• Choose “Custom”
• Click “OK”

Run Connection Automation /GPIO2

• Choose “Custom”
• Click “OK”

Connection between these two points

Click here “Regenerate Layout”

The full block design is presented here. In the design there are four important parts including: ZYNQ
processing, GPIO, Concat, and nlfm_test1 which we designed in the system generator previously.

• Tools  Validate Design
• Click “OK”

• Find and Click “Sources  Hierarchy  Design Sources 
design_nlfm_test1”
• Then right click and choose “Generate Output Products…”
• Click “Generate”

Generate Output Products

• Find and Click “Sources  Hierarchy  Design Sources  design_nlfm_test1”
• Then right click and choose “Create HDL Wrapper…”

• Choose “Let Vivado manager wrapper and auto-update ”
• Click “OK”

• Find and click “Program and Debug  Generate
Bitsteam”
• Click “Save” and “Yes”

Now the bitstream file is being generated, and it will spend a little long time. Wait until the bitstream file is
generated successfully.

• When this window is presented, that means the operation of generating the bitstream file has
been finished.
• Please Choose “View Reports” , Click “OK”!

After the bitstream file has been generated, there are two steps remained in this processing.
• File  Export  Export Hardware, and then Click “OK”.
• File  Launch SDK, and then Click “OK”.

After the bitstream file has been generated, there are two steps remained in this processing.
• File  Export  Export Hardware, and then Click “OK”.
• File  Launch SDK, and then Click “OK”.

Welcome to the third processing. XILINX SDK will be opened automatically.

Flowchart
1 2 3 4
Generator
by using data)
Matlab file)

The Xilinx SDK is opened. Firstly the new application project need to be built. Three steps will be shown in blow:
• File  New  Application Project

• Input the project name “nlfm_test1” which you want and then Click “Next”.

• There are some choices in the Templates window. Generally “Empty Application” or ”Hello World” is
chosen, here we choose ”Hello World” , and then Click “Finish”.

The main window in Xilinx SDK

helloworld.c

helloworld.c
Input some codes in “helloworld.c”:
#include "xgpio.h"
#include "xil_printf.h"
XGpio gpio_1;

xparameters.h
Copy “XPAR _GPIO _0 DEVICE_ID ”

helloworld.c
Paste “XPAR _GPIO _0 DEVICE_ID ”

in “helloworld.c”
Input codes:
#define gpio_id_1 XPAR _GPIO _0

DEVICE_ID

xgpio.h
Find “Xgpio_Initiatilize” and

“Xgpio_setDataDirection” in
“xgpio.h”

helloworld.c
Input some codes in “helloworld.c”:
void init_gpio()
{
XGpio_Initialize(&gpio_1,gpio_id_1);
XGpio_SetDataDirection(&gpio_1,1,0);
XGpio_SetDataDirection(&gpio_1,2,0x1fff);
}

xgpio.c
Find “Xgpio_WriteReg””
in “xgpio.c”

helloworld.c
int main()
{
init_platform();
init_gpio();
u32 data_sig;
u16 data_r[5000],data_i[5000];
u32 ii=0;
for(ii=0;ii<5000;ii++)
{
XGpio_DiscreteWrite(&gpio_1,1,ii);
data_sig=XGpio_DiscreteRead(&gpio_1,2);
data_r[ii]=data_sig&0xffff;
data_i[ii]=(data_sig>>16)&0xffff;
xil_printf("%d\r\n",data_r[ii]);
xil_printf("%d\r\n",data_i[ii]);
}
cleanup_platform();
//print("Hello World\n\r");
return 0;
}

• Now please connect the lines between PC and
FPGA board.
• Then Click “Program FPGA”.
• Click “Program”.

Progress Information

Run  Run Configurations…

Please find the Port
connected with
FPGA board from
Device Manager by
your own computer
system.

• Run configuration.
• The data will be received and shown here.
• Copy all the data and save them in one
“txt” file named “data_nlfm_text1.txt”.

Copy all the data and save them in
one “txt” file named
“data_nlfm_text1.txt”.

1 2 3 4
Generator
by using data)
Matlab file)

clear all
close all
clc
load data_nlfm_text1.txt data_nlfm_text1.txt

aa=data_nlfm_text1(:,1);
ii=find(aa>2^15);
aa(ii)=aa(ii)-2^16;
figure(1)
nlfm_real=aa(1:2:length(aa)-1);
plot(nlfm_real)
1. Load the txt file to the Matalab program.
2. Input the Matlab codes which is saved from figure(2)
the last step 。 nlfm_imag=aa(2:2:(length(aa)));
plot(nlfm_imag)
3. Run the program, the last results will be
shown in the last slide.

Real part of NLFM Imaginary part of NLFM

The End
Thanks~~

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Getting Started

Design with FPGA

October 19, 2015

Design of Radar Signal Processor

 Porting to Zedboard (ZYNQ)

 Single Frequency Sine signal

Matlab Program of NLFM

Vivado work  Bitstream file

Xilinx SDK  Porting to Zedboard

Zedboard Run  Data Capture (data.txt)

Matlab  Data Loading and Plotting

 After opening the m-file “nlfm_marine.m” given

Important parameters will be used later.

Button: Simulink Library

Determine the path in which

Libraries  Xilinx Blockset  Basic Elements:

Firstly of all, We have to set up the “Xilinx System Generator” environment.

Chung-Ang University Microwave & Antenna Lab

Simulation system period (sec): Ts

Chung-Ang University Microwave & Antenna Lab

Libraries  Xilinx Blockset  Basic Elements:

The settings of Convert is

Libraries  Simulink  Sources:

Upper limit: Nsample_signal-1

Arithmetic type: Unsigned

Libraries  Xilinx Blockset  Basic Elements:

If we want to see and check the signals from m-fine by the

The last step of this section is to generate the IP catalog which we

Chung-Ang University Microwave & Antenna Lab

Double click the icon

Double click “Create New

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Choose “ZedBoard Zynq Evaluation and

Chung-Ang University Microwave & Antenna Lab

Click “Create Block Design”

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

3. Double click “ZNYQ” , and settings have

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Re-customze IP :AXIO GPIO setting

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab

Chung-Ang University Microwave & Antenna Lab