‫بسم هللا الرحمن الرحيم‬

Lecture (8)

Sequential Circuits Hardware

Description Language
Sequential System Design
Behavioral Modeling in SSD
There are two kinds of behavioral statements in Verilog
HDL: initial and always.
The initial behavior executes once beginning at time=0.
The always behavior executes repeatedly and re-executes
until the simulation terminates.
A behavior is declared within a module by using the
keywords initial or always, followed by a statement or
a block of statements enclosed by the keywords begin and
end.
Behavioral Modeling in SSD (2)
An example of a free-running clock

initial begin
clock = 1’b0;
repeat (30);
#10 clock = ~clock;
end

initial begin
clock = 1’b0;
#300 $finish;
end
always #10 clock = ~clock
 Behavioral Modeling in SSD (3)
The always statement can be controlled by delays that
wait for a certain time or by certain conditions to
become true or by events to occur.
This type of statement is of the form:
always @ (event control expression)
Procedural assignment statements
The event control expression specifies the condition
that must occur to activate the execution of the
procedural assignment statements.
The variables in the left-hand side of the procedural
statements must be of the reg data type and must be
declared as such.
 Behavioral Modeling in SSD (4)
The statements within the block, after the event control
expression, execute sequentially and the execution
suspends after the last statement has executed.
Then the always statement waits again for an event to
occur.
Two kind of events:
 Level sensitive (E.g. in combinational circuits and in latches)
always @(A or B or Reset) will cause the execution of the
procedural statements in the always block if changes occur in A or
B or Reset.
 Edge-triggered (In synchronous sequential circuits, changes in
flip-flops must occur only in response to a transition of a clock
pulse.
always @(posedge clock or negedge reset)will cause the
execution of the procedural statements only if the clock goes
through a positive transition or if the reset goes through a
negative transition.
 Behavioral Modeling in SSD (5)
A procedural assignment is an assignment within an
initial or always statement.
There are two kinds of procedural assignments: blocking
and non-blocking
 Blocking assignments (executed sequentially in the order they
are listed in a sequential block)
 B=A
 C=B+1
 Non-blocking assignments (evaluate the expressions on the
right hand side, but do not make the assignment to the left hand
side until all expressions are evaluated.
 B <= A
 C <= B + 1
 Flip-Flops and Latches
The D-latch is transparent and responds to a change in
data input with a change in output as long as control
input is enabled.
It has two inputs, D and control, and one output Q.
Since Q is evaluated in a procedural statement it must
be declared as reg type.
Latches respond to input signals so the two inputs are
listed without edge qualifiers in the event control
expression following the @ symbol in the always
statement.
There is one blocking procedural assignment statement
and it specifies the transfer of input D to output Q if
control is true.
 Flip-Flops and Latches

module D_latch(Q,D,control);
output Q;
input D,control;
reg Q;
always @(control or D)
if(control) Q = D; //Same as: if(control=1)
endmodule
Flip-Flops and Latches
//D flip-flop //D flip-flop with asynchronous reset.
module D_FF (Q,D,CLK); module DFF (Q,D,CLK,RST);
output Q; output Q;
input D,CLK,RST;
input D,CLK;
reg Q;
reg Q;
always @(posedge CLK or negedge RST)
always @(posedge CLK)
if (~RST) Q = 1'b0; // Same as: if (RST = 0)
Q = D; else Q = D;
endmodule endmodule
 D Flip-Flop with Reset
D Flip-Flop with
Asynchronous
Reset
T & J-K Flip-Flops
 T & J-K Flip-Flops
//T flip-flop from D flip-flop and gates //JK flip-flop from D flip-flop and gates
module TFF (Q,T,CLK,RST); module JKFF (Q,J,K,CLK,RST);
output Q; output Q;
input T,CLK,RST; input J,K,CLK,RST;
wire DT; wire JK;
assign DT = Q ^ T ; assign JK = (J & ~Q) | (~K & Q);
//Instantiate the D flip-flop //Instantiate D flipflop
DFF TF1 (Q,DT,CLK,RST); DFF JK1 (Q,JK,CLK,RST);
endmodule endmodule

Characteristic equations of the flip-flops:

Q(t  1)  Q  T for a T flip - flop
Q(t  1)  JQ' K ' Q for a JK flip - flop
J-K Flip-Flop
• Here the flip-flop is
// Functional description of JK // flip-flop described using the
module JK_FF (J,K,CLK,Q,Qnot); characteristic table rather
output Q,Qnot; than the characteristic
input J,K,CLK; equation.
reg Q; • The case multiway
assign Qnot = ~ Q ;
always @(posedge CLK)
branch condition checks
case({J,K})
the 2-bit number obtained
2'b00: Q = Q;
by concatenating the bits
2'b01: Q = 1'b0;
of J and K.
2'b10: Q = 1'b1; • The case value ({J,K}) is
2'b11: Q = ~ Q; evaluated and compared
endcase with the values in the list
endmodule of statements that follow.
D-Flip-Flop
//Positive Edge triggered DFF with Reset
module DFF(CLK,RST,D,Q);
input CLK,RST,D;
output Q;
reg Q;

always@(posedge CLK or posedge RST)

if (RST) Q<=0;
else Q<=D;
endmodule
Sequential Circuit
 Sequential Circuit (2)
//Mealy state diagram for the circuit
module Mealy_mdl (x,y,CLK,RST);
input x,CLK,RST;
output y;
reg y;
reg [1:0] Prstate,Nxtstate;
parameter S0=2'b00,S1=2'b01,S2=2'b10,S3=2'b11;
always@(posedge CLK or negedge RST)
if (~RST) Prstate = S0; //Initialize to state S0
else Prstate = Nxtstate; //Clock operations
 Sequential Circuit (3)

always @(Prstate or x) //Determine next state

case (Prstate)
S0: if (x) Nxtstate = S1;
S1: if (x) Nxtstate = S3;
else Nxtstate = S0;
S2: if (~x)Nxtstate = S0;
S3: if (x) Nxtstate = S2;
else Nxtstate = S0;
endcase
always @(Prstate or x) //Evaluate output
case (Prstate)
S0: y = 0;
S1: if (x) y = 1'b0; else y = 1'b1;
S2: if (x) y = 1'b0; else y = 1'b1;
S3: if (x) y = 1'b0; else y = 1'b1;
endcase
endmodule
Sequential Circuit (4)
 Sequential Circuit (5)
//Moore state diagram (Fig. 5-19)
module Moore_mdl (x,AB,CLK,RST);
input x,CLK,RST;
output [1:0]AB;
reg [1:0] state;
parameter S0=2'b00,S1=2'b01,S2=2'b10,S3=2'b11;
always @(posedge CLK or negedge RST)
if (~RST) state = S0; //Initialize to state S0
else
case(state)
S0: if (~x) state = S1;
S1: if (x) state = S2; else state = S3;
S2: if (~x) state = S3;
S3: if (~x) state = S0;
endcase
assign AB = state; //Output of flip-flops
endmodule
Sequential Circuit (6)
 Sequential Circuit (7)
//Structural description of sequential circuit
//See Fig. 5-20(a)
module Tcircuit (x,y,A,B,CLK,RST);
input x,CLK,RST;
output y,A,B;
wire TA,TB;
//Flip-flip input equations
assign TB = x,
TA = x & B;
//Output equation
assign y = A & B;
//Instantiate T flip-flops
T_FF BF (B,TB,CLK,RST);
T_FF AF (A,TA,CLK,RST);
endmodule
 Sequential Circuit (8)
//T flip-flop //Stimulus for testing seq. cir
module T_FF (Q,T,CLK,RST); module testTcircuit;
output Q; reg x,CLK,RST; //inputs for
circuit
input T,CLK,RST;
wire y,A,B; //output from circuit
reg Q;
Tcircuit TC(x,y,A,B,CLK,RST);
always@(posedge CLK or
negedge RST) initial begin
if(~RST) Q=1'b0; RST = 0; CLK = 0;
else Q=Q^T; #5 RST = 1;
endmodule repeat (16)
#5 CLK = ~CLK;
end
initial begin
x = 0; #15 x = 1;
repeat (8)
#10 x = ~ x;
end
endmodule
Sequence Recognizer
Sequence Recognizer (2)
Sequence Recognizer
module seq_recognizer(CLK,RST,X,Z);
input CLK,RST,X;
output Z;
reg [1:0]state, next_state;
parameter A=2’b00,B=2’b01,C=2’b10,D=2’b11;
reg Z;
always@(posedge CLK or posedge RST) begin
if(RST==1) state <= A;
else state <= next_state;
end
always@(X or state) begin
case(state)
A:if(X)next_state <= B; else next_state <= A;
B:if(X)next_state <= C; else next_state <= A;
C:if(X)next_state <= C; else next_state <= D;
D:if(X)next_state <= B; else next_state <= A;
endcase
end
always@(X or state) begin
case(state)
A:Z<=0;
B:Z<=0;
C:Z<=0;
D:Z<=X?1:0;
endcase
end
endmodule
 HDL for Registers and Counters
 Registers and counters can be described in HDL at either the
behavioral or the structural level.
 In the behavioral, the register is specified by a description of the
various operations that it performs similar to a function table.
 A structural level description shows the circuit in terms of a collection
of components such as gates, flip-flops and multiplexers.
 The various components are instantiated to form a hierarchical
description of the design similar to a representation of a logic diagram.
HDL for Registers and Counters (2)
HDL for Registers and Counters (3)

Clear CLK Load Count Function 4-bit binary

0 X X X Clear to 0 counter with
1 +ve 1 X Load inputs parallel load
1 +ve 0 1 Count next
binary state
1 +ve 0 0 No change

Mode Control Function

S1 S0 Register Operation table for 4-
0 0 No Change bit
0 1 Shift Right Universal
1 0 Shift Left Shift
1 1 Parallel Load Register
 HDL for Registers and Counters (4)
//Behavioral description of Universal shift register
module shftreg (s1,s0,Pin,lfin,rtin,A,CLK,Clr);
input s1,s0; //Select inputs
input lfin, rtin; //Serial inputs
input CLK,Clr; //Clock and Clear
input [3:0] Pin; //Parallel input
output [3:0] A; //Register output
reg [3:0] A;
always @ (posedge CLK or negedge Clr)
if (~Clr) A = 4'b0000;
else
case ({s1,s0})
2'b00: A = A; //No change
2'b01: A = {rtin,A[3:1]}; //Shift right
2'b10: A = {A[2:0],lfin}; //Shift left
//Parallel load input
2'b11: A = Pin;
endcase
endmodule
 HDL for Registers and Counters (5)
//Structural description of Universal shift register
module SHFTREG (I,select,lfin,rtin,A,CLK,Clr);
input [3:0] I; //Parallel input
input [1:0] select; //Mode select
input lfin,rtin,CLK,Clr; //Serial input,clock,clear
output [3:0] A; //Parallel output
//Instantiate the four stages
stage ST0 (A[0],A[1],lfin,I[0],A[0],select,CLK,Clr);
stage ST1 (A[1],A[2],A[0],I[1],A[1],select,CLK,Clr);
stage ST2 (A[2],A[3],A[1],I[2],A[2],select,CLK,Clr);
stage ST3 (A[3],rtin,A[2],I[3],A[3],select,CLK,Clr);
endmodule
 HDL for Registers and Counters (6)
//One stage of shift register
module stage(i0,i1,i2,i3,Q,select,CLK,Clr);
input i0,i1,i2,i3,CLK,Clr;
input [1:0] select;
output Q;
reg Q,D;
//4x1 multiplexer
always @ (i0 or i1 or i2 or i3 or select)
case (select)
2'b00: D = i0;
2'b01: D = i1;
2'b10: D = i2; //D flip-flop
2'b11: D = i3; always@(posedge CLK or negedge Clr)
endcase if (~Clr) Q = 1'b0;
else Q = D;
endmodule
HDL for Registers and Counters (7)

4 bit Binary
Counter with
Parallel Load
HDL for Registers and Counters (8)

//Binary counter with parallel load

module counter (Count,Load,IN,CLK,Clr,A,CO);
input Count,Load,CLK,Clr;
input [3:0] IN; //Data input
output CO; //Output carry
output [3:0] A; //Data output
reg [3:0] A;
assign CO = Count & ~Load & (A == 4'b1111);
always @(posedge CLK or negedge Clr)
if (~Clr) A = 4'b0000;
else if (Load) A = IN;
else if (Count) A = A + 1'b1;
else A = A; // no change, default condition
endmodule
HDL for Registers and Counters (9)
4-bit Binary
Ripple
Counter
 HDL for Registers and Counters (10)
//Ripple counter
module ripplecounter(A0,A1,A2,A3,Count,Reset);
output A0,A1,A2,A3;
input Count,Reset;
//Instantiate complementing flip-flop
CF F0 (A0,Count,Reset);
CF F1 (A1,A0,Reset);
CF F2 (A2,A1,Reset); //Complementing flip-flop with delay
CF F3 (A3,A2,Reset); //Input to D flip-flop = Q'
endmodule module CF (Q,CLK,Reset);
output Q;
input CLK,Reset;
reg Q;
always@(negedge CLK or posedge Reset)
if(Reset) Q=1'b0;
else Q=#2 (~Q);//Delay of 2 time units
endmodule
 HDL for Registers and Counters (11)

//Stimulus for testing ripple counter

module testcounter;
reg Count;
reg Reset;
wire A0,A1,A2,A3;
//Instantiate ripple counter
ripplecounter RC (A0,A1,A2,A3,Count,Reset);
always
#5 Count = ~Count;
initial
begin
Count = 1'b0;
Reset = 1'b1;
#4 Reset = 1'b0;
#165 $finish;
end
endmodule