Unit 1 : HDL DESIGN

Introduction to VHDL
 What is VHDL?

• VHDL stands for VHSIC Hardware

Description Language.
• VHSIC is an abbreviation for Very High
Speed Integrated Circuit, a project
sponsered by the US Government and Air
Force begun in 1980 to advance techniques
for designing VLSI silicon chips.
VHDL is an IEEE standard.
 Using VHDL for design synthesis

The design process is a 6 step cycle:

• Define the design requirement
• Describe the design in VHDL code
• Simulate the source code
• Synthesize, optimize, and fit the design
• Simulate the design
• Implement the design
 Design requirements

Required setup, clock requirements,

maximum operating frequency, critical
paths.
Describe the design in VHDL code
Prior to this a design methodology should be used
to describe the system. The most common of these
are:

• Top-down : In top-down, the main functional 

blocks are first defined, where each block has its 
defined inputs and outputs and is performing a 
specific function. Then a description of lower 
levels follows.
•Bottom-up : In this case first the
individual blocks are defined and designed
and then they are brought together to
form the overall design.

•Flat : In this case the design is normally

simple and does not need a hierarchical
approach.
 Simulate the source code

• This is an important feature of Hardware

Description Languages as the simulation is
done before the synthesis and design stage.
 Synthesize, optimize and fit the design

• Synthesis tools in VHDL, allow designers to

design logic circuits by creating design
descriptions without necessarily having to
perform Boolean algebra or create
technology-specific, optimized functions.
Optimization process, is the process
of minimizing the circuitry by means
of reducing the sum of product terms.
However, the process is multi-objective
and dependent on the expression being
realized and the device used in
implementation
Fitting, is the process of taking the logic
produced by the synthesis and optimization
processes and placing it into a logic
device.

Place and route, is fitting the logic into the

logic device and placing the logic elements
in optimal locations and routing the signals
from one unit to another in an optimal
way.
 Design Entity

A design entity is design element in VHDL

and consists of:
• an entity declaration and
• an architecture body.
A

B
F

D
 Entity

An entity body describes the input and output

pins (ports) of the design entity.

entity AOI is
port ( A , B , C , D : in STD_LOGIC ;
F : out STD_LOGIC ) ;
end AOI ;
architecture V1 of AOI is
begin
F <= not ( ( A and
B ) or ( c and D ) )
;
end V1 ;
 Entity Declaration

Each port in an entity should include :

• name of the signal (identifier)
• direction (mode)
• data type
Modes : There are four default modes
in VHDL
in : input into the entity ( unidirectional)
out : output from the entity( unidirectional)
inout : input and output to and from the entity
( bidirectional signals )
buffer : behaves in a similar way as inout,
but the source of the buffered signal is always
determined by the driving value of the port.
 Data Types
There are scalar and array data types
in VHDL.
array types example
string “abc”
bit_vector “1001”
std_logic_vector “101Z”
 Scalar example
type
character ‘a’
bit ‘1’ ‘0’
std_logic ‘0’ forcing 0
‘1’ forcing 1
‘x’ forcing unknown
‘z’ high impedance
‘-‘ don’t care
‘L’ weak 0
‘H’ weak 1
‘U’ uninitialized
boolean true false
real 2.35 -1.0E+38
integer 832 -1
time fs, ps, ns, us, ms, sec, min, hr
 Signals
An internal connection is described in VHDL as a
signal defined inside the architecture.
A AB

B O
F
C
CD
D

architecture V2 of AOI is
signals AB, CD, O : STD_LOGIC ;
begin
AB <= A and B after 2 NS;
CD <= C and D after 2
NS;
O <= AB or CD after 2 NS;
F <= not O after 1 NS;
end V2 ;
Operator Used in VHDL
 Concurrent Statements
• VHDL statements are grouped into sequential and
concurrent statements. Concurrent statements are
used in data flow and structural descriptions.
Sequential statements are used in bahavioral
descriptions

Concurrent statements are mainly:

Concurrent signal assignment statements with
BOOLEAN equations
 Selective signal-assignment (with-select-
when) Conditional statements (if-then-else)
 Data Flow Modeling
• Data flow model specifies the functionality of the entity without
explicitly specifying its structure.
• The functionality shows the flow of information through the entity.
• Expressed using concurrent signal assignment statements.
• Concurrent code is called as Data flow code.
Concurrent Statements
• All concurrent statements in an architecture are executed simultaneously
• Can be used to express parallel activity.
• They can be used for dataflow, behavioral and structural descriptions.
• Process is the only concurrent statement in which sequential statements
are allowed.

Example

Output /signal<= expression containing signals, input/value;

Sun<=a xor b;
Y<=“0010” ;
Conditional Signal Assignment (when statement)
This type of assignment has one target but multiple expressions.
This statement assigns value based on the priority of the condition
Syntax
Signal _name<= expression1 when condition 1 else
expression2 when condition 2 else

…. Expression N;
Example
Architecture Beh of My_nand is 
Begin
C<=‘0’when a<=‘1’and b<=‘1’ else
‘1’;
- Example write a VHDL program of 4:1 Mux by using when statements
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux is
Port (I0,I1,I2,I3 : in std_logic;
sel:std_logic_vector(1 downto 0);
z: out std_logic);
end mux;
architecture Behavioral of mux is
begin
z<=I0 when sel=“00” else
I1 when sel="01“ else
I2 when sel= "10“ else
I3 ;
end Behavioral;
Selective signal assignment( with-select statement)
Syntax
With expression select
Target<=expression1 when choice1,
expression2 when choice2,
expression3 when choice3,
…
Expression N when others,
- All possible choices should be enumerated
- Compared to the when statement, in the with statement choice is limited
to the choices provided by the with expression whereas for the when
statement, each choice can be a separate expression
- With statement does not have any priority.
- Example write a VHDL program of 4:1 Mux by using With select
statements
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux is
Port (I0,I1,I2,I3 : in std_logic;
sel:std_logic_vector(1 downto 0);
z: out std_logic);
end mux;
architecture Behavioral of mux is
begin
with sel select z<=I0 when "00",
I1 when "01",
I2 when "10",
I3 when"11",
'0' when others;
end Behavioral;
 Concurrent Statements
A concurrent signal assignment is triggered by an
event on a signal. An event is a change in value.

An event on the input port A would trigger the

assignment to AB

port (A, B, C, D: in STD_LOGIC;

...
AB <= A and B after 2 NS;
 port (A, B, C, D: in STD_LOGIC;
...
AB <= A and B after 2 NS;

A
B 2 NS

AB
AB <= A and B after 2 NS;
CD <= C and D after 2 NS;
O <= AB or CD after 2 NS;
F <= not O after 1 NS;

AB

F
 Process Statement
• In architecture all process are concurrent.
• In VHDL, Process statements contains only sequential
statement.

• Process statements is a primary concurrent statement used to

describe sequential behavior.
• All statement in process executed sequentially.
• All processes in an architecture execute concurrently
• Signals to which some value is assigned within a process are not
updated until the process suspends.
• Syntax of Process declaration is
Process(sensitivity list)
Declaration part
Begin
Sequential statements
End Process
• In declaration part types, variables, constant, subprograms can
be declared.
• Process never stops, it repeats forever unless suspend.
• To suspend the process unless sensitivity list or wait statement
 Sensitivity List
It is the list of signals to which process is sensitive.
Sensitivity list defines the signal that cause the statement inside the process
statements to execute whenever one or more elements of the list changes its
value.
Process executes when one of the signal in the sensitivity list changes.
Only static signal names are allowed in the sensitivity list.
 GENERATE Statement
• It is used to select concurrent statements conditionally.it is
alternative to structural modeling.
• It is a type of loop and is used outside the process statement
• It is used to create multiple copies of components, processes,
blocks i.e. it provide a compact description.
• Generate statement have two forms
• 1) For generate- It executes concurrent statements number of
times.
• Syntax
Label: for identifier in range generate
{concurrent statement}
End generate [label]
• 2) If generate
Label: if condition generate
{concurrent statement}
End generate [label]
Example:10 input and gate VHDL code by
using generate statement
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and10 is
Port (a,b : in std_logic_vector (9 downto 0);
c: out std_logic_vector (9 downto 0);
);
end and10;
architecture Behavioral of and10 is
Component and123
Port(a,b: in std_logic;
c: out std_logic);
End component;
begin
Lab1: for n in std_logic_vector (9 downto 0) generate and10 : and123
Port map(a=>a(n),b=>b(n) , c=>c(n));
End generate lab1;
end Behavioral;
Ii
Block Statement
• Main purpose of block statement is organizational only.
• It construct only separate part of the code without adding any
functionality
• Syntax
Label : Block(block declarative item)
Begin
Concurrent statement
End block [label]
Write a VHDL code to design D-Latch
When clk<=1 q<=d else q<= db
Entity dlatch is
Port(d, clk : in std_logic;
q,qb: out std_logic);
End dlatch;
Architecture Arch_dlatch of dlatch is
Begin
B1: block(clk=‘1’)
Begin q<= guarded d;
Qb<= guarded not(d);
End block; End Arch_dlatch;
 Components
A component is analogous to a chip socket. It
creates an extra interface which allows
more flexibility when building hierarchical
system out of its component parts.
Component instantiation statement
• Component is predesigned, preanalyse, precompile entity architecture pair.
• For example VHDL code for half adder is written, compile and verified and
place in design libraries then the full adder design
Syntax
component
component_name port list ( actual arguments same as precompile file) ;
end component;
Component Instantiation
• It is selecting a compiled specification of component and linking with the
architecture where it will be used
• Component Instantiation statement is used to build a netlist in VHDL by
referring a previously defined hardware component in current design .
Syntax
Instant_Name: component_name Port map( port name Expression );
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUX2 is
port (SEL, A, B: in STD_LOGIC;
F: out STD_LOGIC);
end MUX2;

SEL
A

F
SELB
B
architecture STRUCTURE of MUX2 is
component INV
port (A: in STD_LOGIC;
F: out STD_LOGIC);
end component;
component AOI
port (A, B, C, D: in STD_LOGIC;
F: out STD_LOGIC);
end component;
signal SELB: STD_LOGIC;
begin
G1: INV port map(SEL,
SELB);
G2: AOI port map(SEL, A, SELB, B, F);
end STRUCTURE;
 Variables
Previously we have looked at signals as
electrical connections or “pieces of wires”.
Variables can be pieces of wire too, but they can also
be more abstract.
Variables can represent wires, registers, or be used to
store intermediate values in abstract calculations.

variable V: STD_LOGIC;

Variables must be defined inside a process, before

begin (unlike signals which are defined in an
architecture).
 Variables

Previously we have looked at signals as

electrical connections or “pieces of wires”.
Variables can be pieces of wire too, but they can also
be more abstract.
Variables can represent wires, registers, or be used to store
intermediate values in abstract calculations.

variable V: STD_LOGIC;

Variables must be defined inside a process, before begin

(unlike signals which are defined in an architecture).
 A variable has a name and a type, just like a signal.

-- Assume A = '0', B = '0', C = '1'

process (A, B, C)
variable V: Std_logic; [ V = ’U’ ]
begin
V := A nand B; [ V = ’1’ ]
V := V nor C; [ V = ’0’ ]
F <= not V;
end process;

Variables behave quite differently to signals; variable assignments never have

a delay. Signal assignments always have a delay (even if it is a delta delay ).
architecture ... When this process is synthesized, each
variable assignment creates a new logic level.
signal F: Std_logic; A new wire is synthesized to hole the value of
the variable each time it is assigned.
begin
process (A, B, C)
variable V: Std_logic;
begin A V
V := A nand V
B; V := V nor
F
B C
C; F <= not V;
end process;

process
(F) begin
... A variable can be used ONLY inside the
end process. So, if we want a value passed
process; between processes, we MUST use a signal.
 Structural Description

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity COMP4 is
port ( A, B : in STD_LOGIC_VECTOR ( 3 downto 0);
F : out STD_LOGIC) ;
end COMP4;

use WORK.GATESPKG.all ;
architecture STRUCT of COMP4 is
signal x : STD_LOGIC_VEXTOR ( 0 to 3 );
begin
u0: xnor2 port map (a(0) , b(0) , x(0)) ;
u1: xnor2 port map (a(1) , b(1) , x(1)) ;
u2: xnor2 port map (a(2) , b(2) , x(2)) ;
u3: xnor2 port map (a(3) , b(3) , x(3)) ;
u4: and4 port map (x(0) , x(1) , x(2) , x(3) , F) ;

end STRUCT;
 Process Statement Execution

A process is an operation that involves a number of

parameters identified in a sensitivity list:
proc_x : process (a , b , c )
begin
x <= a and b and c;
end process;

A process is either being executed or suspended. It is

executed when one of the signals in its sensitivity list had an
event, a change of value.

The process continues to execute until the last

statement is reached or it encounters a wait statement. It
then suspends itself.
A wait statement: is a sequential statement which causes a
process to be suspended. It can wait for a period of time
(wait for), an event on a signal in the sensitivity list (wait
on), a boolean condition to become true (wait until), or
forever (wait ;).

proc_x : process
begin
x <= a and b and c;
wait on a , b , c ;
end process;

The process is used to describe the behaviour of a part of a

system without getting into the details of the implementation,
so can be used to describe hardware at high level of
abstraction.
 Process Statements
Two types of processes
1) Combinational Process
2) Clocked l Process
• Combinational Process It generates combinational logic
All the inputs must be present in the sensitivity list
Process(a,b,c)
Begin
X<=(a and b) or c;
End process;
• Clocked process
Process(clk)
Begin
If(clk’event and clk=‘1’)
q<=d;
End if;
End process;
Any signal assigned under a clk’ event generates a flip-flop.
 Sequential Statements
If Statements
An if statement is a sequential statement which conditionally executes other
sequential statements, based on the value of a Boolean condition.
An if statement can contain any number of other statements, including
other nested if statements.
If condition1 then
{sequential statement}
Elsif condition2 then
{sequential statement}
Else
{sequential statement}
End if;

• If statements evaluates each condition in order

• Statements can be nested.
 Avoid using more than three levels of
if ….else statements
When defining the condition use
parenthesis to differentiate levels of
Process(a,b,c,x) operation on the condition
Begin Process(sel,a,b,c,d)
If(x=“0000”) then Begin
x<=a; If sel(2)=‘1’ then
Elsif(x=“0101”) then Y<=a;
x<=b; Elsif sel(1)=‘1’ then
Else Y<=b;
x<=c; Elsifsel(0)=‘1’ then
End if; Y<=c;
End process; Else
Y<=d;
End if;
End process;
It generates a priority structure
Corresponding to when else command
in the concurrent part
An if statement is synthesised by generating a
multiplexer for every signal or variable assigned
within the statement.
The condition given at the top of the if statement
forms the select input to the multiplexer.

if C1 = '0' then A
V := A; V
else
V := B; B
end if
In the example below the if statement does not have an else part,
but the assignment V within the if still synthesizes to a
multiplexer.

if C2 = '1' and C3 = '1' then

V := not V;
end if;
C1
C2

V
V

If the condition is false, the previous value of V is fed through the

multiplexer unaltered.
Nested if Statements

Each if must be balanced with an end if.

process (C0, C1, C2, A, B, C, D)

begin
if C0 = '1' then
F <= A;
elseif C1 = '1' C2
thenF <= B; D
elseif C2 = '1' then
F <= C; C
else
F <= D; F
B
end if;
A
end if;
end if;
end
 The elseif allows multiple tests to be cascaded together,
such that only the branch following the first true
condition is executed.

process (C0, C1, C2, A, B, C, D)

begin
if C0 = '1' then
F <= A;
elsif C1 = '1'
then
F <= B;
elsif C2 = '1' then
F <= C;
else
F <= D;
end if;
end process;
 Case Statements
The expression at the top of the case is evaluated and compared with the
expressions following the whens. The statments within the matching when
branch are executed, then control jumps to the statement following end case.
Syntax case expression is
When choice1=>{statements}
When choice 2=>{statements}
End case; SEL
case SEL is when 2
"00" => F <= A;
when "01" => F <= B;
when "10" => F <= C; A
when "11" => F <= D;
when others <= null; F
end case; B
C

:case statements is a series of parallel checks to check a condition just like

D
with select. Statements following each when clause is evaluated only if the
choice value matches the expression value.
 Invalid case statements
Signal value:integer range 0 to 15;
Signal out_1: BIT;
Ex1 case value is
End case
-must have at least one when clause
Ex2 Case value is
When 0=>out_1<=‘1’;
When 1=>out_1<=‘0’;

End case;
Invalid:- values 2 to 15 are not covered by choices
Ex-3
Case value is
When 0 to 10=>out_1<=‘1’;
When 5 to 15=>out_1<=‘0’;

End case;
Invalid:- Choices 5 to 10 overlap
It is possible to cover several cases in the same when branch
by separating the values with vertical bars. In this example
the branch is executed if ADDRESS is:
16, 20, 24 or 28.

case ADDRESS is

when 16 | 20 | 24 | 28 =>
A <= '1';
B <= '1';

when others =>

end case;
 Null Statments
Does not perform any action
Can be used to indicatn some that when some conditions are
met no action is to be performed
Example
case SEL is when "00" => F <= a;
when "01" => F <= a;
when "10" => F <= b;
when "11" => F <= c;
when others <= null;
end case;
Each branch can also include any number of sequential
statements including other nested case statements as well!!

case ADDRESS is

when 16 | 20 | 24 | 28 =>
A <= '1';
B <= '1';

when others =>

end case;
The null statement means do nothing

A <= '0';
B <= '0';

case ADDRESS is

when 0 to 7 =>
A <= '1';
when 8 to 15 =>
B <= '1';
when 16 | 20 | 24 |
28 =>
A <= '1';
B <= '1';
when others =>
null;
It is possible also to cover a whole range using the case statement.

case ADDRESS is

when 0 to 7 =>
A <= '1';

when 8 to 15 =>
B <= '1';

when 16 | 20 | 24 |
28 =>
A <= '1';
B <= '1';

when others =>

end case;
 If ADDRESS is:
1) =9
2) =19
What will be the values of A and B?
A <= '0';
B <= '0';

case ADDRESS is

when 0 to 7 =>
A <= '1';

when 8 to 15 =>
B <= '1';

when 16 | 20 | 24 |
28 =>
A <= '1';
B <= '1';

when others =>

null;
Case versus if:

1) if is used when priority is desired.

2)in cases of more than three branches, case is
preferred.
 LOOPS
There are 3 different kinds of loop statements in
VHDL:
1) While loop repeats the enclosed sequence of
statements if the condition tested is true
The while loop, tests a boolean condition at the
top of the loop, and only leaves the loop when
the condition is false.
Sequence of statement will execute still the
condition is true.
While loop
Loop lable:while CONDITION loop
Sequence_of _statements
end loop loop_lable;
Ex:- process(a)
Begin
i:=0;
L1: while i<10 loop
i:=i+2;
End loop L1;
End process;
2) The unbounded loop statement simply loops forever.
Loop
...
exit;
..
exit when CONDITION;
end loop;
Ex:- L1 –LOOP WHEN(I<5)
Ex:-
sum:=1; j:=0;
l3: loop
j:=j+21;
sum:=sum*10;
if sum>100 then
exit l3;
end if
end loop l3;
 FOR Loops
The FOR loop is a sequential statement which is
used to execute a set of sequential statements
repeatedly.
The loop is executed once for each value in the
range.
The range determines no of execution of loops.
The range is tested at the beginning of the loop
execution.
The loop parameter is a constant which may be
used but not altered
Loop counter only exists within the loop.
The syntax is
Loop_lable: for loop_paramenter in range loop
Sequence_of_statements;
End loop loop_lable;
The range can be ascending or descending, but the loop
parameter cannot change in increments greater than 1.

for I in 0 to 3 loop
F(I) <= A(I) and B(3-I);
V := V xor A(I);
end loop;

for I in 3 downto 0 loop

F(I) <= A(I) and B(3-I);
V := V xor A(I);
end loop;
The loop parameter is technically a constant, which
means that its value cannot be changed using an
assignment.

You cannot jump out of a loop by forcing the value of the

loop parameter

for I in 0 to 3 loop
F(I) <= A(I) and B(3-I);
V := V xor A(I);
if V = 'X' then
I := 4;
end if;
end loop;
FOR Loop are synthesized by making
multiple copies of the logic synthesized
inside the loop, one copy for each possible
value of the loop parameter.
process (A, B) A(0)
F(0)
B(3)
variable V: Std_logic;
begin
A(1)
V := '0'; B(2)
F(1)

for I in 0 to 3 loop
F(I) <= A(I) and B(3-I); A(2)
V := V xor A(I); B(1)
F(2)

end loop;
G <= V; A(3)
end B(0)
F(3)

process;
0

A(0
)
A(1
) A(2) G
A(3
)
ClockGenerator_1: process
begin
for I in 1 to 1000 loop
Clock <= '0';
wait for 5 NS;
Clock <= '1';
wait for 10 NS;
end loop;
wait;
end process
ClockGenerator_
1;
ClockGenerator_2: process
begin
while NOW < 15 US loop
Clock <= '0';
wait for 5 NS;
Clock <= '1';
wait for 10 NS;
end loop;
wait;
end process
ClockGenerator_
2;
ClockGenerator_3: process
begin
loop
Clock <= '0';
wait for 5 NS;
Clock <= '1';
wait for 10
NS;
exit when NOW >= 15 US;
end loop;
wait;
end process
ClockGenerator_3;
 Sequential Logic:Latches
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LATCH is
port (ENB, D: in STD_LOGIC;
Q: out STD_LOGIC);
end;
architecture BEHAVIOUR of
LATCH
is
begin
proce
ss
(EN
B,
D)
begin
 process (ENB, D)
begin
if ENB = '1' then
Q <= D;
end if;
end process;

The use of transparent latches is discouraged in some FPGA

technologies because the implementation requires asynchronous
feedback
 Edge Triggered Flip-Flops

This is achieved by using the signal attribute’EVENT as follows:

process (Clock)
begin

if Clock'EVENT and Clock = '1' then

Q0 <= D0;
Q1 <= D1;

end if;

end process;

Each signal has a signal attribute S’EVENT, which has a boolean value True
or False.
S’Evant changes during any delta in which there is an event on the
signal (i.e. signal changes value).

process
begin
...
S <=
'1';
wait for 10 NS;
S <= '1';
wait for 10 NS;
S <= '0';
wait for 10 NS;
S <= '0';
...
 Rising_edge and Falling_edge Functions
Testing for a clock edge is such a common requirement that the package
std_logic_1164 includes standard functions Rising_edge and
Falling_edge .

The functions are given a signal of type STD_LOGIC and return a value
which is either True or False.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
...
process (Clock)
begin

if RISING_EDGE(Clock) then
Q <= D;
end if;

end process;
process (Clock)
begin
if Clock'EVENT and Clock = '1' then
Q <= D;
end if;
end process;

process (Clock)
begin
if RISING_EDGE(Clock) then
Q <= D;
end if;
end process;

Not all synthesis tools support the RISING_EDGE and

FALLING_EDGE functions.
 Synchronous operations and Asynchronous operations can be
described within a single process.

...
signal Count :
STD_LOGIC_VECTOR(7 downto 0);
begin
process (Clock, Reset)
begin Loa
Dat Rese
if Reset = '0' then a d
t
Count <= "00000000"; Count
elsif RISING_EDGE(Clock) then
if Load = '1' then '1'
Count <= Data;
else + Cloc
k
>

Count <= Count + '1';

end if;
end if;
end process;
process (Clock)
begin
if
RISING_ED
GE(Clock)
then Reset
if Reset = '1' then
Q <= '0';
Q
Data
elsif Enable = '1' then
Enabl
Q <= Data;
end if; e
Cloc >
end if; k
end
process;
Wait until Statement

It suspends the process until a condition becomes True. The condition

can be any Boolean expression.

Another_Flipflop: process
begin Rese
wait until Clock = '1'; t
if Reset = '1' then Q
Q <= '0'; Dat
else a
Q <= D;
end if;
end process; Cloc >
k
Another_Flipflop: process

begin
wait until RISING_EDGE(Clock);

if Reset = '1' then Rese

Q <= '0'; t
else Q
Q <= D; Dat
end if; a
end process;
Cloc >
k
 Concatenation
• The concatenation operator “&” is used to
join together two arrays end to end to make
one longer array

Signal A,B: STD_LOGIC_VECTOR(7 downto 0);

Signal F: STD_LOGIC_VECTOR(15 downto 0);

F<= A & B;
 • Concatenation can also be used to
concatenate arrays with single bits, or even
bits with bits.

Signal A,B,C: STD_LOGIC;

Signal F: STD_LOGIC_VECTOR(3 downto 0);

F(3 downto 1) <= (A & B) & C;

F(3) = A
F(2) = B
F(1) = C
F(0) = unchanged
• Shift and rotate operations can be
performed in one line by combining
concatenation with slice names.

Signal Reg: STD_LOGIC_VECTOR(7 downto 0);

Reg <= Reg(6 downto 0) & ‘0’;

Shift left one digit

Reg <= Reg(6 downto 0) & Reg(7);

Rotate left one digit

 Shift and Rotate
• In VHDL these operations can be
performed also using the shift and rotate
operators:
• Shift left / right logical : sll srl
• Shift left / right arithmatic : sla sra
• Rotate left / right : rol ror
 Signal Reg: STD_LOGIC_VECTOR(7 downto 0);

Reg <= ‘0’ & Reg(7 downto 1);

Reg <= Reg srl 1;
Ex:- A =0010101
Shift right one digit
A=0001010

Reg <= Reg(0) & Reg(7 downto 1);

Reg <= Reg ror 1;
Ex:- A =0010101
A=1001010 Rotate right one digit

Reg <= ‘1’& Reg(7 downto 1);

Shift right arithmetic
Reg <= Reg sra 1; one digit
A=0010101
A=1001010
 Signal Reg: STD_LOGIC_VECTOR(7 downto 0);

Reg <= ‘0’ & Reg(7 downto 1) ;

Reg <= Reg sll 1;
Ex:- A =0010101
Shift left one digit
A=0101010

Reg <= Reg(6 downto 0) & Reg(7);

Reg <= Reg rol 1;
Ex:- A =0010101
A=0101010 Rotate left one digit

Reg <= Reg(6 downto 0) & ‘1’;

Shift left arithmetic one
Reg <= Reg sla 1; digit
A=0010101
A=0101011
 Example
Variable A: STD_LOGIC_VECTOR (3 downto 0);
...
A:= “0110”;

• What is the value of this expression?

A(0) & ‘1’ & A(2 downto 1)

“0111”