MACHINE-LEVEL PROGRAMMING I:

BASICS
COMPUTER ARCHITECTURE AND ORGANIZATION
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Today: Machine Programming I: Basics

• History of Intel processors and architectures

• C, assembly, machine code
• Assembly Basics: Registers, operands, move

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Intel x86 Processors, contd.

• Machine Evolution
• 386 1985 0.3M
• Pentium 1993 3.1M
• Pentium/MMX 1997 4.5M
• PentiumPro 1995 6.5M
• Pentium III 1999 8.2M
• Pentium 4 2001 42M
• Core 2 Duo 2006 291M
• Core i7 2008 731M
• Added Features
• Instructions to support multimedia operations
• Parallel operations on 1, 2, and 4-byte data, both integer & FP
• Instructions to enable more efficient conditional operations
• Linux/GCC Evolution
• Two major steps: 1) support 32-bit 386. 2) support 64-bit x86-64
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Intel’s 64-Bit
• Intel Attempted Radical Shift from IA32 to IA64
• Totally different architecture (Itanium)
• Executes IA32 code only as legacy
• Performance disappointing
• AMD Stepped in with Evolutionary Solution
• x86-64 (now called “AMD64”)
• Intel Felt Obligated to Focus on IA64
• Hard to admit mistake or that AMD is better
• 2004: Intel Announces EM64T extension to IA32
• Extended Memory 64-bit Technology
• Almost identical to x86-64!
• All but low-end x86 processors support x86-64
• But, lots of code still runs in 32-bit mode
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Our Coverage
• IA32
• The traditional x86

• x86-64/EM64T
• The emerging standard

• Presentation
• Book presents IA32 in Sections 3.1—3.12
• Covers x86-64 in 3.13

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Today: Machine Programming I: Basics

• History of Intel processors and architectures

• C, assembly, machine code
• Assembly Basics: Registers, operands, move

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Definitions
• Architecture: (also instruction set architecture:
ISA) The parts of a processor design that one needs
to understand to write assembly code.
• Examples: instruction set specification, registers.
• Microarchitecture: Implementation of the
architecture.
• Examples: cache sizes and core frequency.

• Example ISAs (Intel): x86, IA, IPF

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Assembly Programmer’s View

CPU Memory
Addresses
PC Registers Object Code
Data Program Data
Condition OS Data
Instructions
Codes
Stack
• Programmer-Visible State
• PC: Program counter
• Address of next instruction
• Called “EIP” (IA32) or “RIP” (x86-64)
• Register file
• Heavily used program data • Memory
• Condition codes • Byte addressable array
• Store status information about most recent • Code, user data, (some) OS data
arithmetic operation • Includes stack used to support
• Used for conditional branching procedures
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Program to Process
• We write a program in e.g., C.
• A compiler turns that program into an instruction list.
• The CPU interprets the instruction list (which is more a graph of
basic blocks).

void X (int b) {
if(b == 1) {
…
int main() {
int a = 2;
X(a);
}

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Process in Memory What is in memory.

• Program to process.
main; a = 2 Stack
What you wrote
X; b = 2
void X (int b) {
if(b == 1) {
Heap
…
void X (int b) {
int main() {
if(b == 1) {
int a = 2;
…
X(a);
int main() {
}
int a = 2;
X(a);
What must the OS track for
a process? } Code
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A shell forks and execs a calculator

int pid = fork(); int calc_main(){
pid = fork();
if(pid == 0) { if(pid
int q==
= 7;
0) {
close(“.history”); close(“.history”);
do_init();
exec(“/bin/calc”); exec(“/bin/calc”);
ln = get_input();
} else { } exec_in(ln);
else {
wait(pid); wait(pid);
USER
OS
pid = 128
127
open files = “.history” Process Control
last_cpu = 0 Blocks (PCBs)

pid = 128
open files =
last_cpu = 0
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A shell forks and then execs a calculator

main; a = 2 Stack Stack

0xFC0933CA Heap 0x43178050 Heap

int shell_main() { int calc_main() {
int a = 2; int q = 7;
… Code … Code
USER
OS
pid = 128
127
open files = “.history” Process Control
last_cpu = 0 Blocks (PCBs)
pid = 128
open files =
last_cpu = 0
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Anatomy of an address space

mapped segments
Header
DLL’s
Code
Process’s Stack
Initialized data address space

Heap

Initialized data
Executable File
Code

Inaccessible
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Turning C into Object Code

• Code in files p1.c p2.c

• Compile with command: gcc –O1 p1.c p2.c -o p
• Use basic optimizations (-O1)
• Put resulting binary in file p

text C program (p1.c p2.c)

Compiler (gcc -S)

text Asm program (p1.s p2.s)

Assembler (gcc or as)

binary Object program (p1.o p2.o) Static libraries

(.a)
Linker (gcc or ld)

binary Executable program (p) 21

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Compiling Into Assembly

C Code Generated IA32 Assembly

int sum(int x, int y) sum:
{ pushl %ebp
int t = x+y; movl %esp,%ebp
return t; movl 12(%ebp),%eax
} addl 8(%ebp),%eax
popl %ebp
ret

Some compilers use

instruction “leave”
Obtain with command
/usr/local/bin/gcc –O1 -S code.c
Produces file code.s 22
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Assembly Characteristics: Data Types

• “Integer” data of 1, 2, or 4 bytes

• Data values
• Addresses (untyped pointers)

• Floating point data of 4, 8, or 10 bytes

• No aggregate types such as arrays or structures

• Just contiguously allocated bytes in memory

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Assembly Characteristics: Operations

• Perform arithmetic function on register or memory

data

• Transfer data between memory and register

• Load data from memory into register
• Store register data into memory

• Transfer control
• Unconditional jumps to/from procedures
• Conditional branches
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Object Code

Code for sum

• Assembler
• Translates .s into .o
0x401040 <sum>:
• Binary encoding of each instruction
0x55 • Nearly-complete image of executable code
0x89
0xe5 • Missing linkages between code in different
0x8b files
0x45
0x0c
• Linker
0x03 • Resolves references between files
0x45 • Total of 11 bytes • Combines with static run-time libraries
0x08
0x5d
• Each instruction • E.g., code for malloc, printf
1, 2, or 3 bytes
0xc3 • Some libraries are dynamically linked
• Starts at address
0x401040 • Linking occurs when program begins
execution
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Disassembling Object Code

Disassembled
080483c4 <sum>:
80483c4: 55 push %ebp
80483c5: 89 e5 mov %esp,%ebp
80483c7: 8b 45 0c mov 0xc(%ebp),%eax
80483ca: 03 45 08 add 0x8(%ebp),%eax
80483cd: 5d pop %ebp
80483ce: c3 ret

• Disassembler
objdump -d p
• Useful tool for examining object code
• Analyzes bit pattern of series of instructions
• Produces approximate rendition of assembly code
• Can be run on either a.out (complete executable) or .o file
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Alternate Disassembly

Disassembled
Object
0x401040:
0x55 Dump of assembler code for function sum:
0x89 0x080483c4 <sum+0>: push %ebp
0xe5 0x080483c5 <sum+1>: mov %esp,%ebp
0x8b 0x080483c7 <sum+3>: mov 0xc(%ebp),%eax
0x45 0x080483ca <sum+6>: add 0x8(%ebp),%eax
0x0c 0x080483cd <sum+9>: pop %ebp
0x03 0x080483ce <sum+10>: ret
0x45
0x08 • Within gdb Debugger
0x5d
0xc3 gdb p
disassemble sum
• Disassemble procedure
x/11xb sum
• Examine the 11 bytes starting at sum
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What Can be Disassembled?

% objdump -d WINWORD.EXE

WINWORD.EXE: file format pei-i386

No symbols in "WINWORD.EXE".
Disassembly of section .text:

30001000 <.text>:
30001000: 55 push %ebp
30001001: 8b ec mov %esp,%ebp
30001003: 6a ff push $0xffffffff
30001005: 68 90 10 00 30 push $0x30001090
3000100a: 68 91 dc 4c 30 push $0x304cdc91

• Anything that can be interpreted as executable code

• Disassembler examines bytes and reconstructs assembly source
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 University of Texas at Austin

Today: Machine Programming I: Basics

• History of Intel processors and architectures

• C, assembly, machine code
• Assembly Basics: Registers, operands, move

30
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Integer Registers (IA32) Origin

(mostly obsolete)

%eax %ax %ah %al accumulate

%ecx %cx %ch %cl counter

general purpose

%edx %dx %dh %dl data

%ebx %bx %bh %bl base

source
%esi %si index

destination
%edi %di index
stack
%esp %sp
pointer
base
%ebp %bp
pointer

16-bit virtual registers

(backwards compatibility) 31
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Simple Memory Addressing Modes

• Normal (R) Mem[Reg[R]]

• Register R specifies memory address

movl (%ecx),%eax

• Displacement D(R) Mem[Reg[R]+D]

• Register R specifies start of memory region
• Constant displacement D specifies offset

movl 8(%ebp),%edx

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Using Simple Addressing Modes

swap:
pushl %ebp
void swap(int *xp, int *yp) movl %esp,%ebp Set
{ Up
pushl %ebx
int t0 = *xp;
int t1 = *yp;
*xp = t1; movl 8(%ebp), %edx
*yp = t0; movl 12(%ebp), %ecx
} movl (%edx), %ebx
Body
movl (%ecx), %eax
movl %eax, (%edx)
movl %ebx, (%ecx)

popl %ebx
popl %ebp Finish
ret

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Using Simple Addressing Modes

swap:
pushl %ebp
void swap(int *xp, int *yp) movl %esp,%ebp Set
{ Up
pushl %ebx
int t0 = *xp;
int t1 = *yp;
*xp = t1; movl 8(%ebp), %edx
*yp = t0; movl 12(%ebp), %ecx
} movl (%edx), %ebx
Body
movl (%ecx), %eax
movl %eax, (%edx)
movl %ebx, (%ecx)

popl %ebx
popl %ebp Finish
ret

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Understanding Swap

void swap(int *xp, int *yp) •

{ • Stack
int t0 = *xp; • (in memory)
Offset
int t1 = *yp;
*xp = t1; 12 yp
*yp = t0; 8 xp
}
4 Rtn adr
0 Old %ebp %ebp
-4 Old %ebx %esp
Register Value
%edx xp
%ecx yp
%ebx t0 movl 8(%ebp), %edx # edx = xp
%eax t1 movl 12(%ebp), %ecx # ecx = yp
movl (%edx), %ebx # ebx = *xp (t0)
movl (%ecx), %eax # eax = *yp (t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0
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Address
Understanding Swap 123 0x124
456 0x120
0x11c
%eax 0x118
%edx Offset
0x114
%ecx yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx
4 Rtn adr 0x108
%esi
%ebp 0
0x104
%edi -4
0x100
%esp
movl 8(%ebp), %edx # edx = xp
%ebp 0x104 movl 12(%ebp), %ecx # ecx = yp
movl (%edx), %ebx # ebx = *xp (t0)
movl (%ecx), %eax # eax = *yp (t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0

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Address
Understanding Swap 123 0x124
456 0x120
0x11c
%eax 0x118
%edx 0x124 Offset
0x114
%ecx yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx
4 Rtn adr 0x108
%esi
%ebp 0
0x104
%edi -4
0x100
%esp
movl 8(%ebp), %edx # edx = xp
%ebp 0x104 movl 12(%ebp), %ecx # ecx = yp
movl (%edx), %ebx # ebx = *xp (t0)
movl (%ecx), %eax # eax = *yp (t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0

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Address
Understanding Swap 123 0x124
456 0x120
0x11c
%eax 0x118
%edx 0x124 Offset
0x114
%ecx 0x120 yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx
4 Rtn adr 0x108
%esi
%ebp 0
0x104
%edi -4
0x100
%esp
movl 8(%ebp), %edx # edx = xp
%ebp 0x104 movl 12(%ebp), %ecx # ecx = yp
movl (%edx), %ebx # ebx = *xp (t0)
movl (%ecx), %eax # eax = *yp (t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0

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Address
Understanding Swap 123 0x124
456 0x120
0x11c
%eax 0x118
%edx 0x124 Offset
0x114
%ecx 0x120 yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx 123
4 Rtn adr 0x108
%esi
%ebp 0
0x104
%edi -4
0x100
%esp
movl 8(%ebp), %edx # edx = xp
%ebp 0x104 movl 12(%ebp), %ecx # ecx = yp
movl (%edx), %ebx # ebx = *xp (t0)
movl (%ecx), %eax # eax = *yp (t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0

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Address
Understanding Swap 123 0x124
456 0x120
0x11c
%eax 456 0x118
%edx 0x124 Offset
0x114
%ecx 0x120 yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx 123
4 Rtn adr 0x108
%esi
%ebp 0
0x104
%edi -4
0x100
%esp
movl 8(%ebp), %edx # edx = xp
%ebp 0x104 movl 12(%ebp), %ecx # ecx = yp
movl (%edx), %ebx # ebx = *xp (t0)
movl (%ecx), %eax # eax = *yp (t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0

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Address
Understanding Swap 456 0x124
456 0x120
0x11c
%eax 456
456 0x118
%edx 0x124 Offset
0x114
%ecx 0x120 yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx 123
4 Rtn adr 0x108
%esi
%ebp 0
0x104
%edi -4
0x100
%esp
movl 8(%ebp), %edx # edx = xp
%ebp 0x104 movl 12(%ebp), %ecx # ecx = yp
movl (%edx), %ebx # ebx = *xp (t0)
movl (%ecx), %eax # eax = *yp (t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0

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Address
Understanding Swap 456 0x124
123 0x120
0x11c
%eax 456 0x118
%edx 0x124 Offset
0x114
%ecx 0x120 yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx 123
4 Rtn adr 0x108
%esi
%ebp 0
0x104
%edi -4
0x100
%esp
movl 8(%ebp), %edx # edx = xp
%ebp 0x104 movl 12(%ebp), %ecx # ecx = yp
movl (%edx), %ebx # ebx = *xp (t0)
movl (%ecx), %eax # eax = *yp (t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0

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Complete Memory Addressing Modes

• Most General Form

D(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]+ D]
• D: Constant “displacement” 1, 2, or 4 bytes
• Rb: Base register: Any of 8 integer registers
• Ri: Index register: Any, except for %esp
• Unlikely you’d use %ebp, either
• S: Scale: 1, 2, 4, or 8 (why these numbers?)

• Special Cases
(Rb,Ri) Mem[Reg[Rb]+Reg[Ri]]
D(Rb,Ri) Mem[Reg[Rb]+Reg[Ri]+D]
(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]] 45
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x86-64 Integer Registers

%rax %eax %r8 %r8d

%rbx %ebx %r9 %r9d

%rcx %ecx %r10 %r10d

%rdx %edx %r11 %r11d

%rsi %esi %r12 %r12d

%rdi %edi %r13 %r13d

%rsp %esp %r14 %r14d

%rbp %ebp %r15 %r15d

• Extend existing registers. Add 8 new ones.

• Make %ebp/%rbp general purpose 48