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    Control Unit Operation: Roselle Manalang Manuel Vincent Galdo Ron Castro

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    The document discusses control unit operation in computers. It describes how instruction execution involves breaking down each instruction cycle into smaller sub-cycles like fetch, indirect, execute, etc. Each sub-cycle involves one or more micro-operations, which are the simplest atomic operations of the processor, like transferring data between registers or performing arithmetic. The control unit is responsible for coordinating these micro-operations during instruction execution. It can be implemented through either hardwired logic or a microprogrammed approach using a microcode control memory.

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    Control Unit Operation: Roselle Manalang Manuel Vincent Galdo Ron Castro

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    Vincent Galdo
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    The document discusses control unit operation in computers. It describes how instruction execution involves breaking down each instruction cycle into smaller sub-cycles like fetch, indirect, execute, etc. Each sub-cycle involves one or more micro-operations, which are the simplest atomic operations of the processor, like transferring data between registers or performing arithmetic. The control unit is responsible for coordinating these micro-operations during instruction execution. It can be implemented through either hardwired logic or a microprogrammed approach using a microcode control memory.

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    202-compArchAndOrg-BSIT2-1

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    The document discusses control unit operation in computers. It describes how instruction execution involves breaking down each instruction cycle into smaller sub-cycles like fetch, indirect, execute, etc. Each sub-cycle involves one or more micro-operations, which are the simplest atomic operations of the processor, like transferring data between registers or performing arithmetic. The control unit is responsible for coordinating these micro-operations during instruction execution. It can be implemented through either hardwired logic or a microprogrammed approach using a microcode control memory.

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    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    40 views10 pages

    Control Unit Operation: Roselle Manalang Manuel Vincent Galdo Ron Castro

    Uploaded by

    Vincent Galdo
    The document discusses control unit operation in computers. It describes how instruction execution involves breaking down each instruction cycle into smaller sub-cycles like fetch, indirect, execute, etc. Each sub-cycle involves one or more micro-operations, which are the simplest atomic operations of the processor, like transferring data between registers or performing arithmetic. The control unit is responsible for coordinating these micro-operations during instruction execution. It can be implemented through either hardwired logic or a microprogrammed approach using a microcode control memory.

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    CHAPTER 15

    CONTROL UNIT
    OPERATION 

    Roselle Manalang Manuel


    Vincent Galdo
    Ron Castro
    15.1 MICRO-OPERATIONS
     In computer central processing units, micro-operations (also known as micro-ops) are the functional or atomic, operations of a processor.
    These are low level instructions used in some designs to implement complex machine instructions. They generally perform operations on data
    stored in one or more registers. They transfer data between registers or between external buses of the CPU, also performs arithmetic and
    logical operations on registers.
     In executing a program, operation of a computer consists of a sequence of instruction cycles, with one machine instruction per cycle. Each
    instruction cycle is made up of a number of smaller units – Fetch, Indirect, Execute and Interrupt cycles. Each of these cycles involves series
    of steps, each of which involves the processor registers. These steps are referred as micro-operations. the prefix micro refers to the fact that
    each of the step is very simple and accomplishes very little. Figure below depicts the concept being discussed here.

    Summary: Execution of a program consists of sequential


    execution of instructions. Each instruction is executed during an
    instruction cycle made up of shorter sub-cycles(example – fetch,
    indirect, execute, interrupt). The performance of each sub-cycle
    involves one or more shorter operations, that is, micro-
    operations.
    15.2 CONTROL OF THE PROCESSOR
     As a result of our analysis in the proceeding sections, we have decomposed the behavior or functioning of the processor into elementary operations, called micro operations.
    By reducing the operation of the processor to its most fundamental level, we are able to define exactly what is that the control unit must cause to happen. Thus, we can define
    the functional requirements for the control unit: those functions that the control unit must perform. A definition of those functional requirements is the basis for the design and
    implementation of the control unit.

     With the information at hand, the following three step process leads to a characterization of the control unit:

     1.       Define the basic elements of the processor

     2.       Describe the micro operations that the processor perform

     3.       Determine the functions that the control unit must perform to cause the micro operations to be performed.

    The basic functions of the processor


    are the following:
    - ALU
    - registers
    - Internal data paths
    - External data paths
    - Control unit
    15.3 HARDWIRED IMPLEMENTATION 
    Design of Control Unit
    The Control Unit is classified into two major categories:

    • Hardwired Control
    • Microprogrammed Control
    Hardwired Control

    The Hardwired Control organization involves the control logic to be implemented with gates, flip-flops, decoders, and
    other digital circuits.

    The following image shows the block diagram of a Hardwired Control organization.
    • A Hard-wired Control consists of two decoders, a sequence counter, and a number of logic
    gates.
    • An instruction fetched from the memory unit is placed in the instruction register (IR).
    • The component of an instruction register includes; I bit, the operation code, and bits 0 through
    11.
    • The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.
    • The outputs of the decoder are designated by the symbols D0 through D7.
    • The operation code at bit 15 is transferred to a flip-flop designated by the symbol I.
    • The operation codes from Bits 0 through 11 are applied to the control logic gates.
    • The Sequence counter (SC) can count in binary from 0 through 15.
    MICRO-PROGRAMMED CONTROL
     The Microprogrammed Control organization is implemented by using the programming approach.

     In Microprogrammed Control, the micro-operations are performed by executing a program consisting of micro-instructions.

     The following image shows the block diagram of a Microprogrammed Control organization.

    • The Control memory address register specifies the address of the micro-instruction.
    • The Control memory is assumed to be a ROM, within which all control information is
    permanently stored.
    • The control register holds the microinstruction fetched from the memory.
    • The micro-instruction contains a control word that specifies one or more micro-operations for the
    data processor.
    • While the micro-operations are being executed, the next address is computed in the next address
    generator circuit and then transferred into the control address register to read the next
    microinstruction.
    • The next address generator is often referred to as a micro-program sequencer, as it determines the
    address sequence that is read from control memory.
    15.4 RECOMMENDED READING
    War and Peace
    by Leo Tolstoy
    A legendary masterpiece, this book is synonymous with
    difficult reading, so why not challenge yourshelf.
    15.5 KEY TERMS, REVIEW QUESTIONS, AND PROBLEMS

    main memorymany multicoremultiplexoropcod


    integrated core (MIC)MIPS SPECspeed metricstored-
    eoriginal
    ratememory address program conceptupward
    equipmentmanufacturer
    register(MAR)memory compatiblevon Neumann
    (OEM)program counter
    buffer machinewaferword
    (PC)rate metricratio
    register(MBR)microproces
    sor

    Review Questions

    2.1What is a stored program computer?


    2.2What are the four main components of any general-purpose computer?
    2.3At the integrated circuit level, what are the three principal constituents of a computersystem?
    2.4Explain Moore’s law.
    2.5List and explain the key characteristics of a computer family.
    2.6What is the key distinguishing feature of a microprocessor?
    Problems

    2.1You are to write an IAS program to compute the results of the following equation.
    Y=aNX=1X
    Assume that the result of the computation does not arithmetic overflow and thatX,Y,andNare positive integers withN1.Note:
    The IAS did not have assembly languageonly machine language

    a.Use the equation Sum(Y)=N(N+1)/2 when writing the IAS program.


    b.Do it the “hard way,” without using the equation from part (a).
    2.2a.On the IAS, what would the machine code instruction look like to load thecontents of memory address 2 to the
    accumulator?
    b.How many trips to memory does the CPU need to make to complete this instruc-tion during the instruction cycle?
    2.3On the IAS, describe in English the process that the CPU must undertake to read avalue from memory and to write a value
    to memory in terms of what is put into theMAR, MBR, address bus, data bus, and control bus.

    2.4Given the memory contents of the IAS computer shown below


    Address            Contents
    08A              010FA210FB
    08B             010FA0F08D
    08C             020FA210FB 
    show the assembly language code for the program, starting at address 08A.
    Explainwhat this program does.
    3.8KEY TERMS, REVIEW QUESTIONS, AND PROBLEMS

    Key Terms

    address bus distributed arbitration memory buffer register (MBR)


    address lines error control function multilane distribution
    Arbitration execute cycle Packets
    asynchronous timing fetch cycle PCI Express (PCIe)
    balanced transmission Flit peripheral component
    Bus flow control function interconnect (PCI)
    bus width instruction cycle Phit
    centralized arbitration Interrupt QuickPath Interconnect
    control lines interrupt handler          (QPI)
    data bus interrupt service routine (ISR) root complex
    data lines Lane synchronous timing
    differential signaling memory address register system bus
    disabled interrupt         (MAR)
    THANK YOU 

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