Getting To Know PERC: - Calibre PERC Addresses A Number of Electrical Design Issues

Getting to know PERC
• Calibre PERC addresses a number of electrical design issues:

– Electrical Rules Checks (ERC)
– Electrostatic Discharge (ESD) protection analysis
– Multiple supply domain checks
– ESD layout resistance and current density analysis
– Electrical Overstress (EOS) checks
• PERC uses a library of TCL functions in conjunction with the Calibre TVF en
vironment.
• PERC rule development involves writing Tcl procedures that invoke these f
unctions.
How is Calibre PERC Used?
• Calibre PERC can be used to analyze:
– The source netlist (the original circuit design)
– The extracted layout netlist
– The Chip layout (P2P and CD)
• Use Calibre PERC to analyze the source netlist:
– Before chip layout has started to verify that your circuit design compliance wit
h all AERC, ESD, and multi-domain rules.
• Use Calibre PERC to analyze the layout netlist:
– To verify compliance with all AERC, ESD, and multi-domain rules
– To analyze layout-specific ESD and multi-domain protection
• Use Calibre PERC to analyze the layout:
– To verify ESD path resistance
– To determine shape-specific current densities
PERC Job Flow-ERC and ESD Applications
Extractd
Source
<OR> Layou Layout
Netlist
Netlist Data
PERC Calibre
Rule File
PERC
SVDB
PERC Calibre
Report RVE
PERC Job Flow-LDL(P2P and CD) Applications
Layout
Data
PERC
Report
Calibre PERC
(Extract layout data) Pin Pair
PERC
List
Rule File
Calibre PERC
PERC (Compute results) DFM
P2P/CD Database
Report
Calibre
RVE
RDB
PERC Invocation-Command Line
• Perform hierarchical ESD/ERC analysis:
calibre -perc -hier rules
• Perform hierarchical CD/P2P analysis:
calibre -perc -ldl -hier rules
PERC Rule File Components
• There are two major sections in a PERC rule file:
– PERC job control statements (SVRF code)
– PERC analysis statements (TCL code)
Anatomy of a PERC Rule File
(Analyze Source Netlist)
SOURCE PATH “src.net” This statement loads
SOURCE PRIMARY “TOP” the library of PERC
SOURCE SYSTEM SPICE Tcl functions.
Job control statements –
covered in this module MASK SVDB DIRECTORY “svdb” QUERY
PERC NETLIST SOURCE
This module covers the
PERC REPORT “perc.rep”
statements used in the
PERC LOAD aerc INIT aerc_init SELECT rule_1
PERC initialization
procedure.
TVF FUNCTION aerc [/*
package require CalibreLVS_PERC
proc aerc_init {} { This module covers the
perc::define_net_type “Power” {vdd?} statements used in the
perc::define_net_type “Ground” {gnd?} PERC rule procedure.
PERC analysis statements – }
covered in subsequent modules
proc rule_1 {} {
perc::check_device -type {MN MP} -pinNetType {g {Power || Ground}}\
-comment “Gates tied to supply”
}
*/]
Analyze Existing Layout Netlist
LAYOUT PATH “lay.sp”

LAYOUT PRIMARY “TOP”
LAYOUT SYSTEM SPICE
MASK SVDB DIRECTORY “svdb” QUERY
PERC NETLIST LAYOUT

INCLUDE “perc.rules”
Extract Layout Netlist and Run PERC
LAYOUT PATH “lab2.gds”

LAYOUT PRIMARY “TOP”
LAYOUT SYSTEM GDS
MASK SVDB DIRECTORY “svdb” QUERY
PERC NETLIST LAYOUT

INCLUDE “perc.rules”
Calibre PERC: Its All About Nets and Paths
• The PATHCHK operation provides basic ERC analysis:
– Finds paths through transistors and resistor (other devices could be added, if n
eeded)
– Answers basic questions regarding path connections.
– Example: “Which nets have a path to ground”
• Calibre PERC AERC extends ERC analysis by allowing the user to specify net
and path conditions:
– Only considers those nets that meet user-specified conditions.
– Only constructs paths that meet user-specified conditions.
– Example: “Which NMOS gate pins have a path to ground that does not have a
series resistor of at least 50 ohms?”
What is a Net?
• A net:
– Is a connection between two device pins, or a connection from an I/O port to
a device pin.
• Every net is uniquely identified by:
– A name (VDD, Clock_A, reset, …), or a number.
• An example:
Net "VDD"
M0 VDD
Net "1"
.SUBCKT Top INA VDD VSS Net "INA" Net "3"

M0 3 1 VDD VDD p R1
M1 3 1 VSS VSS n INA 3
1
R1 INA 1 100
Net "VSS"
.ENDS
M1 VSS
What is a Net Type?
• A net type is a user-defined label applied to related nets.
• The nets are related in any way that is meaningful to designer (ie., the net
s do not have to be electrically related).
• By default, net type labels apply to top-level nets only, but they can apply t
o cells and instances by using appropriate options.
• Net type labels are applied across the hierarchy to nets connected through
cell ports.
• Net type labeling stops at device pins.
Supply Supply VDD, VDD:1, VSS, and

CELL
VDD:1 2 VSS:1
VSS:1 all have the
VSS VSS
Supply net type
Legend:
net type
What is a Path?
• A path:
– Is a connection that can be traced between two points in the circuit .
– Starts at a device pin or circuit port.
– By default, stops at the first device pin it encounters.
– Can “pass through” device pins based on path specifications.
• A path can contain multiple nets, based on path specifications.
• Every net is its own path. Nets and paths can traverse hierarchy through p
orts.
• If resistor pins participate in paths, then these paths exist:
M0 VDD
Path 1
Path2
R1
Path numbers shown for
INA 3 Path3 illustration purposes only –
1
paths are not numbered in
Path4
the database.
M1 VSS
What is Path Type?
• A path type is a user-defined label generated from a net type.
• Initially, a path type label applies only to the nets having a net type label.
• Path type labels are propagated across device pins to other nets based up
on the path specification.
• Path type propagation stops at device pins that are not in the path specific
ation.
Supply Supply
CELL
2
VDD, VDD:1, VSS, and
VDD:1 VSS:1
VSS VSS VSS:1 all have the Supply
Supply net type. They also get
Supply Supply
the Supply path type
If R devices are part of the path Legend:

specification, the Supply path
net type
type gets passed through them
to other nets path type

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Getting to know PERC

• Calibre PERC addresses a number of electrical design issues:

LAYOUT PATH “lay.sp”

MASK SVDB DIRECTORY “svdb” QUERY

PERC NETLIST LAYOUT

PERC LOAD aerc INIT aerc_init SELECT rule_1

LAYOUT PATH “lab2.gds”

MASK SVDB DIRECTORY “svdb” QUERY

PERC NETLIST LAYOUT

PERC LOAD aerc INIT aerc_init SELECT rule_1

.SUBCKT Top INA VDD VSS Net "INA" Net "3"

Supply Supply VDD, VDD:1, VSS, and

If R devices are part of the path Legend:

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