Logic and Computer Design Fundamentals

Chapter 9 – Memory Basics

Charles Kime & Thomas Kaminski

© 2004 Pearson Education, Inc.
Terms of Use
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Overview

 Memory definitions
 Random Access Memory (RAM)
 Static RAM (SRAM) integrated circuits
• Cells and slices
• Cell arrays and coincident selection
 Arrays of SRAM integrated circuits
 Dynamic RAM (DRAM) integrated circuits
 DRAM Types
• Synchronous (SDRAM)
• Double-Data Rate (DDR SRAM)
• RAMBUS DRAM (RDRAM)
 Arrays of DRAM integrated circuits

Chapter 9 2
Memory Definitions

 Memory ─ A collection of storage cells together with

the necessary circuits to transfer information to and
from them.
 Memory Organization ─ the basic architectural
structure of a memory in terms of how data is accessed.
 Random Access Memory (RAM) ─ a memory
organized such that data can be transferred to or from
any cell (or collection of cells) in a time that is not
dependent upon the particular cell selected.
 Memory Address ─ A vector of bits that identifies a
particular memory element (or collection of elements).

Chapter 9 3
Memory Definitions (Continued)
 Typical data elements are:
• bit ─ a single binary digit
• byte ─ a collection of eight bits accessed together
• word ─ a collection of binary bits whose size is a
typical unit of access for the memory. It is typically
a power of two multiple of bytes (e.g., 1 byte, 2 bytes,
4 bytes, 8 bytes, etc.)
 Memory Data ─ a bit or a collection of bits to
be stored into or accessed from memory cells.
 Memory Operations ─ operations on memory
data supported by the memory unit. Typically,
read and write operations over some data
element (bit, byte, word, etc.).
Chapter 9 4
Memory Organization

 Organized as an indexed array of words. Value of the

index for each word is the memory address.
 Often organized to fit the needs of a particular
computer architecture. Some historically significant
computer architectures and their associated memory
organization:
• Digital Equipment Corporation PDP-8 – used a 12-bit address
to address 4096 12-bit words.
• IBM 360 – used a 24-bit address to address 16,777,216 8-bit
bytes, or 4,194,304 32-bit words.
• Intel 8080 – (8-bit predecessor to the 8086 and the current
Intel processors) used a 16-bit address to address 65,536 8-bit
bytes.

Chapter 9 5
Memory Block Diagram

 A basic memory system is n Data Input Lines

shown here: n

 k address lines are Memory

k Address Lines Unit
decoded to address 2k k
2k Words
words of memory. 1 n Bits per Word
 Each word is n bits. Read
1
 Read and Write are singleWrite
control lines defining the n
simplest of memory
n Data Output Lines
operations.

Chapter 9 6
 Memory Organization Example

 Example memory
contents: Memory Address Memory
• A memory with 3 Binary Decimal Content
000 0 10001111
address bits & 8
001 1 11111111
data bits has:
010 2 10110001
• k = 3 and n = 8 so 011 3 00000000
23 = 8 addresses 100 4 10111001
labeled 0 to 7. 101 5 10000110
• 23 = 8 words of 8-bit 11 0 6 00110011
data 111 7 11001100

Chapter 9 7
Basic Memory Operations

 Memory operations require the following:

• Data ─ data written to, or read from, memory as
required by the operation.
• Address ─ specifies the memory location to operate
on. The address lines carry this information into
the memory. Typically: n bits specify locations of 2n
words.
• An operation ─ Information sent to the memory and
interpreted as control information which specifies
the type of operation to be performed. Typical
operations are READ and WRITE. Others are
READ followed by WRITE and a variety of
operations associated with delivering blocks of data.
Operation signals may also specify timing info.
Chapter 9 8
Basic Memory Operations (continued)
 Read Memory ─ an operation that reads a data value stored
in memory:
• Place a valid address on the address lines.
• Wait for the read data to become stable.
 Write Memory ─ an operation that writes a data value to
memory:
• Place a valid address on the address lines and valid data on the data
lines.
• Toggle the memory write control line
 Sometimes the read or write enable line is defined as a clock
with precise timing information (e.g. Read Clock, Write
Strobe).
• Otherwise, it is just an interface signal.
• Sometimes memory must acknowledge that it has completed the
operation.

Chapter 9 9
Memory Operation Timing
 Most basic memories are asynchronous
• Storage in latches or storage of electrical charge
• No clock
 Controlled by control inputs and address
 Timing of signal changes and data observation is critical to the
operation
 Read timing:
20 ns
Clock T1 T2 T3 T4 T1

Address Address valid

Memory
enable
Read/
Write
Data Data valid
output
65 ns
Read cycle
Chapter 9 10
Memory Operation Timing
 Write timing:
20 ns

Clock T1 T2 T3 T4 T1

Address Address valid

Memory
enable
Read/
Write
Data
input Data valid

75 ns
 Critical times measured with respect
Writeto edges
cycle of write pulse (1-0-1):
• Address must be established at least a specified time before 1-0 and held for at
least a specified time after 0-1 to avoid disturbing stored contents of other
addresses
• Data must be established at least a specified time before 0-1 and held for at least
a specified time after 0-1 to write correctly

Chapter 9 11
RAM Integrated Circuits

 Types of random access memory

• Static – information stored in latches
• Dynamic – information stored as electrical charges
on capacitors
 Charge “leaks” off
 Periodic refresh of charge required
 Dependence on Power Supply
• Volatile – loses stored information when power
turned off
• Non-volatile – retains information when power
turned off

Chapter 9 12
 Static RAM  Cell
 Array of storage cells used to implement static RAM
 Storage Cell Select

• SR Latch
• Select input for
control B
S Q
C

• Dual Rail Data

Inputs B and B C
R Q
• Dual Rail Data B
RAM cell
Outputs C and C

Chapter 9 13
 Static RAM  Bit Slice
 Represents all circuitry that is required for 2n Select
Word
1-bit words select
0
B
XC
• Multiple RAM cells S Q

C Word
B R Q X select
• Control Lines: RAM cell 0
RAM cell
Word
 Word select i select
1
– one for each word Word
select
Select RAM cell

2n  1
 Re ad / Write X Word
S Q select
 Bit Select 2n  1
RAM cell
R Q X

• Data Lines: RAM cell

Read/Write
logic
 Data in Data in
S Q Data out
 Data out Data in Read/ Bit
Write select
R Q
(b) Symbol

Write logic Data out

Read logic
Read/ Bit
Write select
(a) Logic diagram Chapter 9 14
 2n-Word  1-Bit RAM IC
4-to-16 Word select
 To build a RAM IC Decoder 0
A3 A3 23 1
from a RAM slice, A2 A2 22
2
3
RAM cell

we need: A1 A1 21
4
5

• Decoder  decodes A0 A0 20
6
7
RAM cell

16 x 1
the n address lines to RAM
8
9

2n word select lines input

Data Data
output
10
11
12
• A 3-state buffer  13
14

• on the data output Read/

Write
15

permits RAM ICs to enable

Memory RAM cell

be combined into a (a) Symbol Read/Write

logic

RAM with c  2n words Data input Data in

Data out Data
output
Read/ Bit
Write select

Read/Write
Chip select
(b) Block diagram
Chapter 9 15
Cell Arrays and Coincident Selection

 Memory arrays can be very large =>

• Large decoders
• Large fanouts for the bit lines
• The decoder size and fanouts can be reduced by
approximately n by using a coincident selection in
a 2-dimensional array
• Uses two decoders, one for words and one for bits
• Word select becomes Row select
• Bit select becomes Column select
 See next slide for example
• A3 and A2 used for Row select
• A1 and A0 for Column select

Chapter 9 16
Cell Arrays and Coincident Selection
(continued)
Row decoder
2-to-4
Decoder 0
A3 21
RAM cell RAM cell RAM cell RAM cell
0 1 2 3
A2 20
1

Row RAM cell RAM cell RAM cell RAM cell

select 4 5 6 7
2

RAM cell RAM cell RAM cell RAM cell

8 9 10 11

RAM cell RAM cell RAM cell RAM cell

12 13 14 15

Read/Write Read/Write Read/Write Read/Write

logic logic logic logic

Data in Data in Data in Data in

Data out Data out Data out Data out
Read/ Bit Read/ Bit Read/ Bit Read/ Bit
Write select Write select Write select Write select
Data input
Read/Write

X X X X
Column select Data
0 1 2 3 output
Column 2-to-4 Decoder
decoder with enable
21 20 Enable

A1 A0
Chip select Chapter 9 17
RAM ICs with > 1 Bit/Word

 Word length can be quite high.

 To better balance the number of words
and word length, use ICs with > 1
bit/word
 See Figure 9-8 for example
• 2 Data input bits
• 2 Data output bits
• Row select selects 4 rows
• Column select selects 2 pairs of columns

Chapter 9 18
Making Larger Memories
Data In
 Using the CS lines, we De c o de r
A1 D-In
can make larger A0
R/W
memories from smaller D3 CS D-Out

ones by tying all A1 D-In

address, data, and R/W A0
R/W
lines in parallel, and D2 CS D-Out
using the decoded
A1 D-In
higher order address A0
R/W
bits to control CS. D1 CS D-Out

 Using the 4-Word by 1- A1 D-In

Bit memory from A0
R/W
before, we construct a A3 S 1 D0 CS D-Out

16-Word by A2 S0
Data Out
1-Bit memory.   A1
A0
R/W
Chapter 9 19
Making Wider Memories

 To construct wider Data In 3210

memories from narrow A1 D-In

A0
ones, we tie the address R/W
CS D-Out
and control lines in
parallel and keep the data A1 D-In
lines separate. A0
R/W
 For example, to make a 4- CS D-Out

word by 4-bit memory A1 D-In

from 4, 4-word by 1-bit A0
R/W
memories   CS D-Out

 Note: Both 16x1 and 4x4 A1 A1 D-In

memories take 4-chips A0 A0
R/W
and hold 16 bits of data. R/W CS D-Out
CS

Data Out 3210

Chapter 9 20
Dynamic RAM (DRAM)

 Basic Principle: Storage of information

on capacitors.
 Charge and discharge of capacitor to
change stored value
 Use of transistor as “switch” to:
• Store charge
• Charge or discharge
 See next slide for circuit, hydraulic
analogy, and logical model.

Chapter 9 21
 Dynamic RAM (continued)

Select

To Pump
Stored 1 Stored 0
T
B
C
DRAM cell
(a) (b) (c)

Write 1 Write 0
Select

(d) (e)
B D Q C
Read 1 Read 0
C DRAM cell
model

(h) (f) (g)

Chapter 9 22
 Dynamic RAM - Bit Slice
Word
 C is driven by 3-state
Select
select
0

drivers B
D Q
C

 Sense amplifier is used C DRAM cell Word

model select
0

to change the small Word

DRAM cell

select
voltage change on C Word Select
1
DRAM cell
into H or L select
2n 2 1

Word
 In the electronics, B, C, D Q
select
2n 2 1
C DRAM cell
and the sense amplifier model DRAM cell

output are connected to Read/Write

logic

make destructive read Sense

amplifier
Data in
Data out

into non-destructive Data in Read/ Bit

Write select

read (b) Symbol

Write logic
Read logic Data out
Read/ Bit
Write select
(a) Logic diagram Chapter 9 23
Dynamic RAM - Block Diagram

 Block Diagram – See Figure 9-14 in text

 Refresh Controller and Refresh Counter
 Read and Write Operations
• Application of row address
• Application of column address
• Why is the address split?
• Why is the row address applied first?

Chapter 9 24
 Dynamic RAM Read Timing
20 ns

Clock T1 T2 T3 T4 T1

Address Row Column

Address Address

RAS

CAS

Output
enable
Read/
Write

Data Hi-Z
Data valid
output
65 ns
Read cycle
Chapter 9 25
 DRAM Types
 Types to be discussed
• Synchronous DRAM (SDRAM)
• Double Data Rate SDRAM (DDR SDRAM)
• RAMBUS® DRAM (RDRAM)
 Justification for effectiveness of these types
• DRAM often used as a part of a memory hierarchy (See details in
chapter 14)
• Reads from DRAM bring data into lower levels of the hierarchy
• Transfers from DRAM involve multiple consecutively addressed
words
• Many words are internally read within the DRAM ICs using a
single row address and captured within the memory
• This read involves a fairly long delay

Chapter 9 26
DRAM Types (continued)

 Justification for effectiveness of these types (continued)

• These words are then transferred out over the memory data
bus using a series of clocked transfers
• These transfers have a low delay, so several can be done in a
short time
• The column address is captured and used by a synchronous
counter within the DRAM to provide consecutive column
addresses for the transfers
 burst read – the resulting multiple word read from
consecutive addresses

Chapter 9 27
Synchronous DRAM
 Transfers to and from the DRAM are synchronize with a clock
 Synchronous registers appear on:
• Address input
• Data input
• Data output
 Column address counter
• for addressing internal data to be transferred on each clock cycle
• beginning with the column address counts up to column address + burst
size – 1
 Example: Memory data path width: 1 word = 4 bytes
Burst size: 8 words = 32 bytes
Memory clock frequency: 5 ns
Latency time (from application of row address until first word
available): 4 clock cycles
Read cycle time: (4 + 8) x 5 ns = 60 ns
Memory Bandwidth: 32/(60 x 10 -9) = 533 Mbytes/sec

Chapter 9 28
Double Data Rate Synchronous DRAM

 Transfers data on both edges of the clock

 Provides a transfer rate of 2 data words per
clock cycle
 Example: Same as for synchronous DRAM
• Read cycle time = 60 ns
• Memory Bandwidth: (2 x 32)/(60 x 10-9) = 1.066
Mbytes/sec

Chapter 9 29
 RAMBUS DRAM (RDRAM)

 Uses a packet-based bus for interaction between the RDRAM ICs and the
memory bus to the processor
 The bus consists of:
• A 3-bit row address bus
• A 5-bit column address bus
• A 16 or 18-bit (for error correction) data bus
 The bus is synchronous and transfers on both edges of the clock
 Packets are 4-clock cycles long giving 8 transfers per packet representing:
• A 12-bit row address packet
• A 20-bit column address packet
• A 128 or 144-bit data packet
 Multiple memory banks are used to permit concurrent memory accesses
with different row addresses
 The electronic design is sophisticated permitting very fast clock speeds

Chapter 9 30
Arrays of DRAM Integrated Circuits

 Similar to arrays of SRAM ICs, but there are

differences typically handled by an IC called a
DRAM controller:
• Separation of the address into row address and
column address and timing their application
• Providing RAS and CAS and timing their
application
• Performing refresh operations at required intervals
• Providing status signals to the rest of the system
(e.g., indicating whether or not the memory is active
or is busy performing refresh)

Chapter 9 31
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Chapter 9 32