INTRODUCTION

TO
PIC
MICROCONTROLLERS
The term PIC stands for
“Peripheral Interface Controller”

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UNIT I INTRODUCTION TO PIC MICROCONTROLLER
Introduction to PIC Microcontroller–PIC 16C6x and PIC16C7x
Architecture–PIC16cxx–- Pipelining - Program Memory
considerations – Register File Structure - Instruction Set - Addressing
modes – Simple Operations.

UNIT II INTERRUPTS AND TIMER

PIC micro controller Interrupts- External Interrupts-Interrupt
Programming–Loop time subroutine - Timers-Timer Programming–
Front panel I/O-Soft Keys– State machines and key switches– Display
of Constant and Variable strings.

UNIT III PERIPHERALS AND INTERFACING

I2C Bus for Peripherals Chip Access– Bus operation-Bus subroutines–
Serial EEPROM—Analog to Digital Converter–UART-Baud rate
selection–Data handling circuit–Initialization - LCD and keyboard
Interfacing -ADC,
R.Hariharan DAC,
AP / EEE and Sensor Interfacing.
-SECE
UNIT IV INTRODUCTION TO ARM PROCESSOR
ARM Architecture –ARM programmer’s model –ARM Development
tools- Memory Hierarchy –ARM Assembly Language Programming–
Simple Examples–Architectural Support for Operating systems.

UNIT V ARM ORGANIZATION

3-Stage Pipeline ARM Organization– 5-Stage Pipeline ARM
Organization–ARM Instruction Execution- ARM Implementation–
ARM Instruction Set– ARM coprocessor interface– Architectural
support for High Level Languages – Embedded ARM Applications.

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CISC - Complex Instruction Set Compute
Vs
RISC - Reduced Instruction Set Computer
 In early years memory was
slow,
RISC -expensive and the
relatively limited
programming was done in
number of instructions.
assembly language
smaller number of
types of computer
Instructions could by retrieved up
10 times faster
instructions
to sofrom
that ait
local ROM
can operate than from main
at a higher
memory, programmers tried to put
speed.
as many instructions as possible
in a microcode. 
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ARM - Acorn RISC Machine,
achine Advanced RISC Machine

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Types of ARM
Processors

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R.Hariharan AP / EEE -SECE
R.Hariharan AP / EEE -SECE
Raspberry Pi 2 Model B and its
ARMv7-based
ARMv7 BCM2709 processor

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 Who is he…….?

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
None other than Steve Sanghi, the chairman,
president and CEO of Microchip Technology Inc.
Moved from India to U.S. to pursue a Master’s degree at
the University of Massachusetts
In 1993, Sanghi became president and CEO of Microchip.

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Some of the low-end device numbers are
12C5XX
16C5X
16C505

Mid range PIC architectures are built by upgrading

low-end architectures with more number of
peripherals,
peripherals more number of registers and more
data/program memory.
memory
Some of the mid-range devices are
16C6X
16C7X
16F87X
Program memory type is indicated by an alphabet.
C = EPROM F = Flash RC = Mask ROM
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 Name these… ??

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 6x/7x family of Micro controllers:
PIC 16C62A and 16C74A
are found with a suffix A.

A indicates the Brown-Out Reset.

Reset

Brown-Out Reset which causes a reset of the

PIC when the Power Supply voltage drops below 4.0 V

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Salient features
 Speed : PIC executes most of its instructions in 0.2 s
or five instructions per microsecond.
 Instruction set Simplicity : just 35 instructions.
 Integration of operational features:
Power-on-reset and brown-out protection ensure
that the chip operates only when the supply voltage
is within specifications.
 Watch dog timer: resets the PIC if the chip
malfunctions or deviates from its normal operation
at any time.
 Powerful output pin control:
single instruction can select and drive a single output
pin high or low in its 0.2 s instruction execution time.
The PINAPcan
R.Hariharan -SECE a load of up to 25A.
/ EEEdrive
 I/O port expansion:
With the help of built in Serial Peripheral Interface
(SPI) the number of I/O ports can be expanded.
EPROM/DIP/ROM options are provided.

 Interrupt control:
Up to 12 independent interrupt sources can control
when the CPU will deal with each sources.

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 Programmable timer options:
Three timers can characterize inputs, control outputs and
provide internal timing for the program execution.
execution
There are Three Timers : Namely Timer 0,
0 Timer1,
Timer1
Timer 2
Timer0:
Timer0 8-bit timer/counter with 8-bit prescaler
Timer1:
Timer1 16-bit timer/counter with prescaler can be
incremented during sleep via external crystal/clock
Timer2:
Timer2 8-bit timer/counter with 8-bit period
register, pre- scaler and post- scaler

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Capture/Compare/PWM (CCP) module(s)
Capture is 16-bit, max resolution is 12.5 ns, Compare is
16-bit, max resolution is 200ns, PWM max resolution is
10-bit
Synchronous Serial Port (SSP) with SPITM and I2C
Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
Parallel Slave Port (PSP) 8-bits wide, with external RD,
WR and CS controls
Brown-out detection circuitry for Brown-out Reset (BOR)
PIC16CXX microcontroller family has enhanced core
features, eight-level deep stack, and multiple internal and
external interrupt sources.
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R.Hariharan AP / EEE -SECE
To Which DOT you are attracted more

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 PORTA is a bi-directional I/O port.
RA0 can also be analog input0.
RA1 can also be analog input1.
RA2 can also be analog input2.
Master clear (reset) input or
programming voltage input. This
RA3 can also be analog input3 or
pin
RC2 isCapture1
an active input
low reset
/ to the device.
Compare1
analog reference voltage.
output
RA4 / PWM1
can also be output.
the clock input to the
RC3 - synchronous serial clock
Timer0.
input/output
RA5 can also SPIanalog
be and I2C.
input4
• PORTC is a bi-directional I/Oorport.
the
slave
• RC0select for the
can also be the Timer1
synchronous serial
oscillator output orport.
Timer1 clock
input.
•RC1 can also be the Timer1
oscillator input.
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• PORTB is a bi-directional I/O port.
• RB0 can also be the external interrupt
pin
• RB4 Interrupt on change pin.
• RB5 Interrupt on change pin.
•RC4
RB6 Interrupt
SPI Dataon Inchange pin / Serial
(SPI mode)
mode
programming clock.
data I/O (I2C mode).
mode
• RB7 Interrupt
RC5 can alsoonbe
change pinData
the SPI / Serial
Out
programming
RC6 can alsodata.
be the USART
Asynchronous Transmit or
Synchronous Clock.
RC7 can also be the USART
Asynchronous Transmit or
Synchronous Data.
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R.Hariharan AP / EEE -SECE
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R.Hariharan AP / EEE -SECE
ARCHITECTURE
CENTRAL PROCESSOR UNIT (CPU):

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 Functio
n
process are predetermi
. ne d ma
Their b nufactu
i t s are c ring
module o n
s, A/D nected to some
convert
module
, etc. er, seria on-chip
Any ch l co m m
ange of unicatio
the ope th ei r n
ration. c on tents wi
ll direct
ly affec
t
used for
storing
tteemporary
data and
result
lts
created

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R.Hariharan AP / EEE -SECE
STACK:
part of RAM.
Stack consists of eight 13-bit registers.
registers
 Before the microcontroller executes a subroutine or an
interrupt occurs,
occurs the address of the instruction to be
executed next is pushed onto the stack.
stack

after the stack has been pushed eight times, the ninth push
overwrites the value that was stored with the first push. 
 The PIC16CXX can directly or indirectly address its register
files or data memory.
 The PIC16CXX has an orthogonal instruction set that makes
it possible to carry out any operation on any register using any
addressing mode.
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CPU REGISTERS
The CPU registers are
Working Register (W)
Status – Register
FSR – File Select Register
INDF
PCLATH
Program Counter
PCL
Eight Level Stack

8
All SFR in PIC are ______ bits size
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Working Register:(W)
Temporary holding register.
Called as Accumulator.
Cannot be access Directly
W content moved to some other register and then it
can be accessed.
used by many instructions as source of an
operand.
destination for the result of instruction execution.
It is a 8-bit regarding.

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 Status Register: can be destination for any instruction
contains : arithmetic status of the ALU
reset Status, bank select bits for data memory.
R/W-0 R-1 R/W - X

*R/W – X ( Write to these three bits

are disabled)
Arithmetic
Zero Bit or
NOT_TO, Carry Bit
*R-1 ( Read Only)
NOT_PD
Logical
Read Only , After reset it will get value Digital
1
RegisterBank
Register BankSelect
Select– –Indirect
Direct Addressing
Addressing
Operation
Carry
TO – Time Out ( Watches if PD – Power Down (Watches if
Watchdog
Bank Timer Out is 00 Bank 0 instruction
Sleep 00h - 7Fh is executed)
occurred
0 ) 1 =1Power
01 Bank 80h Up or CLRWDT
– FFh
01 = Power Up 00hor- CLRWDT
FFh 0 = Sleep Instruction
Bank 10 Bank 2 100h –
0 = Sleep
1 Instruction
R.Hariharan AP / EEE -SECE 1FFh
Bank 11 Bank 3 180h –
FSR – (File Select Register): Special Purpose Register
 Indirect addressing.
 8-bit register file - address pointer
 any address is first written in FSR access entire register file.

INDF – (Indirect File): Special Purpose Register

 Is not a Physical Register
 Addressing INDF - Addresses Register address
in FSR .

FSR
inc f=
INDF
INDF ==
FSR05= 06
R.Hariharan AP / EEE -SECE 10
0A
Program Counter: (PC) 13 bit wide
PCL 8 Bit – Readable
PCH 5 Bit – Not Readable

Cleared
But are indirectly writable
through the PCLATH register.
PCLATH is SFR 8 Bits but
Cleared only upper 5bits are used.

On any reset, the upper

bits of the PC will be
cleared.
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Program Counter: (PC) CALL Function

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PCL – Program Counter Low
Power ON – exists in Data Memory
/ Reset
Program
PCLATH – Program Counter
Counter Latch= 0Holding

Memory Mnemonic PC
Location L
0 ORG 0 0
1 clrf PORT A 1
2 clrf PORT B 2
3 clrf TRISA 3
4 Loop 1: clrf 4
PORTC
5
5 clrf TRISB
64
6 goto Loop1

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PCL – Program Counter
ProgramLow
Counter = 0
PCLATH – Program Counter Latch Holding
Power ON / Reset
Program Counter Low is a SFR with __ bits 8
Memory Mnemonic PC PCL – Point the next
Location L command to be executed
ORG 0 0
0 movwf PORTB Program memory – 8K.
1
1 clrf PORT A So 2^13 = 8192
2
2 clrf PORT B 3 But PCL is 8 Bits, we can
3 clrf TRISA 4 only move up to
4 Loop 1: clrf 5 2^8 = 256 different
PORTC locations
clrf TRISB
6
5
74
6 goto Loop1
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7 movwf PORTA
PCLATH – Program Counter Latch Holding
Memory
Location
Mnemonic PC
L
PCLH – Holding register
ORG 0 0 Data memory – 8K
0 clrf PORT A PC= 11, allowing to jump
1
2K
1 Call Out
2 So 2 ^ 11 = 2024
2 clrf TRISA Stack
3
8
3 Loop 1: clrf 4
PORTC .
clrf TRISB 5 .
4 .
6
5 goto Loop1 .
6 2 2
100 9
100 Out: clrf PORT B 101 1

101R.Hariharan AP return
/ EEE -SECE 0 4
PCL – (Program Counter Low Byte): Special Purpose Register
 Indirect addressing.
 the lower 8-bits of the 13-bit program counter.
 We can read the register values.

PCLATH – (Program Counter Program Counter Latch

Holding): Special Purpose Register
 upper 3-bits of PCLATH remains zero and serves
no purpose able to use only lower 5 bits
 PCLATH is automatically written into the PC at the
same time

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Memory Organization:
It has three memory blocks.
Program memory
Data memory
Stack

Program memory :
13 Bit program counter
• PIC16C7X family has a _________

• Capable of addressing an 8K x 14 program memory

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Program memory :
Place where user can write
the assembly code.
Reset Vector :
Interrupt Vector :
PC = 0000h

PC = 0004h

Reset
Interrupt
Power ON

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 Page PC LATCH Start End
Number Bit 4 Bit 3 Position Position

0 0 0 0000h 7FFh
1 0 1 800 FFFh
2 1 0 10000 17FFh
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3 1 1 1800 1FFFh
Program Memory
 A program memory of 6x/7x family controllers have
either 2k,4k or 8k address of program memory.
 PIC family uses 13-bit program counter allowing the
controllers to an 8k-program memory without
changing the CPU structure.

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R.Hariharan AP / EEE -SECE
Data Memory map

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 Who is he ?
Mr. JADAV
PAYENG
1360 Acers of Dense Forest –
Forest man of India

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 32 Bytes 32 Bytes

128 Bytes 128 Bytes

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 One Bank = 128 Bytes

Four Banks = 128 x 4

Total Bank = 512 Bytes

2 ^ 9 = 512 Bytes

To Access all RAM/Data memory

File Register = 9 Bits

96 + 80 + 16 + 80 + 16 + 80
= 368 Bytes

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 00 Bank 0 00h - 7Fh
01 Bank 1 80h – FFh
10 Bank 2 100h –
1FFh
11 Bank 3 180h –
0 0 1FFh0 0 0 0 0 0 0 00
Bank 0
0 0 1 1 1 1 1 1 1 7F

0 1 0 0 0 0 0 0 0 80
Bank 1
0 1 1 1 1 1 1 1 1 FF

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Direct Addressing

= 7 Bits

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In-direct Addressing

INDF - all bank 0x 00 Location

FSR - all bank 0x 04 Location

Bank
0
0 00h - FFh
Bank
1
Bank
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2 100h – 1FFh
1
R.Hariharan AP / EEE -SECE
Pipelining

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Only
Instruction Set Summary
35 Instructions.
PIC16CXX instruction is a 14-bit word divided.
 divided into an OPCODE & one or more OPERANDS.
OPCODE specifies instruction type
OPERANDS specify the operation of instruction.
 All instruction are executed in 1 Cycle except Conditional branch, its 2 Cycle.

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 Instruction Set Summary

 4 Oscillator Pulse = 1 Instruction Cycle

If using Oscillator = 4 MHz
1 Instruction Cycle = 1µs
Conditional branching = 2 µs
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 • Byte-oriented instruction

• Bit-oriented instruction

• Literal and Control operations instruction

Word List : f – any memory location

W – Working Register
b – Bit position in ‘f’ register.
TOS – Top of Stack.
[ ] – Option
< > - Bit position inside register.

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Byte – Oriented Instructions

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Byte – Oriented Instructions
‘ f ’ – file register ‘ d ’ – destination register
(0x00 to 0x7F)
file register – which register is to be used
by instruction.

destination register - where the result of the

operation to be placed.
d = 0; result placed in W register.
d = 1; result placed in file register
specified in instruction.
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Bit – Oriented Instructions
‘ b ’ – bit field ‘ f ’ – destination register

Ex :
btfsc PORT A, 4

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Literal and Control Instructions

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Data Transfer:
Transfer of data is done between
W register and an ‘ f ’ register

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