Scribd Logo
Upload

Welcome to Scribd!

  • 285 views

    Electronic Devices & Circuits: Khurram Bughio Lecturer Electrical Engineering, MUET

    Uploaded by

    Noor Saba
    This document discusses biasing techniques for JFET transistors, including self-bias and voltage-divider bias. Self-bias uses a single resistor to establish the operating point of the transistor, with the gate connected to ground. Voltage-divider bias uses two resistors to set the gate voltage. Both techniques aim to reverse bias the gate-source junction for proper operation. The document also covers analyzing bias circuits graphically using the transistor's transfer characteristic curve and establishing stable operating points.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd

    Electronic Devices & Circuits: Khurram Bughio Lecturer Electrical Engineering, MUET

    Uploaded by

    Noor Saba
    285 views23 pages
    This document discusses biasing techniques for JFET transistors, including self-bias and voltage-divider bias. Self-bias uses a single resistor to establish the operating point of the transistor, with the gate connected to ground. Voltage-divider bias uses two resistors to set the gate voltage. Both techniques aim to reverse bias the gate-source junction for proper operation. The document also covers analyzing bias circuits graphically using the transistor's transfer characteristic curve and establishing stable operating points.

    Original Title

    JFET Biasing

    Copyright

    © © All Rights Reserved

    Available Formats

    PPTX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document discusses biasing techniques for JFET transistors, including self-bias and voltage-divider bias. Self-bias uses a single resistor to establish the operating point of the transistor, with the gate connected to ground. Voltage-divider bias uses two resistors to set the gate voltage. Both techniques aim to reverse bias the gate-source junction for proper operation. The document also covers analyzing bias circuits graphically using the transistor's transfer characteristic curve and establishing stable operating points.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    285 views23 pages

    Electronic Devices & Circuits: Khurram Bughio Lecturer Electrical Engineering, MUET

    Uploaded by

    Noor Saba
    This document discusses biasing techniques for JFET transistors, including self-bias and voltage-divider bias. Self-bias uses a single resistor to establish the operating point of the transistor, with the gate connected to ground. Voltage-divider bias uses two resistors to set the gate voltage. Both techniques aim to reverse bias the gate-source junction for proper operation. The document also covers analyzing bias circuits graphically using the transistor's transfer characteristic curve and establishing stable operating points.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 23

    Electronic Devices & Circuits

    Khurram Bughio
    Lecturer
    Electrical Engineering, MUET
    JFET Biasing
    JFET Biasing Types
    • Just like the BJT, the purpose of biasing is to select the proper dc gate-
    to-source voltage to establish a desired value of drain current and thus,
    a proper Q-point.
    • There are two types of bias circuits
    1. Self-bias
    2. Voltage-divider bias.
    Self Bias
    • Self-bias is the most common type of JFET bias.
    • Recall that a JFET must be operated such that the gate-source junction
    is always reverse-biased. This condition requires a negative VGS for an
    n-channel JFET and a positive VGS for a p-channel JFET.
    • This can be achieved using the self-bias arrangements shown in figure
    • The gate resistor, RG , does not affect the
    bias because it has essentially no voltage
    drop across it; and therefore the gate
    remains at 0V. RG is necessary only to isolate
    an ac signal from ground in amplifier
    applications.
    • For the n-channel JFET in figure, IS produces a voltage drop across RS
    and makes the source positive with respect to ground,
    • Since IS = ID and VG = 0, then VS = IDRS
    • The gate-to-source voltage is,
    VGS = VG - VS = 0 - IDRS = -IDRS
    Thus, VGS = -IDRS
    • For the p-channel JFET, the current through RS produces a negative
    voltage at the source, making the gate positive with respect to the
    source. Therefore, since IS = ID
    Thus, VGS = +IDRS
    • In the following analysis, the n-channel JFET in figure is used for
    illustration. Keep in mind that analysis of the p-channel JFET is the same
    except for opposite-polarity voltages.
    • The drain voltage with respect to ground is determined as follows:
    VD = VDD - IDRD
    • Since, VS = IDRS
    • The drain-to-source voltage is
    VDS = VD - VS = VDD - ID(RD + RS)
    Setting the Q-Point of Self Biased JFET
    • The basic approach to establishing a JFET bias point is to determine ID
    for a desired value of VGS or vice versa. Then calculate the required
    value of RS using the following relationship. The vertical lines indicate
    an absolute value.

    • For a desired value of VGS, ID can be determined in either of two ways:


    1. From the transfer characteristic curve for the particular JFET
    2. Or using IDSS and VGS(off) from the JFET data sheet.
    Midpoint Bias
    • It is usually desirable to bias a JFET near the midpoint of its transfer
    characteristic curve where ID = lDSS/2.
    • Under signal conditions. midpoint bias allows the maximum amount of
    drain current swing between IDSS and 0. Using square law equation, it is
    seen that lD is approximately one-half of lDSS when VGS =
    VGS(off)/3.4

    • So, by selecting VGS = VGS(off)/3.4, you should get a midpoint bias in


    terms of ID.
    • To set the drain voltage at midpoint (VD = VDD/2), select a value of RD to
    produce the desired voltage drop. Choose RG arbitrarily large to
    prevent loading on the driving stage in a cascaded amplifier
    arrangement.
    Graphical Analysis of a Self-biased JFET
    • You can use the transfer characteristic curve of a JFET and certain
    parameters to determine the Q-point (lD and VGS) of a self-biased circuit.
    • A circuit is shown in figure, and a transfer characteristic curve is shown
    in figure. If a curve is not available from a data sheet, you can plot it
    from using data sheet values for IDSS and VGS(off)
    • To determine the Q-point of the circuit in figure, a self-bias dc load line
    is established on the graph as follows.
    • First, calculate VGS when ID is zero,
    VGS = -IDRS = (0)(470) = 0V
    This establishes a point at the origin on the graph (ID = O, VGS = 0).
    • Next, calculate VGS when ID = IDSS
    From the curve in figure, lDSS = 10mA
    VGS = - IDRS = -(10)(470) = -4.7V
    This establishes a second point on the graph ID = 10 mA, VGS = -4.7 V.
    • Now, with two points, the load line can be drawn on the transfer
    characteristic curve as shown in figure.
    Graphical Analysis of a Self-biased JFET
    Voltage Divider Bias
    • An n-channel JFET with voltage-divider bias is
    shown in figure. The voltage at the source of
    the JFET must be more positive than the
    voltage at the gate in order to keep the gate-
    source junction reverse-biased.
    Graphical Analysis of JFET with Voltage
    Divider Bias
    • An approach similar to the one used for self-bias can be used with
    voltage-divider bias to graphically determine the Q-point of a circuit on
    the transfer characteristic curve.
    • In a JFET with voltage-divider bias when ID = 0, VGS is not zero, as in the
    self-biased case, because the voltage divider produces a voltage at the
    gate independent of the drain current. The voltage-divider dc load line is
    determined as follows.
    Q Point Stability
    • Unfortunately, the transfer characteristic of a JFET can differ
    considerably from one device to another of the same type.
    • For example. a 2N5459 JFET is replaced in a given bias circuit with
    another 2N5459, the transfer characteristic curve can vary greatly.
    • In this case, the maximum lDSS is 16mA and the minimum lDSS is 4mA.
    Likewise, the maximum VGS(off) is - 8V and the minimum VGS(off) is -2V. This
    means that if you have a selection of 2N5459s and you randomly pick
    one out, it can have values anywhere within these ranges.
    • If a self-bias dc load line is drawn as illustrated in figure, the same
    circuit using a 2N5459 can have Q-point anywhere along the line from
    Q1, the minimum bias point to Q2, the maximum bias point.
    • Accordingly, the drain current can be any value between ID1 and ID2.This
    means that the dc voltage at the drain can have a range of values
    depending on ID.
    • Also, the gate-to-source voltage can be any value between VGS1 and VGS2.
    • Figure illustrates Q-point stability for a self-biased JFET and for a JFET
    with voltage-divider bias.
    • With voltage-divider bias, the dependency of ID on the range of Q-points
    is reduced because the slope of the bias line is less than for self-bias for
    a given JFET. Although VGS varies quite a bit for both self-bias and
    voltage-divider bias, ID is much more stable with voltage-divider bias.
    Thanks

    You might also like