Multiplexer & de Multiplexer-4
Multiplexer & de Multiplexer-4
Multiplexer & de Multiplexer-4
circuits
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ADDER :
TRUTH TABLE
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Sum = A XOR B
Carry = A AND B
K MAPS FOR HALF ADDER
FULL ADDER
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Multiplexer
➢ Multiplexer is an digital circuit that has multiple inputs and single output.
➢ The selection of 1 of n input lines is done by the select lines.
➢ It has one output selected at a time.
➢ It is also known as DATA SELECTOR.
➢ A multiplexer has,
○ N data inputs
○ 1 output
○ M select lines, with 2M = N
Block Diagram of MUX
Types of MUX
➢ 2 by 1 (1 select line)
➢ 4 by 1 (2 select lines)
➢ 8 by 1 (3 select lines)
➢ 16 by 1 (4 select lines)
2:1 MUX
0 D0
1 D1
Hardware Implementation
➢ The Logical level applied to the S input
determines which AND is enabled, so
that data input passes through the OR
gate to the output
➢ The output Y=DOS+D1S
➢ When
○ S=0,AND gate 1 is enabled and
AND gate 2 is disabled . So Y = DO
○ S=1,AND gate 1 is disabled and
AND gate 2 is enabled . So Y = D1
4:1 MUX
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
HARDWARE IMPLEMENTATION:
1. Computer Memory:
This abruptly reduces the number of logic gates or integrated circuits to perform
the logic function since the multiplexer is a single integrated circuit. In this kind
of applications, multiplexers are viewed as logic function generators.
Assume the function as F(A,B,CD) = ∑m (1,4,5,7,9,12,13)
AB 1 S0 S1 Y
0 0 I0 = CD
1 1 1
0 1 I1 = C+D
1 1
1 0 I2 = C
1
1 1 I3 = CD
De Multiplexer
➢ De-Multiplexer (De-MUX) is the reverse of Multiplex process i.e
reconverting the signal containing multiple analog & digital signals into
original separate signals.
➢ The selection of 1 of n input lines is done by the select lines.
➢ Demultiplexers are also called as DATA DISTRIBUTORS. Since they
transmit the same data which is received at the input to different
destinations.
Block Diagram of De - MUX
Types of De - MUX
Enable S Y0 Y1
E
0 x 0 0
1 0 1 0
1 1 0 1
Hardware Implementation of 1:2 De - MUX
➢ The input is routed to Y0 and Y1
depends on the value of select input
S. In the table output Y1 is active
when the combination of select line
and input line are active high, i.e., S F
= 11.
➢ When the select lines S=0, AND gate
A1 is enabled while A2 is disabled.
➢ When S=1, AND gate A2 is enabled
and AND gate A1 is disabled, thus
data is passed to the Y0 output.
1:4 De - MUX
Enable S1 S0 Y0 Y1 Y2 Y3
E
0 x x 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
Hardware Implementation of 1:4 De - MUX
1.CommunicationSystem:
Communication system use multiplexer to carry multiple data like audio, video
and other form of data using a single line for transmission. This process make the
transmission easier. The demultiplexer receive the output signals of the
multiplexer and converts them back to the original form of the data at the
receiving end. The multiplexer and demultiplexer work together to carry out the
process of transmission and reception of data in communication system.
2. ALU (Arithmetic Logic Unit)
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ENCODER:
An encoder is a combinational circuit that converts binary information in
the form of a 2N input lines into N output lines, which represent N bit
code for the input. For simple encoders, it is assumed that only one input
line is active at a time.
DECODER:
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
3:8 DECODER