Embedded System: Serial Peripheral Interface (SPI)

Taksim
Serial Peripheral Interface

)SPI(
Embedded System
Taksim Team
.Anas Reda Shamasneh
.Abdullah Barakat Njoum
.Asalah Farraj
.Doha Jaradat
Dr. Emad Hamadeh
Anas
Serial Peripheral Interface(SPI)
 The Serial Peripheral Interface (SPI) is an AHB (Advanced High

Performance Bus) peripheral , a synchronous serial
communication interface specification.
 used for short-distance communication between microcontrollers

and small peripherals such as shift registers, sensors, and SD cards
 The interface was developed by Motorola in the mid-1980s and has

become a de facto standard. Typical applications include Secure
Digital cards and liquid crystal displays.
 SPI devices communicate in full duplex mode using a master-

slave architecture with a single master.
Anas
 SPI is also called as a three wire interface, but the interface bus
comprises more than three wires. The three wires carry input data to
that slave and output data from the slave and the timing clock. The
four wires of SPI are labelled as:
 MOSI (Master Out / Slave In)

 MISO (Master In / Slave Out)
 SCK (Serial Clock)
 SS (Slave Select)
Anas

 Master Out Slave In(MOSI): Data output from the SPI Master and input to the
selected SPI slave.
 Master In Slave Out(MISO): Data input to the SPI Master and output from the
selected SPI slave. Only one selected slave device can drive data out from its
MISO pin.
 Serial Clock(SCK): Driven by the SPI Master and regulates the flow of data
bits.
 Slave Select(SS): Selects a particular slave via hardware control. Slave

devices that are not selected do not interface with SPI bus activities. The SS
control line can be used as an input to the SPI master indicating a multiple
master bus contention.
Anas
Read Protocol
Anas
Multiple slaves
 In general, each slave will need a separate SS line. To talk to a particular
slave, you'll make that slave's SS line low and keep the rest of them high (you
don't want two slaves activated at the same time, or they may both try to talk
on the same MISO line resulting in garbled data)
Anas
Multiple slaves
 On the other hand, some parts prefer to be daisy-chained together, with
the MISO (output) of one going to the MOSI (input) of the next.
 In this case, a single SS line goes to all the slaves. Once all the data is
sent, the SS line is raised, which causes all the chips to be activated
simultaneously.
Abdullah
Full duplex communication

During each SPI clock cycle, a full duplex data transmission occurs:
 the master sends a bit on the MOSI line, the slave reads it from that
same line.
 the slave sends a bit on the MISO line, the master reads it from that
same line.
Abdullah
Data Sending
 The clock is an oscillating signal that tells the receiver exactly when to
sample the bits on the data line.
 This could be the rising (low to high) or falling (high to low) edge of the
clock signal; the datasheet will specify which one to use.
 When the receiver detects that edge, it will immediately look at the
data line to read the next bit (see the arrows in the below diagram)
Abdullah
Data Receiving
 When data is sent from the master to a slave, it's sent on a data line
called MOSI, for "Master Out / Slave In".
 If the slave needs to send a response back to the master, the master
will continue to generate a prearranged number of clock cycles, and the
slave will put the data onto a third data line called MISO, for "Master In
Slave Out".
Abdullah
Bandwidth of SPI
Abdullah
Bandwidth of SPI
 The previous figure shows some of the buses with their properties.
 The SPI had the largest bandwidth since the year of its invention (1989)
till the beginning of the hyper buses invention (2001).
 There was a gap between the SPI’s bandwidth and the other buses’
bandwidth.
Abdullah
Block Diagram
Abdullah
SPI Advantages
 Full duplex communication.
 Provide good signal integrity and high speed.
 Higher throughput than I²C or SMBus. Not limited to any maximum clock
speed, enabling potentially high speed.
 Complete protocol flexibility for the bits transferred.
 Extremely simple hardware interfacing.
 At most one unique bus signal per device.
 Simple software implementation.
Abdullah
SPI Disadvantages
 Requires more pins on IC packages than I²C, even in the three-
wire variant.
 No hardware flow control by the slave (but the master can delay the
next clock edge to slow the transfer rate).
 No hardware slave acknowledgment (the master could be transmitting
to nowhere and not know it)
 Typically supports only one master device (depends on device's
hardware implementation).
 No error-checking protocol is defined.
 Only handles short distances.
 SPI does not support hot swapping (dynamically adding nodes).
Asalah
SPI Registers
Asalah
Following are the bits in the

SPCR Register
Asalah
SPI status Register

 The SPI Status Register is the register from where we can get the
status of the SPI bus and interrupt flag is also set in this register.
Asalah
SPI Data Register

 The SPI Data register is an 8-bit read/write register.
 It is used for reading the incoming data, and writing (transmitting) the
outgoing data.
 The 7th bit is obviously, the Most Significant Bit (MSB), while the 0th bit is
the Least Significant Bit (LSB).
Asalah
SPI Clock Counter Register

 This register controls the frequency of master SCK (Serial Clock).
 This is an 8-bit register.
 It indicates the number of PCLK(Peripheral clock) cycles that make up
an SPI clock.
 It should always contain an even number which is greater than 8.
Violation of this may result in unpredictable behavior.
Asalah
SPI Modes of Operation

 The master and slave have to agree on certain synchronization
protocols. For this, two features of the clock i.e. the Clock Polarity
(CPOL or CKP) and Clock Phase (CPHA) come in to picture.
 Clock Polarity determines the state of the clock. When CPOL is LOW,
the clock generated by the Master i.e. SCK is LOW when idle and
toggles to HIGH during active state (during a transfer). Similarly, when
CPOL is HIGH, SCK is HIGH during idle and LOW during active state.
 Clock Phase determines the clock transition i.e. rising (LOW to HIGH)
or falling (HIGH to LOW), at which the data is transmitted. When CPHA
is 0, the data is transmitted on the rising edge of the clock. Data is
transmitted on the falling edge when CPHA is 1.
Asalah

Depending on the values of Clock Polarity (CPOL) and Clock Phase
(CPHA), there are 4 modes of operation of SPI: Modes 0 through 3
 Mode 0:
Mode 0 occurs when Clock Polarity is LOW and Clock Phase is 0 (CPOL =
0 and CPHA = 0). During Mode 0, data transmission occurs during rising
edge of the clock.
 Mode 1:
Mode 1 occurs when Clock Polarity is LOW and Clock Phase is 1 (CPOL =
0 and CPHA = 1). During Mode 1, data transmission occurs during falling
edge of the clock.
Asalah

 Mode 2:
Mode 2 occurs when Clock Polarity is HIGH and Clock Phase is 0 (CPOL = 1
and CPHA = 0). During Mode 2, data transmission occurs during rising edge of
the clock
 Mode 3:
Mode 3 occurs when Clock Polarity is HIGH and Clock Phase is 1 (CPOL = 1
and CPHA = 1). During Mode 3, data transmission occurs during rising edge of
the clock.
Doha
The SRAM driver object

 The SPI Driver
 The SRAM System Interface
 The Local Memory Cache Sub-System
Doha
SRAM Access Methods

 This is the primary API interface for communicating with the external
Microchip 23K256 32 KB SPI memory.
 Normally, your application will make an initial call to the Init method
with a set of I/O pins to assign to chip select, clock, serial out, and
serial in.
 The Init method then initializes the SPI driver itself as well as starts up
the 23K256 and puts it into sequential access mode.
 Finally, the method initializes the cache sub-system and puts it into a
known state with an empty cache.
Doha
Cache Architecture
Doha
Cache Support Methods

 the SRAM cache is implemented as local Propeller hub memory
 when a byte is read from the SRAM, instead of reading a single byte,
the entire page is read in from the SRAM
 That access is made locally in the cache and the external SRAM is not
accessed.
 When the application require an address that is not in the cache , a new
page must be loaded in and the old page destroyed.
 This is called “thrashing” the cache. This is where the concept of “dirty”
and “clean” cache pages comes into play.
Doha
Different between UART , I2C and

SPI
Doha
Doha
Key Point
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?Any Question
Taksim Team

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Taksim

Serial Peripheral Interface

Serial Peripheral Interface(SPI)

 The Serial Peripheral Interface (SPI) is an AHB (Advanced High

 used for short-distance communication between microcontrollers

 The interface was developed by Motorola in the mid-1980s and has

 SPI devices communicate in full duplex mode using a master-

Serial Peripheral Interface(SPI)

 MOSI (Master Out / Slave In)

Serial Peripheral Interface(SPI)

 Slave Select(SS): Selects a particular slave via hardware control. Slave

Full duplex communication

Following are the bits in the

SPI status Register

SPI Data Register

SPI Clock Counter Register

SPI Modes of Operation

SPI Modes of Operation

SPI Modes of Operation

The SRAM driver object

SRAM Access Methods

Cache Support Methods

Different between UART , I2C and

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