Digital Logic Level: Ms - Chit Su Mon
Digital Logic Level: Ms - Chit Su Mon
Digital Logic Level: Ms - Chit Su Mon
In general, a circuit designer starts with a Boolean function and then
applies the laws of Boolean algebra to it in an attempt to find a simpler
but equivalent one. From the final function, a circuit can be constructed.
To use this approach, we need some identities from Boolean algebra. It
is interesting to note that each law has two forms that are duals of
each other.
By interchanging AND and OR and also 0 and 1, either form can be
produced from the other one. All the laws can be easily proven by
constructing their truth tables. Except for DeMorgan’s law, the
absorption law, and the AND form of the distributive law, the results are
reasonably intuitive.
CIRCUIT EQUIVALENCE
• Along the long edges are two parallel rows of pins about 5 mm long
that can be inserted into sockets or soldered to printed circuit
boards.
INTEGRATED CIRCUITS
Each pin connects to the input or output of some gate on the
chip or to power or to ground. The packages with two rows of
pins outside and ICs inside are technically known as Dual
Inline Packages or DIPs, but everyone calls them Chips.
Chips can be divided into rough classes based on the number
of gates they contain, as given below.
◦ SSI (Small Scale Integrated) circuit: 1 to 10 gates.
◦ MSI (Medium Scale Integrated) circuit: 10 to 100 gates.
◦ LSI (Large Scale Integrated) circuit: 100 to 100,000 gates.
◦ VLSI (Very Large Scale Integrated) circuit: >100,000 gates.
INTEGRATED CIRCUITS
An eight-input
multiplexer circuit.
MULTIPLEXER
A 3-to-8 decoder
circuit.
A simple 4-bit
comparator.
A 12-input, 6-output
programmable logic array.
The little squares represent
fuses that can be burned
out.
SHIFTERS
Notice the pairs of AND gates for all the bits except the gates on the end.
When C = 1, the right member of each pair is turned on, passing the
corresponding input bit to output. Because the right AND gate is
wired to the input of the OR gate to its left, a right shift is performed. When
C = 0, it is the left member of the AND gate pair that turns on, doing a left
shift.
ADDERS (1)
(a) (b)
A 1-bit ALU.
ARITHMETIC LOGIC UNITS
(a) A clock.
SR Latch
LATCHES
chip.
• RAMs are not the only kind of memory chips. In many applications,
such as toys, appliances, and cars, the program and some of the
data must remain stored even when the power is turned off.
• Furthermore, once installed, neither the program nor the data are
ever changed. These requirements have led to the development
of ROMs (Read-Only Memories), which cannot be changed
or erased, intentionally or otherwise.
• The data in a ROM are inserted during its manufacture,
and the only way to change the program in a ROM is to
replace the entire chip.
ROMS
• The pins, can be divided into three types: address, data, and control, are
connected to similar pins on the memory and I/O chips via a collection
of parallel wires called a bus.
• To fetch an instruction, the CPU first puts the memory address of that
instruction on its address pins.
• Then it asserts one or more control lines to inform the memory that it
wants to read (for example) a word.
• The memory replies by putting the requested word on the CPU’s data
pins and asserting a signal saying that it is done.
• When the CPU sees this signal, it accepts the word and carries out the
instruction.
CPU CHIPS
• The bus control pins are mostly outputs from the CPU to the
bus (thus inputs to the memory and I/O chips) telling whether
the CPU wants to read or write memory or do something else.
• The interrupt pins are inputs from I/O devices to the CPU. In
most systems, the CPU can tell an I/O device to start an
operation and then go off and do something else while the I/O
device is doing its work.
• Bus arbitration pins are needed to regulate traffic on the
bus, in order to prevent two devices from trying to use it at the
same time.
COMPUTER BUSES
• The problem is that wide buses need more wires than narrow ones.
• They also take up more physical space (e.g., on the motherboard)
and need bigger connectors.
• All of these factors make the bus more expensive.
• Thus there is a trade-off between maximum memory size and
system cost.
• A system with a 64-line address bus and 232 bytes of memory will
cost more than one with 32 address lines and the same 232 bytes of
memory.
• The possibility of expansion later is not free.
BUS CLOCKING