Chapter #6: Sequential Logic Design

Chapter #6: Sequential Logic Design
No. 6-1
Chapter Overview
Sequential Networks
Simple Circuits with Feedback
R-S Latch
J-K Flipflop
Edge-Triggered Flipflops
Timing Methodologies
Cascading Flipflops for Proper Operation
Narrow Width Clocking vs. Multiphase Clocking
Clock Skew
Realizing Circuits with Flipflops

Choosing a FF Type
Characteristic Equations
Conversion Among Types
Metastability and Asynchronous Inputs
Self-Timed Circuits
No. 6-2
Sequential Switching
Networks
Switching Circuits with Feedback:

Network Some outputs are also inputs
Traffic Light Controller is a complex

sequential logic network
Sequential logic forms basis for building

"memory" into circuits
These memory elements are primitive

sequential circuits
No. 6-3
Networks
Simple Circuits with Feedback
Primitive memory elements created from cascaded gates
Simplest gate component: inverter
Basis for commercial static RAM designs
Cross-coupled NOR gates and NAND gates also possible
"1"
"0" Cascaded Inverters: Static Memory Cell
LD
\LD \LD Selectively break feedback path to load new

A
value into cell
Z
LD
No. 6-4
Networks
Inverter Chains
1 0 1 0 0
A
B C D E
X
Odd # of stages leads to ring oscillator Output high

Snapshot taken just before last inverter changes propagating
thru this stage
Timing Waveform: Period of Repeating Waveform ( tp)

Gate Delay ( td)
A (=X) 0 1
B 1
tp = n * td
0
n = # inverters C
D 1
E 0
No. 6-5
Networks
Inverter Chains
Time 1 X X X X X
1 0 X X X X
1 0 1 X X X
1 0 1 0 X X
1 0 1 0 1 X
0
0 0 1 0 1
0 1 1 0 1 0
0 1 0 0 1 0
0 1 0 1 1 0
0 1 0 1 0 0
1
Propagation of Signals through the Inverter Chain
No. 6-6
Networks
Cross-Coupled NOR Gates
Just like cascaded inverters,

R with capability to force output
S to 0 (reset) or 1 (set)
R
Q
S
\Q
Timing Waveform Race

Reset Hold Set Reset Set 100 condition
Q
\Q
Forbidden Forbidden
State State
No. 6-7
Networks
State Behavior of R-S Latch
S R Q QQ QQ
01 10
0 0 hold
0 1 0
1 0 1
1 1 unstable
QQ
00
Truth Table Summary
of R-S Latch Behavior
QQ
11
No. 6-8
Sequential Logic
Networks
Theoretical R-S Latch State Diagram
SR = 00, 01 SR = 00, 10
SR = 1 0
QQ QQ
01 10
SR = 0 1
SR = 0 1 SR = 1 0
SR = 11
SR = 1 1 SR = 1 1
QQ
00
SR = 0 1 SR = 1 0
SR = 0 0
SR = 0 0, 11
QQ
11
No. 6-9
Sequential Logic
Networks
Observed R-S Latch Behavior
SR = 00, 01 SR = 00, 10
SR = 1 0
QQ QQ
01 10
SR = 0 1
SR = 0 1 SR = 1 0
SR = 11
SR = 1 1 SR = 1 1
QQ
00
SR = 0 0
SR = 0 0
Very difficult to observe R-S Latch in the 1-1 state
Ambiguously returns to state 0-1 or 1-0
A true meaning of “race condition” – the resulting state

depends on the circuit’s time-dependent behavior and
cannot be predicted in advance.
No. 6-10
Networks
Definition of Terms
Clock:
Periodic Event, causes state of memory
Tsu Th element to change
Input rising edge, falling edge, high level, low level
Setup Time (Tsu)

Clock Minimum time before the clocking event by
which the input must be stable
There
Thereisisaatiming
timing
"window"
"window" aroundthe
around the Hold Time (Th)
clocking event
clocking event Minimum time after the clocking event during
during
duringwhich
whichthetheinput
input which the input must remain stable
must remain stable
must remain stable
and
andunchanged
unchanged
in
inorder
order
to be recognized
to be recognized
No. 6-11
Networks
Level-Sensitive Latch a.k.a Gated R-S Latch
Schematic: \S
\Q
Clock \R
\enb=1 makes Q
a holding state
\enb
Timing Diagram:
\S
\R \enb >>Q propagation de
lay
\enb
Q
\Q
No. 6-12
Networks
Latches vs. Flipflops
Input/Output Behavior of Latches and Flipflops
Type When Inputs are Sampled When Outputs are Valid

unclocked always propagation delay from
latch input change
level clock high propagation delay from

sensitive (Tsu, Th around input change
latch falling clock edge)
positive edge clock lo-to-hi transition propagation delay from

flipflop (Tsu, Th around rising edge of clock
rising clock edge)
negative edge clock hi-to-lo transition propagation delay from

flipflop (Tsu, Th around falling edge of clock
falling clock edge)
master/slave clock hi-to-lo transition propagation delay from

flipflop (Tsu, Th around falling edge of clock
falling clock edge)
No. 6-13
Networks
7474
D Q
Edge triggered device sample inputs on the event
edge
Clk Level-sensitive latches sample inputs as long as the
Positive edge-triggered clock is asserted
flip-flop
7476 Timing Diagram:

D Q
D
C
Clk Clk
Level-sensitive
latch
Q
Bubble here 7474
for negative
edge triggered Q 7476
device
Behavior the same unless input changes

while the clock is high
No. 6-14
Elements
Typical Timing Specifications: Flipflops vs. Latches
74LS74 Positive
Edge Triggered Tsu Th T su Th
D Flipflop 20 5 20 5
ns ns ns ns
D
Setup time Tw
Hold time 25
Minimum clock width ns
Propagation delays Clk
(low to high, high to low, Tplh T phl
max and typical) 25 ns 40 ns
13 ns 25 ns
Q
All measurements are made from the clocking event

that is, the rising edge of the clock
No. 6-15
Networks
Typical Timing Specifications: Flipflops vs. Latches
74LS76
Clocked Transparent Latch T su Th Tsu Th
20 5 20 5
D ns ns ns ns
Setup time Tw
Hold time 20
Minimum Clock Width Clk ns
Propagation Delays:
high to low, low to high, Tplh T phl
C» Q C» Q
maximum, typical
Q 27 ns 25 ns
data to output
15 ns 14 ns
clock to output
T plh T phl
D»Q D»Q
27 ns 16 ns
15 ns 7 ns

Measurements from falling clock edge
or rising or falling data edge
No. 6-16
Elements
R-S Latch Revisited
Truth Table: Derived K-Map:

Next State = F(S, R, Current State) S
SR
S(t) R(t) Q(t) Q(t+) 00 01 11 10
Q( t )
0 0 0 0 HOLD
0 0 0 X 1
0 0 1 1
0 1 0 0 RESET 1 1 0 X 1
0 1 1 0
1 0 0 1 SET R
1 0 1 1
1 1 0 X Not Allowed Characteristic Equation:
1 1 1 X
Q+ = S + R Q t
S
R-S
R Latch Q+
No. 6-17
Networks
J-K Flipflop
How to eliminate the forbidden state?
Idea: use output feedback to

guarantee that R and S are \Q
never both one K R \Q
R-S
J, K both one yields toggle latch
J S Q
Q
J(t) K(t) Q(t) Q(t+)

0 0 0 0 HOLD
0 0 1 1
0 1 0 0 RESET
0 1 1 0 Characteristic Equation:
1 0 0 1 SET
Q+ = Q K + Q J
1 0 1 1
1 1 0 1 TOGGLE
1 1 1 0
No. 6-18
Networks
J-K Latch: Race Condition
Set Reset 100 Toggle
J
K
Q
\Q
Toggle Correctness: Single State change per clocking event
Solution: Master/Slave Flipflop
No. 6-19
Network
Master/Slave J-K Flipflop
Master Stage Slave Stage
K \P \Q
R \Q R \Q
R-S R-S
Latch Latch
S Q P S Q
J Q
Clk
Sample inputs while clock high Sample inputs while clock low
Uses
Usestime
timeto
tobreak
breakfeedback
feedbackpath
pathfrom
fromoutputs
outputsto
toinputs!
inputs!
1's
Set Reset Catch Toggle 100
J
K
Clk Correct Toggle
P Master
Operation
\P outputs
Q
Slave
\Q outputs
No. 6-20
Networks
Edge-Triggered Flipflops
1's Catching: a 0-1-0 glitch on the J or K inputs leads to a state change!
forces designer to use hazard-free logic
Solution: edge-triggered logic

Negative Edge-Triggered
D
D D flipflop
Holds D when
clock goes low
0
4-5 gate delays
R
Q setup, hold times
Clk=1 necessary to successfully
latch the input
Q
S
0
Holds D when
clock goes low
D
D
Characteristic Equation:
Q+ = D
Negative edge-triggered FF
when clock is high
No. 6-21
Network
Edge-triggered Flipflops
Guaranteed
Step-by-step analysis to hold the
previous value
D 0 4
D D
D 3 D
R R
Q 6 Q
Clk=0 Clk=0
Q 5 Q
D S D S
D 2 D
D D'
D 1 0
D' ° D
Negative edge-triggered FF Negative edge-triggered FF

when clock goes high-to-low when clock is low
data is latched data is held
No. 6-22
Sequential Switching Networks
Positive vs. Negative Edge Triggered Devices
100
D
Clk
Qpos
Positive edge-
\ Qpos triggered FF
Qneg
Negative edge-
\ Qneg triggered FF
Positive Edge Triggered Negative Edge Triggered
Inputs sampled on rising edge Inputs sampled on falling edge

Outputs change after rising edge Outputs change after falling edge
Toggle Flipflop
Formed from J-K with both inputs wired together
No. 6-23
Timing
Methodology
Overview
Set of rules for interconnecting components and clocks
When followed, guarantee proper operation of system
Approach depends on building blocks used for memory elements
For systems with latches:
Narrow Width Clocking
Multiphase Clocking (e.g., Two Phase Non-Overlapping)
For systems with edge-triggered flipflops:
Single Phase Clocking
Definition of proper operation:
(1) correct inputs, with respect to time, are provided to the FFs
(2) no FF changes more than once per clocking event

No. 6-24
Timing
Methodologies
Cascaded Flipflops and Setup/Hold/Propagation Delays
Shift Register IN Q0 Q1
D Q D Q
New value to first stage
C Q C Q
while second stage
obtains current value CLK
of first stage
100
In
Correct Operation, Q0
assuming positive
Q1
edge triggered FFs
Clk
No. 6-25
Timing
Methodologies
Cascaded Flipflops and Setup/Hold/Propagation Delays
Why this works:
Propagation delays far exceed hold times
This guarantees following stage will latch current value

before it is replaced by new value
Assumes infinitely fast distribution of the clock
In
Tsu Tsu
20 ns 20 ns
Q0 Timing
Timingconstraints
constraints
guarantee
guaranteeproper
proper
T plh T plh operation
operationof
of
Q1
13 ns 13 ns cascaded components
cascaded components
Clk
Th Th
5 ns 5 ns
No. 6-26
Timing
Methodologies
Narrow Width Clocking versus Multiphase Clocking
Level Sensitive Latches vs. Edge Triggered Flipflops
Latches use fewer gates to implement a memory function
Less complex clocking with edge triggered devices
CMOS Dynamic Storage Element

\Clk2 Feedback path broken by two
phases of the clock
\(LD·Clk1) (just like master/slave idea!)
\(LD • Clk1) Clk2
A Z 8 transistors to implement memory function
LD•Clk1
LD·Clk1 but requires two clock signals constrained
to be non-overlapping
Edge-triggered D-FF: 6 gates (5 x 2-input, 1 x 3-input) = 26 transistors!
No. 6-27
Timing
Methodologies
Narrow Width Clocking for Systems with Latches for State
Generic Block Diagram

for Clocked Sequential S
System t
Combinational
a
logic
state implemented by t
latches or edge-triggered FFs e
Clock
Two-sided Constraints:
must be careful of very fast signals as well as very slow signals!
Clock Width < fastest propagation through comb. logic

plus latch prop delay
Clock Period > slowest propagation through comb. logic

(rising edge to rising edge)
No. 6-28
Timing
Methodologies
Two Phase Non-Overlapped Clocking

Clock Waveforms:
must never overlap!

only worry about slow signals
   
Embedding CMOS storage
element into Clocked Sequential
Logic
Combinational
Logic 1 Note that Combinational Logic
can be partitioned into two
pieces
CL1: inputs latched and stable

by end of phase 1; compute
Combinational between phases, latch outputs
Logic 2 by end of phase 2
CL2: just the reverse
No. 6-29
Timing
Methodologies
Generating Two-Phase Non-Overlapping Clocks
Clk
phase1 Single reference clock (or crystal)
Phase 1 high while clock is low
Phase 2 high while clock is high
Phase X cannot go high until

phase2 phase Y goes low!
100
Clk
Phase 1
Phase 2
Non-overlap time can be increased by increasing the delay on

the feedback path
No. 6-30
Timing
Methodologies
The Problem of Clock Skew
Correct behavior assumes next state of all storage elements
determined by all storage elements at the same time
Not possible in real systems!

logical clock driven from more than one physical circuit with
timing behavior
different wire delay to different points in the circuit
Effect of Skew on Cascaded Flipflops

FF0 samples IN FF1 samples Q0
100
In
CLK2 is a delayed
Q0 version of CLK1
Q1
Clk1
Clk2
Original State: Q0 = 1, Q1 = 1, In = 0
Because of skew, next state becomes: Q0 = 0, Q1 = 0,
not Q0 = 0, Q1 = 1
No. 6-31
Timing
Methodologies
Design Strategies for Minimizing Clock Skew
Typical propagation delays for LS FFs: 13 ns
Need substantial clock delay (on the order of 13 ns) for skew to
be a problem in this relatively slow technology
Nevertheless, the following are good design practices:

distribute clock signals in opposite direction to data flows
wire carrying the clock between two communicating components

should be as short as possible
for multiphase clocked systems, distribute all clocks in similar

wire paths; this minimizes the possibility of overlap
No. 6-32
Realing Circuits with Different Kinds of FF
s
Choosing a Flipflop
R-S Clocked Latch:
used as storage element in narrow width clocked systems
its use is not recommended!
however, fundamental building block of other flipflop types
J-K Flipflop:
versatile building block
can be used to implement D and T FFs
usually requires least amount of logic to implement f (In,Q,Q+)
but has two inputs with increased wiring complexity
because of 1's catching, never use master/slave J-K FFs

edge-triggered varieties exist
D Flipflop:
minimizes wires, much preferred in VLSI technologies
simplest design technique
best choice for storage registers
T Flipflops:
don't really exist, constructed from J-K FFs
usually best choice for implementing counters
Preset and Clear inputs highly desirable!!

No. 6-33
Realizing Circuits with Different Kinds of Flipflop
s Characteristic Equations
R-S: Q+ = S + R Q Derived from the K-maps

for Q+ = ?Inputs, Q)
D: Q+ = D
E.g., J=K=0, then Q+ = Q
J-K: Q+ = J Q + K Q J=1, K=0, then Q+ = 1
J=0, K=1, then Q+ = 0
T: Q+ = T Q + T Q J=1, K=1, then Q+ = Q
Implementing One FF in Terms of Another
Q K
J Q
C D Q
D
K Q J C Q
D implemented with J-K J-K implemented with D
No. 6-34
sDesign Procedure
Excitation Tables: What are the necessary inputs to cause a
particular kind of change in state?
Q Q+ R S J K T D
0 0 X 0 0 X 0 0
0 1 0 1 1 X 1 1
1 0 1 0 X 1 1 0
1 1 0 X X 0 0 1 D
Q 0 1
Implementing D FF with a J-K FF: 0 0 1
1) Start with K-map of Q+ = (D, Q)
1 0 1
2) Create K-maps for J and K with same inputs (D, Q)
Q+ = D
3) Fill in K-maps with appropriate values for J and K
to cause the same state changes as in the original K-map
D D
Q 0 1 Q 0 1
E.g., D = Q= 0, Q+ = 0
then J = 0, K = X 0 0 1 0 X X
1 X X 1 1 0
J= D K=D
No. 6-35
s
Design Procedure (Continued)
Implementing J-K FF with a D FF:
1) K-Map of Q+ = F(J, K, Q)
2,3) Revised K-map using D's excitation table

its the same! that is why design procedure with D FF is simple!
JK J
Q 00 01 11 10
0 0 0 1 1
1 1 0 0 1
K
Q+ = D = JQ + KQ
Resulting equation is the combinational logic input to D
to cause same behavior as J-K FF. Of course it is identical
to the characteristic equation for a J-K FF.
No. 6-36
Metastability and Asynchronous Input
s
Terms and Definitions
Clocked synchronous circuits

common reference signal called the clock
state of the circuit changes in relation to this clock signal
Asynchronous circuits
inputs, state, and outputs sampled or changed independent
of a common reference signal
R-S latch is asynchronous, edge-triggered FFs are synchronous,

J-K master/slave FF is in a gray area.
Synchronous inputs
active only when the clock edge or level is active
Asynchronous inputs
take effect immediately, without consideration of the clock
Compare R, S inputs of clocked transparent latch vs. plain latch

No. 6-37
s
Asynchronous Inputs Are Dangerous!
Since they take effect immediately, glitches can be disastrous
Synchronous inputs are greatly preferred!
But sometimes, asynchronous inputs cannot be avoided

e.g., reset signal, memory wait signal
No. 6-38
Metastability and Asynchronous Output
s Handling Asynchronous Inputs
Clocked Synchronizer
Synchronous
System
Async Q0 Async Q0
D Q D Q D Q
Input Input
Clock Clock
Q1 Q1
D Q D Q
Clock Clock
Never allow asynchronous inputs to be fanned out to more than

one FF within the synchronous system
No. 6-39
s What Can Go Wrong
Setup time violation!

In
In is asynchronous
Q0
Fans out to D0 and D1
One FF catches the
signal, one does not
Q1
impossible state might
be reached!
Clk
Single FF that receives the asynchronous signal is a synchronizer
No. 6-40
s Synchronizer Failure
In ? When FF input changes close to clock edge, the FF may

D Q
enter the metastable state: neither a logic 0 nor a logic 1
It may stay in this state an indefinate amount of time, alth

ough this is not likely in real circuits
Logic 1
Logic 0
Time
Small, but non-zero probability Oscilloscope Traces Demonstrating
that the FF output will get stuck Synchronizer Failure and Eventual
in an in-between state Decay to Steady State
No. 6-41
s
Solutions to Synchronizer Failure
the probability of failure can never be reduced to 0, but it can be reduced
slow down the system clock

this gives the synchronizer more time to decay into a steady state
synchronizer failure becomes a big problem for very high speed
systems
cascade two synchronizers
not relying on the clock …
Asynchronous Synchronized
Input D Q D Q Input
Clk
Synchronous System
No. 6-42
Self-Timed and Speed Independent
Circuits
Limits of Synchronous Systems
Fully synchronous not possible for very large systems
because of problems of clock skew
Partition system into components that are locally clocked
These communicate using "speed independent" protocols
Communications
Clocked Signals Clocked
Subsystem Subsystem
Request/Acknowledgement Signaling
Request
S1 S2
Data Flow provider
requester
client server
master slave
Acknowledgement
No. 6-43
Circuits
Synchronous Signaling
Req
Data
Ack
Clk
Master issues read request; Slave produces data and acks back
Req
Data
Wait
Clk
Alternative Synchronous Scheme:

Slave issues WAIT signal if it cannot satisfy request in one
clock cycle
No. 6-44
Circuits
Asynchronous/Speed Independent Signaling
Communicate information by signal levels rather than edges!
No clock signal
4 Cycle Signaling/Return to Zero Signaling
Req
Data
Ack
(1) master raises request (3) master latches data

slave performs request acks by lowering request
(2) slave "done" by raising (4) slave resets self by lowing

acknowledge acknowledge signal
No. 6-45
Circuits
Alternative: 2 cycle signaling
Non-Return-to-Zero
Req
Data
Ack
(1) master raises request

slave services request
(2) slave indicates that it is

done by raising acknowledge
Next request indicated by low level of request
Requires additional state in master and slave

to remember previous setting or request/acknowledge
4 Cycle Signaling is more foolproof
No. 6-46
Circuits
Self-Timed Circuits
Determine on their own when a given request has been serviced
No internal clocks
Usually accomplished by modeling worse case delay within

self-timed component
Input Output
Combinational
logic
Req Ack
Delay
Models worst case delay

e.g., if combinational logic is 5 gate levels deep,
delay line between request in and ack out is
also 5 levels deep
No. 6-47
Chapter Summary
Fundamental Building Block of Circuits with State: latch and flipflop
R-S Latch, J-K master/slave Flipflop, Edge-triggered D Flipflop
Clocking Methodologies:
For latches: Narrow width clocking vs. Multiphase Non-overlapped
Narrow width clocking and two sided timing constraints
Two phase clocking and single sided timing constraints
For FFs: Single phase clocking with edge triggered flipflops
Cascaded FFs work because propagation delays exceed hold times
Beware of Clock Skew

Asynchronous Inputs and Their Dangers
Synchronizer Failure: What it is and how to minimize its impact
Speed Independent Circuits

Asynchronous Signaling Conventions: 4 and 2 Cycle Handshakes
Self-Timed Circuits
No. 6-48

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Chapter #6: Sequential Logic Design

Realizing Circuits with Flipflops

Metastability and Asynchronous Inputs

Switching Circuits with Feedback:

Traffic Light Controller is a complex

Sequential logic forms basis for building

These memory elements are primitive

Simplest gate component: inverter

Basis for commercial static RAM designs

Cross-coupled NOR gates and NAND gates also possible

\LD \LD Selectively break feedback path to load new

Odd # of stages leads to ring oscillator Output high

Timing Waveform: Period of Repeating Waveform ( tp)

Propagation of Signals through the Inverter Chain

Just like cascaded inverters,

Timing Waveform Race

Very difficult to observe R-S Latch in the 1-1 state

Ambiguously returns to state 0-1 or 1-0

A true meaning of “race condition” – the resulting state

Setup Time (Tsu)

Input/Output Behavior of Latches and Flipflops

Type When Inputs are Sampled When Outputs are Valid

level clock high propagation delay from

positive edge clock lo-to-hi transition propagation delay from

negative edge clock hi-to-lo transition propagation delay from

master/slave clock hi-to-lo transition propagation delay from

7476 Timing Diagram:

Behavior the same unless input changes

All measurements are made from the clocking event

Truth Table: Derived K-Map:

Idea: use output feedback to

J(t) K(t) Q(t) Q(t+)

Set Reset 100 Toggle

Toggle Correctness: Single State change per clocking event

Solution: Master/Slave Flipflop

Solution: edge-triggered logic

Negative edge-triggered FF Negative edge-triggered FF

Positive Edge Triggered Negative Edge Triggered

Inputs sampled on rising edge Inputs sampled on falling edge

When followed, guarantee proper operation of system

Approach depends on building blocks used for memory elements

For systems with latches:

Narrow Width Clocking

Multiphase Clocking (e.g., Two Phase Non-Overlapping)

For systems with edge-triggered flipflops:

Single Phase Clocking

Definition of proper operation:

(2) no FF changes more than once per clocking event

This guarantees following stage will latch current value

Assumes infinitely fast distribution of the clock

Less complex clocking with edge triggered devices

CMOS Dynamic Storage Element

Edge-triggered D-FF: 6 gates (5 x 2-input, 1 x 3-input) = 26 transistors!

Generic Block Diagram

Clock Width < fastest propagation through comb. logic

Clock Period > slowest propagation through comb. logic

CL1: inputs latched and stable

CL2: just the reverse

Phase 1 high while clock is low