JSS ACADEMY OF TECHNICAL EDUCATION

Department Of Electronics And Communication

JSS campus Dr Vishnuvardhan road, Bengalluru-560060

PROJECT TITLE
Design and Implementation of Accuracy-Controllable Approximate Multiplier

SL.no NAME USN

1 SUPRIYA 1JS15EC106

Under the guidance of

2 T S PRIYA 1JS15EC108
Mrs Saroja S Bhusare
Asst. Professor, Dept of E & C
3 NANDINI C R 1JS16EC412
JSSATE, Bangalore-60

4 RAKSHITHA N 1JS16EC418
 CONTENTS
• Introduction
• Problem Statement
• Objectives
• Literature Survey
• Conventional Multiplier
• Braun Multiplier
• Wallace Multiplier
• Approximate Multiplier
• Approximate Multiplier Results
• Wallace Tree Multiplier Results
• Comparison With Wallace
• Conclusion
• Future Scope
 INTRODUCTION

 Multipliers are key components of many high performance systems such as

Microprocessors, Digital Signal Processors, ALU [Arithmetic Logic Unit], etc.

 Multiplier operation is essential and abundant in DSP Applications. Achieving

maximum implementation efficiency and clock performance is therefore
critical to DSP systems and frequently presents a significant challenge to
hardware engineers.

 Multipliers play a key role in the high performance Digital Systems. Design
considerations of multipliers include the following- high speed, low power
consumption, short critical delay path and reduced area.
 PROBLEM STATEMENT

Design and implementation of Accuracy-Controllable Approximate Multipliers

The aim of the Project is to design and implement an approximate multiplier which
consumes less power and has shorter critical path.

OBJECTIVES
 To carry out extensive literature survey on approximate multipliers.

 To design and implement an approximate multiplier that can control accuracy

dynamically.

 To implement a multiplier which consumes less power and has a shorter critical path
delay than the conventional multipliers.

 To validate the design with an application.

 LITERATURE SURVEY
SL. Title of the paper Journal Author Problem Author Results
NO published addressed approach/m
ethod
1 Design & Analysis April- Amir High power Dadda Transistor count-
of Approximate 2015 Momeni, usage and Multiplier 50%
compressors for Jie Han, large area of using gate improvement.
Multiplication Paolo compressors level Power
Montuschi implementati consumption-60%
on. improvement
In terms of delay
44% in the
designed
compressor
2 Design of A 2015 Soheil Low Power Analyzed Gaussian error
dynamic Range Hashemi, efficiency DRUM’s distribution with
Unbiased R. Iris error & non-zero average.
Multiplier for Bahar, power With standard
approximate Sherief consumption deviations of
applications Reda charactereisti 0.45% to 0.61%
cs both This design
analytically achieves power
and savings of 58%.
emperically .
SL. Title of the paper Journal Author Problem Author Results
NO published addressed approach/method
3 Approximate 2015 Zhixi Yang, Accuracy , 3 approximate 4- Achieved
compressors for Jie Han, error 2compressors are significant
error resilient Fabrizio control proposed for the reductions
multiplier design Lombardi partial product in area and
reduction in power of
multiplier compressor
for
multiplier
design.
4 Analysis of 2016 K’Andrea Area Designed Dadda Power
column C, ,delay and and Wallece consumption
compression Bickerstaff, power column , area,and
multipliers Earl E compression delay is
Swartzland multipliers in deep reduced.
er submicron
technology
 CONVENTIONAL MULTIPLIER
• A conventional array multiplier is one of the most basic parallel multiplier circuit.
The major limitation of an array multiplier is its area size. Fig.1 shows the
multiplication process of Array Multiplier.
• This results in increase in area , power consumption and carry propagation delay.
To overcome these problem we go for approximate multiplier design.

Fig.1. Multiplication in Array Multiplier

 BRAUN MULTIPLIER

Fig.2. Schematic of Braun multiplier

WALLACE TREE MULTIPLIER

Fig.3. Dot diagram of Wallace Multiplier

 APPROXIMATE MULTIPLIER
INCOMPLETE ADDER CELL

 Accurate half adder and Incomplete

adder cell (iCAC) are shown in Fig.4(a)
and Fig.4(b) respectively.
Figure (a) shows an accurate half adder,
for which the following equation can be Fig.4 (a) Accurate half adder Fig.4 (b) Incomplete adder cell
obtained.

{c,s} = a+b = 2c+s = (c+s) +c

for the adder cell in fig.(b) the equations

follows as :
p = c+s , q=c
{c,s} = a+b = p+q
RESULT OF ACCURATE HA & ICAC
AREA ,POWER OF HA & ICAC
DELAY OF HA & ICAC
A row of incomplete adder cells with two 8-bit
inputs

Fig.5. A Row of Incomplete Adder Cells with two 8-bit inputs.

Two 8-bit outputs :
Approximate sum : P = {p7, p6, p5, p4, p3, p2, p1, p0}
Error recovery vector : Q = {q7, q6, q5, q4, q3, q2, q1,q0}
Approximate Tree Compressor with eight inputs

Fig.6. Structure of an ATC with eight inputs

Where P1,P2,P3 and P4 are the approximate sum
Q1,Q2,Q3 and Q4 are error recovery vectors
V is the accuracy compensation vector.
 CARRY MASKABLE ADDER
 A CMA is used to control the accuracy flexibly and dynamically. A ‘K’ bit CMA
comprises ‘K-1’ carry maskable full adder and 1 Carry maskable half adder. Fig.7(a) and
Fig.7(b) shows Carry maskable half adder and Carry maskable full adder respectively.

 If mask_x signal is “0” then s=x OR y, Cout=0

If mask_x signal is “1” then s=x XOR y, Cout=x AND y

Fig. 7. (a) Carry maskable half adder Fig.7(b) Carry maskable full adder
RESULT OF CMA( when maskx is “0”)
RESULT OF CMA( when maskx is “1”)
Structure of an 8-bit multiplier with 8x8 partial products

Fig.8. Structure of an 8-bit Multiplier with 8 x 8 Partial Products.

 Approximate Multiplier Results

a b Expected values x ( obtained results)

55 22 0B4A 0AAA
A0 0C 0780 0780
A3 B0 7010 5FF0
Synthesized RTL diagram of Approximate Multiplier
Wallace Tree Multiplier Results
Synthesized RTL diagram of Wallace Tree
Multiplier
AREA,POWER,DELAY OF APPROXIMATE MULTIPLIER
AREA,POWER,DELAY OF WALLACE
MULTIPLIER
 COMPARISION WITH WALLACE

SL NAME OF THE MULTIPLIER AREA POWER DELAY

NO
5030 units 461496.19 nw 4599 ps

1. Wallace Tree Multiplier

3672 units 175762.91 nw 1037 ps

(reduced 26.9%) (reduced 61.9%) (reduced
2. Approximate multiplier 77.45%)
 CONCLUSION

An accuracy-controllable approximate multiplier has been designed in this project that

consumes less power and has a shorter critical path delay than the conventional Multiplier. Its
dynamic controllability is realized by the proposed CMA. The multiplier was evaluated at both the
circuit and application levels. The experimental results demonstrate that the approximate
multiplier was able to deliver significant power savings and speedups while maintaining a
significantly smaller circuit area than that of the conventional Wallace tree multiplier. The
quantitative values obtained for Approximate Multiplier are as follows, the power reduced by
61.9%, Area reduced by 26.9%, delay reduced by 77.45%. Furthermore, for the same accuracy,
this multiplier deliveres greater improvements in both power consumption and critical path delay
than other previously studied approximate multipliers.

FUTURE SCOPE
The designed multiplier can be validated for an application such as digital image processing
and digital system processor. Efficient technique can be applied to further improvise the accuracy
of the multipliers.
THANK YOU