Physical Verification

PHYSICAL VERIFICATION
AGENDA
 DRC (Design Rule Check)

 LVS (Layout vs Schematic)
 ERC (Electrical Rule Check)
 LEC (Logic Equivalence Check)
 Antenna Effect
DRC (DESIGN RULE CHECK)
 Design rule checks are nothing but physical checks of metal width, pitch and spacing
requirement for the different layers with respect to different manufacturing process.
 If we give physical connection to the components without considering the DRC rules,
then it will lead to failure of functionality of chip, so all DRC violations has to be cleaned
up.
 After the completion of physical connection, we check each and every polygon in the
design, based on the design rules and reports all the violations. This whole process is
called Design Rule Check.
 Inputs of DRC :- netlist, GDS-II, Rule Deck File

 Types of DRC
 Minimum width and spacing for metal.
 Minimum width and spacing for via.
 Enclosed Via Spacing Rule
 Minimum Enclosed Area Rule
 Shorts violation
 Misaligned Via wire
 Short Violation
Solution
 Different Spacing violation
Solution
 Same layer spacing with net and cell geometry blockage.
Solution
 Minimum area requirement
Solution
 VIA Misalignment
Solution
LVS (LAYOUT VS SCHAMETIC)
 Inputs:- netlist, GDS-II, LVS Rule Deck File

 LVS rule deck file contains the layer definition to identify the layers used in layout file and
to match it with the location of layer in GDS. It also contains device structure definitions.
LVS (LAYOUT VS SCHEMATIC)
 LVS check involve three steps:

 Extraction
 The tool takes GDSII file containing all the layers and uses polygon based approach to
determine the components like transistors, diodes, capacitors and resistors and also
connectivity information between devices presented in the layout by their layers of
construction. All the device layers, terminals of the devices, size of devices, nets, vias and the
locations of pins are defined and given an unique identification.
 Reduction
 All the defined information is extracted in the form of netlist.
LVS (LAYOUT VS SCHEMATIC)
 Comparison
 The extracted layout netlist is then compared to the netlist of the same stage using the LVS
rule deck. In this stage the number of instances, nets and ports are compared. All the
mismatches such as shorts and opens, pin mismatch etc.. are reported. The tools also checks
topology and size mismatch.
 Typical errors which can occur during LVS checks are:

 Shorts
 Opens
 Component mismatch
 Missing components
 Parameter mismatch
ERC (ELECTRICAL RULE CHECK)
 ERC involves checking a design for all electrical connection.

 Checks such as
 Well and subtract area for proper contact and spacing.
 Unconnected input or shorted output.
 Gates should not connect directly to supply (Must be connect through TIE high/low cells only).
 Floating gate error
 If any gate is unconnected, this could lead to leakage issues.
 VDD/VSS errors:
 The well geometries need to be connected to power/Ground and if the PG connection is not
complete or if the pins are not defined, the whole layout can report errors like “NWELL not
connected to VDD.
LEC (LOGIC EQUIVALENCE CHECK)
 Inputs:- library files, Golden netlist, Reference netlist

 Ensure the functional check between RTL and Netlist.
 LEC can be perform between any two representations of a design:
 RTL vs Netlist OR Reference Netlist vs Golden netlist.
ANTENNA CHECKS
 Antenna Check The antenna effect is caused by the charges collected on the floating
interconnects, which are connected to only a gate oxide. During the metallization, long
floating interconnects act as temporary capacitors and store charges gained from the
energy provided by fabrication steps such as plasma etching and CMP. If the collected
charges exceed a threshold, the Fowler-Nordheim (F-N) tunneling current will discharge
through the thin oxide and cause gate damage. On the other hand, if the collected
charges can be released before exceeding the threshold through a low impedance path,
such as diffusion, the gate damage can be avoided
ANTENNA CHECKS
 Antenna Check For example, considering the routing in Figure A, the interconnects are
manufactured in the order of poly, metal 1, and metal 2. After manufacturing metal 1 (see
Figure B), the collected charges on the right metal 1 pattern may cause damage to the
connected gate oxide. The discharging path is constructed after manufacturing metal 2
(see Figure C), and thus the charges can be released through the connected diffusion on
the left side.
ANTENNA CHECKS
 Solution for antenna violation

 Jumper insertion
 Embedded protection diode

Physical Verification

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PHYSICAL VERIFICATION

 DRC (Design Rule Check)

 Inputs of DRC :- netlist, GDS-II, Rule Deck File

 Different Spacing violation

 Same layer spacing with net and cell geometry blockage.

 Minimum area requirement

 Inputs:- netlist, GDS-II, LVS Rule Deck File

 LVS check involve three steps:

 Typical errors which can occur during LVS checks are:

 ERC involves checking a design for all electrical connection.

 Inputs:- library files, Golden netlist, Reference netlist

 Solution for antenna violation

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