Overview of PCI Express

Overview of PCI Express
Agenda
• History of PCI
• Introduction to PCI Express
• Benefits of PCI Express
• PCI Express Architecture
• Virtual Instrumentation and PCI Express
History of PCI Express
History of PCI
• PCI Overview
• PC Architecture with PCI
• Challenges Facing PCI
PCI Bus History and Overview
• Speeds of 33MHz – 66MHz
• Unifying effect on PC
• Processor Independence
• Buffered Isolation
• Bus Mastering
• Plug-and-Play Operation
PC Architecture with PCI
PCI Challenges
• Limited Bandwidth
• Bandwidth shared between all devices
• Limited host pin-count
• Lack of support for real time data transfer
• Stringent routing rules
• Lack of scaling with frequency and voltage
• Absence of power management
Introduction to PCI Express
Introduction to PCI Express
• Evolution of PC Buses
• PCI Express in Desktops
• ExpressCard: PCI Express for Laptops
Evolution of PC Buses
20 GHz+
15 GHz
>12 GHz Copper Signalling Limit

10 GHz
5 GHz
1 GHz Parallel Bus Limit

1 GHz
AGPx
HL
66 MHz
PCIx
VL PCI Bus
VESA
8.33 MHz EISA
MCA
ISA Bus
80s 90s 00s

Evolution of Industry Standard Bus Throughput
100000 PCI Express Gen 2
USB PCI Express Gen 1
Ethernet
10000 PC Buses PCI -X 1.0 40X
PCI 2.x
Speed (Mbits/S)
PCI 1.x Gigabit Ethernet

1000
EISA/MC
ISA USB 2.0
Fast Ethernet
100
10
Ethernet USB 1.1
Year
Industry Bus Performance
10000
Max Bandwidth (Mbytes/s)
PCI Express (x16)

1000
Gigabit Enet PCI (32/33)
100 USB 2.0
IEEE 1394a
Fast Enet
10 GPIB
USB 1.1
1
10000 1000 100 10 1 0.1
Approximate Latency (usec)
PCI Express: Evolutionary Model of PCI
• Serial interconnect @ 2.5Gb/S
– PCI transactions are packetized and then serialized
– LVDS Signalling, point-to-point, 8B/10B encoded
– Bandwidth is available PER slot, and in BOTH directions
– X1 gives real-world performance of 200MByts/S/direction
– X16 gives real-world performance of 3.2GBytes/S per
direction
PCI Express in Desktops
x16 PCIe
Replaced AGP
Six
PCI
Four
x1 PCIe
Intel 925XE Express Chipset

ExpressCard : PCI Express for Laptops
• 34mm and 54 mm form-factors
Both USB 2.0

And PCIe signaling
on host
Benefits of PCI Express
• Bandwidth Improvements
• Software Backward Compatibility
• Layered Architecture
• Next Generation I/O
• I/O Simplification
Improved Bandwidth
• Up to 30X bandwidth increase
over PCI
• Scalable bandwidth by
increasing lane width
Bus Bandwidth (MBytes/s)

PCI (32-bit, 33 MHz) 132
x1 PCI Express 250
x4 PCI Express 1000
x16 PCI Express 4000
Dedicated Bandwidth
• PCI Express dedicates bandwidth per device
Software Backward Compatibility
PCI and PCI Express

PCI PnP Model (init, enum, config)
use same software
OS Config
No OS Impact
model
PCI Software/Driver Model
S/W
Packet-based Protocol
Transaction
New hardware layers
Data Link
Data Integrity deliver 30X
performance of PCI
Physical Point-to-point, serial, differential… Future speeds and
encoding technologies
only impact physical layer
• Layered Architecture
– Adapts to new technologies, while preserving software
investment.
– Future increased signaling rates
– Software compatibility
• Next-Generation I/O
– Isochronous (guaranteed) bandwidth
– Key for next generation high performance data acquisition
and multimedia applications
Up-plugging
Installing boards in higher lane slots
– Allowed by PCI Express
– Example: plugging a x4 PCI Express module in a x8 slot
– Caveat: Motherboard vendors only required to support a x1
data rate in this configuration
• Full bandwidth support will be vendor specific
Down-plugging
Installing boards in lower lane slot
– Physically prevented by the design of the slots and
connectors for Desktop (PCI) form-factor
– Will be allowed in CompactPCI Express and PXI Express
Card Interoperability
The specification only guarantees a x1 connection when down plugging (i.e.

a x4 card in a x16 slot may only negotiate to a x1)
PCI Express Architecture
PCI Express Architecture
• PCI Express Layers
• 8B/10B Encoding
• Scalable Lane Widths
• Isochronous Transfer
• PCI Express Flow Control
PCI Express Layers
OS Config PCI PnP Model (init, enum, config)
No OS Impact
S/W PCI Software/Driver Model
Transaction Packet-based Protocol
Data Link Data Integrity
Physical Future speeds and

Point-to-point, serial, differential…
encoding technologies
only impact physical layer
PCI Express Physical Layer
Sequence Packet
Frame CRC Frame
Data Number Request Data
Device B
Data Device A X1 Lane
Data
Packet Sequence
Frame CRC Frame
Clock Request Number
Clock
• Point to point differential interconnect with 2 endpoints

• Two unidirectional links, No Sideband Signals
• Bit rate: > 2.5Gb/s/pin/dir and beyond
• Clocking: Embedded clock signaling using 8b/10b encoding
• Interface Width: Per direction: x1, x2, x4, x8, x12, x16, x32
• Gen-2 (5GB/s) speed increase in mid ‘06
8B/10B Encoding
• Consumes 20% of available bandwidth
– Incorporated into 250 Mbytes/s bandwidth numbers already
• Guarantees minimum transition density
• Allows for clock recovery on each transition
• Routing Flexibility
– No need to address clock/data skew
PCI Express Lane Width ...
...
Byte 5 Byte 5
Byte 4 Byte Stream Byte 4
Byte 3 {conceptual} Byte 3
Byte 2 Byte 2
Byte 1 Byte 1
Byte 0 Byte 0
Byte 3
Byte 2
Byte 4 Byte 5 Byte 6 Byte 7
Byte 1
Byte 0 Byte 1 Byte 2 Byte 3
Byte 0
8b/10b 8b/10b 8b/10b 8b/10b

8b/10b P>S P>S P>S P>S
P>S
Lane 0 Lane 0 Lane 1 Lane 2 Lane 3
Bandwidth is selectable using multiple lanes

Isochronous Support
• PCI Express employs a traffic class (TC) / virtual channel (VC) scheme
• Traffic Class determines priority.
• Device drivers or application software assign the traffic class
• Virtual channels are hardware buffers on PCIe devices
• Flexible (and complicated) mapping of TC’s to specific VC buffers inside
devices
• Internal arbitration and prioritization takes place in order to determine
which packets are forwarded first.
Flow Control in PCI Express
• Credit-based flow control
– Can only transmit if receiver has buffer space
– No dropped packets
– No retries (Doesn’t send if packet cannot be received)
– Congestion spreads “up the chain”
• Split transaction
– Request packets requiring a response are split
• Handled entirely within the data link layer
• Frees up bandwidth
Virtual Instrumentation and PCI Express
PCI Express M Series Data Acquisition
• Up to 32 channels, 16-bit,
1.25 MS/s analog inputs
• High-speed analog, digital,
and counter I/O on a single
device
• x1 PCI Express connector
• Backward software
compatibility
NI PCIe-6251 Ÿ NI PCIe-6259
Industry’s First PCI Express Frame Grabber
NI PCIe-1429
– Supports any Camera Link camera
– x4 PCI Express connector
• 680 MB/second throughput
(Camera Link maximum)
– PCI Express Vision in Action!
NI PCIe-GPIB
• x1 PCI Express interface
• High-performance GPIB
– 1.5 Mbytes/s (standard)
– 7.9 Mbytes/s (HS488)
• Ships with NI-488.2 for Windows
2000/XP
• For applications with available PCI Express slot(s)

PCI Express Control of PXI with MXI-Express
• Two MXI-Express kits
– NI PXI-PCIe8361 has one x1 cabled PCI Express link
– NI PXI-PCIe8362 has two x1 cabled PCI Express links
• Control of two PXI chassis from a single PCI Express
board with the NI PCIe-8362
• Over 40% increase in the throughput of PCI control of
PXI with MXI-4
• Sustained throughput
– 160 MB/s (two chassis)
– 110 MB/s (one chassis)
PCI Express Overview
• PCI Express is the next evolution in PC bus technology
– Up to 30X bandwidth improvement over PCI
– Dedicated bandwidth per device
– Backward software compatibility
• PCI and PCI Express will be offered side-by-side in Desktop
PCs during adoption stages
• PCI Express fuels new applications for control, test, and design
with Virtual Instrumentation

Overview of PCI Express

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Overview of PCI Express

>12 GHz Copper Signalling Limit

1 GHz Parallel Bus Limit

80s 90s 00s

PCI 1.x Gigabit Ethernet

PCI Express (x16)

Intel 925XE Express Chipset

Both USB 2.0

Bus Bandwidth (MBytes/s)

PCI and PCI Express

The specification only guarantees a x1 connection when down plugging (i.e.

S/W PCI Software/Driver Model

Transaction Packet-based Protocol

Data Link Data Integrity

Physical Future speeds and

• Point to point differential interconnect with 2 endpoints

8b/10b 8b/10b 8b/10b 8b/10b

Lane 0 Lane 0 Lane 1 Lane 2 Lane 3

Bandwidth is selectable using multiple lanes

• For applications with available PCI Express slot(s)

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