Lecture 10 - Interrupts

Interrupts
MOKHTAR NIBOUCHE
[email protected]
ROOM 2N36
DEPARTMENT OF ENGINEERING DESIGN AND MATHEMATICS
FACULTY OF ENVIRONMENT AND TECHNOLOGY
UNIVERSITY OF THE WEST OF ENGLAND
Learning Outcomes
2
At the end of the lecture you should be able to

understand:
The concept of interrupts in microcontrollers.
The interrupt process for the PIC P16F877.
Introduction
3
You are preparing for an exam
The telephone starts ringing
There is somebody at the door
There is a fire in the kitchen

What are interrupts?
4
Interrupts are hardware- or software-driven signals that

cause a microcontroller (or processor) to suspend its
current programme sequence and execute a subroutine
(Interrupt Service Routine or ISR).
Typically, interrupts are generated by peripherals or
hardware devices that need to give data to or take data
from the microcontroller (for example, A/D and D/A
converters and other processors).
Interrupts can also signal that a particular event has
taken place (for example, a timer has finished counting,
an EEPROM has finished writing data ..).
Interrupts can be triggered either by software or by
hardware (a pin, an external peripheral, or on-chip
peripheral/logic).
5
If hardware interrupts are triggered at the same

time, the microcontroller services them according
to a set priority ranking.
Interrupts, whether hardware or software, can be
placed in one of the following two categories:
Maskable interrupts. These are interrupts that can be
blocked (masked) or enabled (unmasked) through
software.
Non-maskable interrupts. These interrupts cannot be
blocked. The microcontroller will immediately approve
this type of interrupt and branch to the corresponding
subroutine (for example, a Microcontroller RESET).
What are interrupt?
6
Interrupts are generally handled in four main phases:

Receive the interrupt request. Suspension of the
current programme sequence must be requested by a
software interrupt (from program code) or hardware
interrupt (from a pin or an on-chip device).
Approve the interrupt. The microcontroller must
approve the interrupt request. If the interrupt is maskable,
certain conditions must be met in order for the core to
approve it. For nonmaskable interrupts, approval is
immediate.
Prepare for the interrupt service routine and save
register values (context save).
7
Execute the interrupt service routine. The micro-

controller branches to its corresponding interrupt service
routine (ISR). At the end of the process, the core resumes its
initial task (context restore).
After a reset is initiated, all the interrupts are disabled. The
first thing to do then is to globally enable them.
8
(Flag) (Enable) (Global Enable)

Register Register Global Switch
1
Interrupts
0
Core
1
Interrupt Process for the P16F877
9
14 possible interrupt sources

Timer0, Timer1 and Timer3 overflow interrupts (max value 255);
ADC conversion complete interrupt;
Data EEPROM write complete interrupt;
INT Pin interrupt (external)
PORT B change interrupt (pins RB7:RB4)
........ (refer to the data sheet for the remaining sources)
To be operational, the interrupts have to be enabled.
After a reset is initiated, all interrupts are disabled.
The global enable (global switch) is also disabled.
10
PIE and PIR

Registers
INTCON
register
Bits ending with IF represents the Flag bits

Bits ending with IE represents the Enable bits
PEIE for the peripheral interrupt enable bit
GIE for the global interrupt enable bit
11
Interrupts are controlled by at least three registers

INTCON (Interrupt Control Register) This register
contains the status of the high-priority interrupts.
PIE (PIE1, PIE2) (Peripheral Interrupt Enable
Register) This register contains the interrupt
enabling bits of the low-priority interrupts.
PIR (PIR1, PIR2) (Peripheral Interrupt Flag
Register) This register contains the interrupt flags
of the low-priority interrupts.
OPTION_REG could also be involved (INTEDG<6>
for an external interrupt).
12
INTCON at addresses 0Bh

(Bank 0), 8Bh (Bank 1), 10Bh
(Bank 2) and 18Bh(Bank 3).
PIE1 and PIE2 at Addresses
8Ch (Bank 1) and 8Dh (Bank 1).
PIR1 and PIR2 at addresses
0Ch (Bank 0) and 0Dh (Bank 0).
OPTION_REG at addresses
81h (Bank 1) and 181h (Bank 3).
13
When an interrupt is enabled, the
PC is loaded with 0004h (Interrupt
Vector Address).
The Global Interrupt Enable (GIE)
bit is cleared.
The return address is PUSHed into
the stack.
The programme processes the
subroutine associated with the
interrupt (Interrupt Service
Routine).
On completion, the address of the
next isntruction is POPed from the
stack.
The programme resumes its initial
activity.
(the Flag bit has to be cleared
manually)
14
Two major issues.

1. It is only the address of the
next instruction that is
PUSHed into the stack. You
might need to save the
content of some registers (W
and STATUS at least)
2. Interrupt Latency: the time
from the interrupt event
occurring (flag bit set) to the
time that the instruction at
address 0004h starts
executing (interrupt
enabled). This takes 3 to 4
cycles.
15
INTCON Register
0Bh (Bank 0);
8Bh (Bank 1);
10Bh (Bank 2);
18Bh(Bank 3).
16
Example: Using an external interrupt

(RB0/INT), which corresponds to pin 33 on the
P16877.
Set pin <7> of the INTCON register to 1 (High). This
will enable the interrupts globally (GIE = 1).
Set pin <4> of the INTCON register to 1 (High). This
will inform the processor that RB0 has been set as the
external interrupt pin (INTE = 1).
To define the event (rising edge or falling edge of the
clock), bit <6> INTEDG of the OPTION_REG has to be
set. By default, INTEDG = 1.
17
Example: Using an external interrupt

(RB0/INT), which corresponds to pin 33 on
the P16877.
When an interrupt occurs, bit <1> of INTCON
register is set (INTF = 1). This flag has to be reset
manually (by software).
The PC is loaded with the Interrupt Vector
Address 0004h.
The ISR is processed.
18
ORG 0000h ;at power up or reset (using the command ORG)

GOTO start ;Goto to main
ORG 0004h ;Processor jumps here if there is an interrupt
GOTO ISR ;Goto the ISR (could be processed directly as well)
.............
............. ; code
.............
ISR
............. ; ISR code
.............
RETFIE ;End of the interrupt routine

.............
............. ; code
.............
start ; start of main

Further Reading
19
PICmicro Mid-Range MCU Family (DS33023A)

Section 8 Interrupts.
http://hobbyprojects.com/pic_tutorials/tutorial11.html
http://hobbyprojects.com/pic_tutorials/tutorial12.html

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Interrupts

At the end of the lecture you should be able to

You are preparing for an exam

The telephone starts ringing

There is somebody at the door

There is a fire in the kitchen

Interrupts are hardware- or software-driven signals that

If hardware interrupts are triggered at the same

Interrupts are generally handled in four main phases:

Execute the interrupt service routine. The micro-

(Flag) (Enable) (Global Enable)

14 possible interrupt sources

PIE and PIR

Bits ending with IF represents the Flag bits

Interrupts are controlled by at least three registers

INTCON at addresses 0Bh

Two major issues.

Example: Using an external interrupt

Example: Using an external interrupt

ORG 0000h ;at power up or reset (using the command ORG)

RETFIE ;End of the interrupt routine

start ; start of main

PICmicro Mid-Range MCU Family (DS33023A)

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