8085 Interrupts: Md. Asaduzzaman, 17114005 Sanjib Majumder, 17114001 Anuwarul Kabir, 17114008

8085 Interrupts
Md. Asaduzzaman, 17114005

Sanjib Majumder, 17114001
Anuwarul Kabir, 17114008
MCSE 6003 : Microprocessor Design

Why interrupts are needed?
I/O devices connected to p, may demand
service at any time.
In two ways p can service:
o Polling Routine - p checks each of the I/O
devices every so often.
o Interrupt - I/O device sends service request to p
whenever it needs.

What is Interrupt?
Interrupt is signals send by an I/O device to the p, to request the p to
perform a particular task or work.
The process starts from the I/O.
p checks for any interrupts at the 2nd T-state of last machine cycle.
Interrupts sent by I/O devices are of asynchronous type.

Terminology
Maskable Interrupt - Those interrupts whose request can be denied by p.
Non-maskable Interrupt - Interrupts whose request cannot be denied.
Interrupt Service Routine (ISR) - is a special block of code associated with a

specific interrupt
Interrupt Vector - is the memory location of ISR.
Level Triggering - the circuit will become active when clock pulse is on a particular
level.
Edge Triggering - the circuit becomes active at negative or positive edge of the
clock signal.
Logic Diagram of Maskable and Non-maskable Interrupt

Types of Interrupts
Two Types of Interrupts
1. Software Interrupt - cause of the interrupt is the execution of the special
instructions supported by the p.
2. Hardware Interrupt - An external device initiates the hardware interrupts and
placing an appropriate signal at the interrupt pin of the processor.

Software Interrupts
A software interrupt is a particular instruction that can be inserted into the
desired location in the program.
There are eight software interrupts in 8085:
1. RST0
2. RST1
3. RST2
4. RST3
5. RST4
6. RST5
7. RST6
8. RST7

Software Interrupts
Allow the p to transfer program control from the main program to a
subroutine program.
The program control returns back to the main program after completing
the subroutine.
Each interrupt is associated with a vector address.
Formula to calculate vector address is:
Vector Address = Interrupt Number x 8
For RST2, vector address = 2 x 8 = 16D = 10H

Software Interrupts
Instruction Address of ISR
RST0 8x0 = 0000H
RST1 8x1 = 0008H
RST2 8x2 = 0010H
RST3 8x3 = 0018H
RST4 8x4 = 0020H
RST5 8x5 = 0028H
RST6 8x6 = 0030H
RST7 8x7 = 0038H

Software Interrupts
Interrupt Service Routine (ISR)
Main Program
0020H -----
0020H -----
X
5000H .
RST4
.
5001H Y
.
5002H 2030H -----
2031H RET

Hardware Interrupts
Interrupts that are activated by some peripheral devices by placing
appropriate signals at the interrupt pins of p.
Upon receiving of an interrupt signal, p completes the task it was currently
executing and transfer the program control to the specific ISR.
Upon completion of the ISR, p returns to the main program.
There are five hardware interrupts in 8085:
1. TRAP or RST4.5
2. RST7.5
3. RST6.5
4. RST5.5
5. INTR

Hardware Interrupts

Hardware Interrupts
TRAP/RST4.5
Only non-maskable interrupt.
Has the highest priority among all interrupts.
Vector address is 4.5x8 = 0024H.
Signal must make a LOW to HIGH transition and remain HIGH until
acknowledged, making it both edge and level triggering interrupt.
Two ways to clear TRAP interrupt:
1. Giving a low signal on RESETIN pin (external signal).
2. Giving a high TRAP ACKNOWLEDGE (internal signal)

Hardware Interrupts
RST7.5
Is a maskable interrupt.
Has second priority among all interrupt and the highest priority among all
maskable interrupts.
Vector address is: 7.5x8 = 003CH.
Triggered at the rising edge of the signal, making it edge triggering interrupt.

Hardware Interrupts
RST6.5 and RST5.5
Both are maskable interrupt.
Vector address are: 6.5x8 = 0034H and 5.5x8 = 002CH respectively.
Both are level triggering interrupt.

Hardware Interrupts
INTR
Is a maskable, level triggering interrupt with lowest priority.
Is the only Non-vectored interrupt.
The following sequence of events occurs when INTR signal goes high.
1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends active low
interrupt acknowledge signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic places an instruction
OPCODE on the data bus. In the case of multibyte instruction, additional interrupt
acknowledge machine cycles are generated by the 8085 to transfer the additional
bytes into the microprocessor.
4. On receiving the instruction, the 8085 saves the address of next instruction on stack
and execute received instruction.

Hardware Interrupts

Software Interrupts
Interrupt Trigger Priority Maskable Vector Address
TRAP Edge and Level 1st (Highest) No 0024H
RST7.5 Edge 2nd Yes 003CH
RST6.5 Level 3rd Yes 0034H
RST5.5 Level 4th Yes 002CH
INTR Level 5th (Lowest) Yes -

Knowledge is
?
having the right
answer.
Intelligence is
asking the right
question.

8085 Interrupts: Md. Asaduzzaman, 17114005 Sanjib Majumder, 17114001 Anuwarul Kabir, 17114008

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8085 Interrupts

Md. Asaduzzaman, 17114005

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

Non-maskable Interrupt - Interrupts whose request cannot be denied.

Interrupt Service Routine (ISR) - is a special block of code associated with a

Interrupt Vector - is the memory location of ISR.

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

MCSE 6003 : Microprocessor Design

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