3D IC Technology

3D IC Technology
Contents
Limits of 2D
3D-IC Benefits
3D-IC Technology
10 Jan 2017
LIMITS OF 2D
10 Jan 2017
Limits of 2D
1D gate to 3D gate
MOS devices start 3D in 22 nm technology
High K Metal
Gate to increase
field effect
Current
drive
(mA/m)
2.0
Tri-Gate for
increasing drive
current and
reducing leakage
Strain to
increase mobility
1.5
Gate
material
1.0
Strain
0.5
0.0
130 nm
90 nm
65 nm
45 nm
32 nm
Technology node
4
10 Jan 2017
22 nm
17 nm
Limits of 2D
Giga-device to its limits

Technology
130nm
90nm
100M
250M
2006
2D
2.5D
3D
32nm
22nm
5nm
500M
2G
7G
150 G
2008
2010
45nm
Complexity
Packaging
200
4
Core+
Embedded Core+
DSP
DSP
blocks
11Mb
Mb
Mem
Mem
Core
Core
DSPs
DSPs
10
10Mb
Mb
Mem
Mem
Dual
Dualcore
core
Dual
DSP
Dual DSP
RF
RF
Graphic
Graphic
Process.
Process.
100
100Mb
Mb
Mem
Mem
Sensors
Sensors
2012
Quad
QuadCore
Core
Quad
DSP
Quad DSP
3D
3DImage
ImageProc
Proc
Crypto
Cryptoprocessor
processor
Reconf
ReconfFPGA,
FPGA,
Multi
MultiRF
RF
11Gb
Memories
Gb Memories
Multi-sensors
Multi-sensors
2020
??
Limits of 2D
Needs for improved protection, but noise margins reduced

500 mV
100 mV
Supply (V) margin
margin
5.0
3.3
I/O supply
2.5
1.8
1.2
1.0
Core supply
0.5 0.35 0.18 130n 90n 65n 45n 32n 22n 17n
Technology
Adapted from ITRS roadmap for semiconductors, 2011
6
10 Jan 2017
Limits of 2D
Needs for improved reliability but

reduced operating windows
IESD
Destruction
IEMC
Thermal stress
IC operation
area
Safe ESD
protection
window
IC Reliability
constraints
VESD
VEMC
IC linear
susceptibility
IC non-linear
susceptibility
Adapted from Lowering Component Level HBM/MM

ESD Specifications and Requirements, Industry Council
on ESD Target Levels, White Paper 2007
7
10 Jan 2017
IC
vulnerability
3D-IC BENEFITS
10 Jan 2017
3D-IC Benefits
Evolutionary
and revolutionary
interconnect
technologies are
needed to
enable migration
to 3D
ITRS 2009 - The next Step in Assembly and Packaging:

System Level Integration in the package, white paper
10 Jan 2017
3D-IC Benefits
Georgia-Tech vision of SoC
From Georgia Tech 3D system packaging research

http://www.prc.gatech.edu.
10
10 Jan 2017
3D-IC Benefits
The integration of 3D technologies will enable performances, form factor and

cost requirements of the next generation of electronic devices
From 3DIC & TSV Report Cost, Technologies & Markets,

2007, Yole Dev.
11
10 Jan 2017
3D-IC Benefits
One new piece in the puzzle
From 3DIC & TSV

Report Cost,
Technologies &
Markets, 2007,
Yole Dev.
12
10 Jan 2017
3D-IC Benefits
3D Packaging contributes to More than

Moore at a reasonable price
2008 : Why 3D?
2010 How 3D?
2012 : When 3D?

20xx : Why 2D?
From ITRS 2011 Executive
Summary, and Yole Dev.
13
10 Jan 2017
3D-IC Benefits
3D technology enables the integration of ICs fabricated in different

technologies
4m vias
CMOS, CCD, SOI, Sensor
Bosch process
0.18m SOI
0.35 m SOI
B. Aull, et. al., Laser Radar

Imager Based on 3D Integration
of Geiger-Mode Avalanche
Photodiodes IEEE SSCC 2006.
C. Bower, et. al., High Density Vertical Interconnects

for 3D Integration of Silicon ICs, 56th ECTC, San
Diego, 2006.
Sensor
14
10 Jan 2017
3D-IC Benefits
Improve electronic efficiency
3D minimizes interconnect parasitic effects

3D simplifies multiple supply voltage distribution
3D reduces package pin count
More uniform, high density power delivery
J. Lu, Monolithic 3D Power Delivery

Using Dc-Dc Converter, 3D
Architecture Conference, October,
2006, Burlingame, CA.
15
10 Jan 2017
3D-IC Benefits
A significant increase in bandwidth
2D
3D
Buffer
3-stage
1-stage
Pad Load
3-5 pF
1 pF
Interconnect
capa
5-20 pF
0.1-1 pF
Interconnect
inductance
5-30 nH
0.1-1 nH
Current drive 10-100 mA
1-10 mA
16
10 Jan 2017
3D-IC Benefits
A significant reduction in I/O complexity
Solder ball
ESD protection
Voltage
translation
and level
shifers
17
10 Jan 2017
3D-IC Benefits
A better power efficiency
Smaller wire-length distribution

Shorter wires decrease the
average load capacitance and
resistance and decrease the
number of repeaters needed for
long wires.
The reduced average interconnect
length in 3D IC, vs 2D IC, improves
the wire efficiency by 15-25 %
Active power may be reduced by
25-50%
T. Topol Three-dimensional integrated circuits , Ibm

Journal Research, 2006
18
"Implementing a 2-Gbs 1024-bit

-rate Low-Density ParityCheck Code Decoder in 3D-Ics
, Lili Zhou, ICCD 2007
10 Jan 2017
3D-IC Benefits
2.5D
ICs
The yield of a single 7-Billion CMOS die is too low

4 dies (1.7 B-device each) connected by transposer
The 4-die Virtex-7 reaches 7 Billion devices
19
10 Jan 2017
3D-IC Benefits
Tera-Hertz
computing
in 2015
From ITRS 2009 Assembly

and Packaging.
20
10 Jan 2017
3D-IC Benefits
Atlas photon detector at CERN
The HE physisict dream
High Energy Physics requires sophisticated

detectors
integrating sensors
readout electronics.
Review of 3D
Related
Technologies for
HEP, R. Yarema,
2007
21
10 Jan 2017
3D-IC TECHNOLOGY
22
10 Jan 2017
3D-IC Technology
Higher complexity at lower cost
Stacking of memories
12 chips, 840 m thickness
8 chips, 560 m thickness

23
10 Jan 2017
3D-IC Technology
Interposers
Based on silicon or glass

Replace traditional PCB
laminate or ceramic
technologies
Alternative to very large 2D ICs
at prohibitive costs
Very high density and
bandwidth
Bridge platform between 2D
and 3D
Pitch (m)
From Georgia Tech 3D system
packaging research
http://www.prc.gatech.edu.
From 3DIC & TSV Report Cost,
Technologies & Markets, 2007,
Yole Dev.
24
10 Jan 2017
3D-IC Technology
Direct
bond interconnect (DBI) using magic metal

R around 50 m
Review of 3D Related
Technologies for HEP R.
Yarema, 2007
Ziptronix, 3D Conference, Oct, 2007
25
10 Jan 2017
3D-IC Technology
Wire-Bond
vs. Through-Silicon-Via (TSV)
LOH, 3D
Stacked
Microprocessor:
Are We There
Yet? , IEEE
Micro, 2010
A. Chambers, ThroughWafer Via Etching,

Advanced Packaging,
April 2005
26
10 Jan 2017
3D-IC Technology
Source:
Yole
Dev.
27
10 Jan 2017
3D-IC Technology
Terrazon with super contact
28
10 Jan 2017
3D-IC Technology
Process offered by CMC, CMP

and MOSIS
Terrazon with 2 flip chips
29
Jan 10, 2017
3D-IC Technology
IC design with Direct

Bond Interconnect (DBI)
From CMP annual users meeting, 3D-IC

Integration, January 20th 2011, PARIS
30
10 Jan 2017
3D-IC Technology
Via formation for die to wafer process
Development of 3D
Integrated Circuits for
HEP, R. Yarema
31
10 Jan 2017
3D-IC Technology
MIT Lincoln Labs

3D case study
R. Yarema,
Development of
3D Integrated
Circuits for
HEP, 12th LHC
Electronics
Workshop,
Valencia, Spain,
September 2529, 2006
32
10 Jan 2017
3D-IC Technology
Development of 3D
Integrated Circuits for
HEP, R. Yarema, 2006
3D IC Pixel Electronics,
the Next Challenge, R.
Yarema, 2008
33
10 Jan 2017

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3D IC Technology

MOS devices start 3D in 22 nm technology

Giga-device to its limits

Needs for improved protection, but noise margins reduced

Supply (V) margin

Needs for improved reliability but

Adapted from Lowering Component Level HBM/MM

ITRS 2009 - The next Step in Assembly and Packaging:

Georgia-Tech vision of SoC

From Georgia Tech 3D system packaging research

The integration of 3D technologies will enable performances, form factor and

From 3DIC & TSV Report Cost, Technologies & Markets,

One new piece in the puzzle

From 3DIC & TSV

3D Packaging contributes to More than

3D technology enables the integration of ICs fabricated in different

CMOS, CCD, SOI, Sensor

B. Aull, et. al., Laser Radar

C. Bower, et. al., High Density Vertical Interconnects

Improve electronic efficiency

3D minimizes interconnect parasitic effects

J. Lu, Monolithic 3D Power Delivery

A significant increase in bandwidth

Current drive 10-100 mA

A significant reduction in I/O complexity

A better power efficiency

Smaller wire-length distribution

T. Topol Three-dimensional integrated circuits , Ibm

"Implementing a 2-Gbs 1024-bit

The yield of a single 7-Billion CMOS die is too low

From ITRS 2009 Assembly

Atlas photon detector at CERN

The HE physisict dream

High Energy Physics requires sophisticated

Higher complexity at lower cost

12 chips, 840 m thickness

8 chips, 560 m thickness

Based on silicon or glass

bond interconnect (DBI) using magic metal

Ziptronix, 3D Conference, Oct, 2007

vs. Through-Silicon-Via (TSV)

A. Chambers, ThroughWafer Via Etching,

Terrazon with super contact

Process offered by CMC, CMP

Terrazon with 2 flip chips

Jan 10, 2017

IC design with Direct

From CMP annual users meeting, 3D-IC

Via formation for die to wafer process

MIT Lincoln Labs

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