Chapter 5 Synchronous Sequential Circuit

ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
Prepared by
S.Senthurpriya, AP/ECE
0
Analysis of Clocked Sequential Circuits

The State
State = Values of all Flip-Flops
x
Example AB=00
Q Q
D CLK
Q Q

State Equations
x
A(t+1) = DA = A(t) x(t)+B(t) x(t) =Ax+Bx
Q Q
Q Q
B(t+1) = DB = A(t) x(t)
CLK
= A x
y(t) = [A(t)+ B(t)] x(t) = (A + B) x

State Table (Transition Table)
Present Input State Next State
x
Output
Q Q
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1 t
x 0 1 0 1 0 1 0 1
A 0 0 0 1 0 1 0 1 t+1
B 0 1 0 1 0 0 0 0
y 0 0 1 0 1 0 1 0 t
D CLK
Q Q
A(t+1) = A x + B x
B(t+1) = A x y(t) = (A + B) x
3

State Table (Transition Table)
x
Present State
Next State Output x=0 x=1 x=0 x=1
Q Q
A 0 0 1 1
B 0 1 0 1
A 0 0 0 0
B 0 0 0 0
A 0 1 1 1
B 1 1 0 0
y 0 1 1 1 t
y 0 0 0 0
D CLK
Q Q
t+1
A(t+1) = A x + B x
B(t+1) = A x y(t) = (A + B) x
4

State Diagram
AB
Present State Next State x=0 x=1 Output x=0 x=1
input/output
1/0 0/1
10
A B 0 0
A B A B 0 0 0 1
y 0
y 0
0/0
00
0 1
1 0 1 1
0
0 0
0
0 0
1
1 1
1
0 0
1
1 1
0
0 0
0/1 1/0
01
Q Q
0/1
11
1/0
D CLK
Q Q
1/0

D Flip-Flops
Example:
Present Input State Next State
x y
CLK
Q
Q
A 0 0 0 0 1 1 1 1
x 0 0 1 1 0 0 1 1
y 0 1 0 1 0 1 0 1
A 0 1 1 0 1 0 0 1
A(t+1) = DA = A x y
01,10 00,11
0
01,10
00,11

JK Flip-Flops
J x K Q Q A
Example:
Present Next I/P State State A B x A B 0 0 0 0 1 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 Flip-Flop Inputs JA KA JB KB 0 0 1 0
J K CLK
Q Q
0
1 1 1 1 0 1
0
1 0 1 0 0 1
0
1 1 0
0
1 0 0
0
1 0 1
1
0 1 1
JA = B JB = x
KA = B x KB = A x
0
1 1
0
1 0
0
1 0
0
1 0
A(t+1) = JA QA + KA QA = AB + AB + Ax B(t+1) = JB QB + KB QB = Bx + ABx + ABx

7

JK Flip-Flops
J x K Q Q A
Example:
Present Next I/P State State A B x A B 0 0 0 0 1 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 Flip-Flop Inputs JA KA JB KB 0 0 1 0
J K CLK
Q Q
0
1 1 1 1 0 1
0
1 0 1 0 0 1
0
1 1 0
0
1 0 0
0
1 0 1
1
0 1 1
1
00
0
11
0
01
0
10
0
1 1
0
1 0
0
1 0
0
1 0
1
8

T Flip-Flops
x T Q R Q A y
Example:
Present Next F.F I/P O/P State State Inputs A B x A B TA TB y 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 0 0 1 0 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 0 0 1 0 0 0 0 0 1 1
T
Q B R Q
CLK
Reset
TA = B x y =AB
TB = x
0
0 1
1
0 1
A(t+1) = TA QA + TA QA = AB + Ax + ABx B(t+1) = TB QB + TB QB =xB

T Flip-Flops
x T Q R Q A y
Example:
Present Next F.F I/P O/P State State Inputs A B x A B TA TB y 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 0 0 1 0 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 0 0 1 0 0 0 0 0 1 1
T
Q B R Q
CLK
Reset
0/0
00
0/0
1/0
01
0
0 1
1
0 1
1/1
11 10
1/0 1/0 0/0

10
0/1
Mealy and Moore Models

The Mealy model: the outputs are functions of both the present state and inputs (Fig. 5-15).
The outputs may change if the inputs change during the clock pulse period.
The outputs may have momentary false values unless the inputs are synchronized with the clocks.
The Moore model: the outputs are functions of the present state only (Fig. 5-20).
The outputs are synchronous with the clocks.
11
Fig. 5.21 Block diagram of Mealy and Moore state machine

12

Mealy
Present State A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 I/P x 0 1 0 1 0 1 0 1 Next O/P State A B y 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0
Moore
Present State A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 I/P x 0 1 0 1 0 1 0 1 Next O/P State A B y 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1
For the same state, the output changes with the input
For the same state, the output does not change with the input
13
Moore State Diagram

State / Output
0 1 00/0 01/0 0
1
11/1
1
10/0
1
0 0
14
State Reduction and Assignment

State Reduction Reductions on the number of flip-flops and the number of gates.
A reduction in the number of states may result in a reduction in the number of flip-flops. An example state diagram showing in Fig. 5.25.
Fig. 5.25 State diagram

15
State Reduction
State: a a b c d e f f g f g a Input: 0 1 0 1 0 1 1 0 1 0 0
Output:
0 0 0 0 0 1 1 0 1 0 0
Only the input-output sequences are important.
Two circuits are equivalent

Have identical outputs for all input sequences; The number of states is not important.
Fig. 5.25 State diagram
16
Equivalent states
Two states are said to be equivalent
For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state. One of them can be removed.
17
Reducing the state table

e = g (remove g); d = f (remove f);
18
The reduced finite state machine
State: a a b c d e d d e d e a Input: 0 1 0 1 0 1 1 0 1 0 0
Output: 0 0 0 0 0 1 1 0 1 0 0
19
The checking of each pair of states for possible equivalence can be done systematically using Implication Table. The unused states are treated as don't-care condition fewer combinational gates.
Fig. 5.26 Reduced State diagram

20
Design Procedure
Design Procedure for sequential circuit
The word description of the circuit behavior to get a state diagram;
State reduction if necessary;

Assign binary values to the states; Obtain the binary-coded state table; Choose the type of flip-flops; Derive the simplified flip-flop input equations and output equations; Draw the logic diagram;
21
Design of Clocked Sequential Circuits

Example: Detect 3 or more consecutive 1s
0 S0 / 0
0 1
S1 / 0 1
State A B S0 0 0 S1 0 1 S2 1 0 1 1 S3
0 S3 / 1 S2 / 0 1
22

Present Input State Next State Output
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1
A 0 0 0 1 0 1 0 1
B 0 1 0 0 0 1 0 1
y 0 0 0 0 0 0 1 1
0
S0 / 0
1 S1 / 0
0
0 0 1
S3 / 1 1
S2 / 0
1
23

Present Input State Next State Output
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1
A 0 0 0 1 0 1 0 1
B 0 1 0 0 0 1 0 1
y 0 0 0 0 0 0 1 1
Synthesis using D Flip-Flops
A(t+1) = DA (A, B, x)
= (3, 5, 7)
B(t+1) = DB (A, B, x) = (1, 5, 7) y (A, B, x) = (6, 7)
24
Design of Clocked Sequential Circuits with D F.F.

DA (A, B, x) = (3, 5, 7) = Ax + B x DB (A, B, x) = (1, 5, 7) = A x + B x
B 0 0 1 0 A 0 1 1 0 x B 0 1 0 0 A 0 1 1 0 x
y (A, B, x) = (6, 7)
=AB
B 0 0 0 0
A 0 0 1 1 x
25
Design of Clocked Sequential Circuits with D F.F.

DA = A x + B x DB = A x + B x y =AB
D CLK x D Q Q y A
Q Q
26
Flip-Flop Excitation Tables

Present Next State State F.F. Input Present Next State State F.F. Input
Q(t) Q(t+1) 0 0 0 1 1 0 1 1
D 0 1 0 1
Q(t) Q(t+1) 0 0 0 1 1 0 1 1 Q(t) Q(t+1) 0 0 0 1 1 0 1 1
J 0 1 x x T 0 1 1 0
K x x 1 0
0 0 (No change) 0 1 (Reset) 1 0 (Set) 1 1 (Toggle) 0 1 (Reset) 1 1 (Toggle) 0 0 (No change) 1 0 (Set)
27
Design of Clocked Sequential Circuits with JK F.F.

Present Input State Next State Flip-Flop Inputs
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1
A 0 0 0 1 0 1 0 1
B JA 0 0 1 0 0 0 0 1 0 x 1 x 0 x 1 x
KA x x x x 1 0 1 0
JB KB 0 x 1 x x 1 x 1 0 x 1 x x 1 x 0
Synthesis using JK F.F.
JA (A, B, x) = (3) dJA (A, B, x) = (4,5,6,7) KA (A, B, x) = (4, 6) dKA (A, B, x) = (0,1,2,3) JB (A, B, x) = (1, 5) dJB (A, B, x) = (2,3,6,7) KB (A, B, x) = (2, 3, 6) dKB (A, B, x) = (0,1,4,5)
28
Design of Clocked Sequential Circuits with JK F.F.

Synthesis using JK Flip-Flops
JA = B x
JB = x
KA = x
KB = A + x
J Q Q A y K
B 0 0 1 0 A x x x x x B 0 1 x x A 0 1 x x x
B x x x x A 1 0 0 1 x B x x 1 1 A x x 0 1 x
J K CLK
Q Q
29
Design of Clocked Sequential Circuits with T F.F.

Present Input State Next State F.F. Input
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1
A 0 0 0 1 0 1 0 1
B 0 1 0 0 0 1 0 1
TA 0 0 0 1 1 0 1 0
TB 0 1 1 1 0 1 1 0
Synthesis using T Flip-Flops TA (A, B, x) = (3, 4, 6) TB (A, B, x) = (1, 2, 3, 5, 6)
30
Design of Clocked Sequential Circuits with T F.F.

Synthesis using T Flip-Flops
TA = A x + A B x TB = A B + B x
B 0 0 1 0 A 1 0 0 1 x B 0 1 1 1 A 0 1 0 1 x
Q x T Q Q A y
CLK
31

Chapter 5 Synchronous Sequential Circuit

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ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS

Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits

A(t+1) = DA = A(t) x(t)+B(t) x(t) =Ax+Bx

B(t+1) = DB = A(t) x(t)

Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits

Next State Output x=0 x=1 x=0 x=1

Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits

A(t+1) = JA QA + KA QA = AB + AB + Ax B(t+1) = JB QB + KB QB = Bx + ABx + ABx

Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits

A(t+1) = TA QA + TA QA = AB + Ax + ABx B(t+1) = TB QB + TB QB =xB

Analysis of Clocked Sequential Circuits

1/0 1/0 0/0

Mealy and Moore Models

Mealy and Moore Models

Fig. 5.21 Block diagram of Mealy and Moore state machine

Mealy and Moore Models

Moore State Diagram

State Reduction and Assignment

Fig. 5.25 State diagram

Only the input-output sequences are important.

Two circuits are equivalent

Reducing the state table

The reduced finite state machine

Fig. 5.26 Reduced State diagram

State reduction if necessary;

Design of Clocked Sequential Circuits

Design of Clocked Sequential Circuits

Design of Clocked Sequential Circuits

Synthesis using D Flip-Flops

Design of Clocked Sequential Circuits with D F.F.

DA (A, B, x) = (3, 5, 7) = Ax + B x DB (A, B, x) = (1, 5, 7) = A x + B x

Design of Clocked Sequential Circuits with D F.F.

Flip-Flop Excitation Tables

Q(t) Q(t+1) 0 0 0 1 1 0 1 1 Q(t) Q(t+1) 0 0 0 1 1 0 1 1

Design of Clocked Sequential Circuits with JK F.F.

Synthesis using JK F.F.

Design of Clocked Sequential Circuits with JK F.F.

Design of Clocked Sequential Circuits with T F.F.

Synthesis using T Flip-Flops TA (A, B, x) = (3, 4, 6) TB (A, B, x) = (1, 2, 3, 5, 6)

Design of Clocked Sequential Circuits with T F.F.

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