ECE-309E Microelectronics: Crystal Growth & Wafer Preparation

ECE-309E Microelectronics
ECE, UIET, KUK-2010

ECE-309E
Microelectronics
Crystal Growth & Wafer
Preparation

ECE, UIET, KUK-2010

Why Silicon
Silicon is the most important semiconductor for the
microelectronics industry. When compared to germanium,
silicon excels for the following reasons:
(1) Si has a larger bandgap (1.1 eV for Si versus 0.66 eV for
Ge).
(2) Si devices can operate at a higher temperature (150
o
C vs
100
o
C).
(3) Intrinsic resistivity is higher (2.3 x 10
5
-cm vs 47 -
cm).
(4) SiO
2
is more stable than GeO
2
which is also water soluble.
(5) Si is less costly.
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Crystal Growth
Shaping
Wafer Slicing
Wafer Lapping
and Edge Grind
Etching
Polishing
Cleaning
Inspection
Packaging
Basic Process Steps for Wafer
Preparation
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Crystal Growth
Czochralski Crystal Growth(CZ)
Wafer Fabrication
Melt Doping
Float Zone refinement
Epitaxy

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Si Wafer Fabrication
Raw Material -Quartzite
Polycrystalline Silicon
Single Crystal Silicon
Wafer
Distillation and
Reduction
Crystal Growth
Grind, Saw, Polish
1
2
3
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Sand to Silicon
The sand that is used to produce silicon wafers is
compose of mainly silicon dioxide. This can be
made to react with carbon at very high temperatures.
The silicon oxygen bond is very strong so a very
high temperature process is needed for this carbon
reducing reaction.
The carbon replaces silicon to form silicon and
carbon monoxide and carbon dioxide.
This process is carried out in sub-merged electrode
arc furnace

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Production of MGS Silicon
MGS-major impurities are B and C
Submerged electrode arc
furnace is a power intensive
process (13kWh/kg.
Used to produce metal alloys
Purity 98%
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Metallurgical Grade Silicon
This process generates polycrystalline silicon with
about 98% to 99% purity and is called crude
silicon or metallurgical grade silicon (MGS).

Crude silicon has a very high impurity
concentration and so needs further refining for use
in the semiconductor industry.

CO Si C SiO
Heat
2 2
2
+ +
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Production of EGS Silicon
-Requires doping element ~ppb, C< 2ppm
Purification of silicon has several steps. First the crude silicon is ground into a fine
powder. The powder is then fed into a reactor along with HCL vapour. At ~300C
trichlorosilane (TCS, SiHCL
3
) is produced.

This TCS vapour is then put through a series of filters, condensers and purifiers to
produce ultra high purity TCS liquid.

At high temperature TCS can react with hydrogen to produce high purity
polysilicon.

This high purity polysilicon is called Electronics Grade Silicon (EGS)
and is ready for processing into a single crystal ingot.
2 3
) 300 (
3 H SiHCL HCL Si
C Heat
+ +

HCL Si H SiHCL
C Heat
3
) 1100 (
2 3
+ +

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Si epi reactor chlorosilane chemistry:

SiCl
4
(gas)+H
2
(gas) SiHCl
3
(gas)+HCl(gas)

SiHCl
3
(gas)+H
2
(gas) SiH
2
Cl
2
(gas)+HCl(gas)

SiH
2
Cl
2
(gas) SiCl
2
(gas)+H
2
(gas)

SiHCl
3
(gas) SiCl
2
(gas)+HCl(gas)

SiCl
2
(gas)+H
2
(gas) Si(solid)+2HCl(gas)

For silane it is not reversible:

SiH
4
Si(solid)+2H
2
(gas)
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CVD Reactor for EGS
Temp-1100C
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Polycrystalline - Single Crystal Si
Crushed high-purity polycrystalline silicon is
doped with elements like arsenic, boron,
phosphorous or antimony and melted at 1400
in a quartz crucible surrounded by an inert gas
atmosphere of high-purity argon.
The melt is cooled to a precise temperature,
then a "seed" of single crystal silicon is placed
into the melt and slowly rotated as it is
"pulled" out.
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Crystal Growth
Two things are necessary to turn the EGS into a single crystal ingot,
these are:
1. High Temperature
2. Single Crystal Silicon Seed
With these two items, molten silicon is produced that can be made to
condense with the same crystal structure as the seed silicon.
There are two methods commonly used to produce single crystal
silicon:
1. The Czochralski Method (CZ)
2. The Floating Zone method (FZ)
Since only the CZ method can be used to make wafers with diameter
greater than 200mm and it is a relatively low cost process, it is the
most popular production method.
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Crystal Puller
Cross Sectional
Diagram
Czochralski
Crystal Growth
(CZ)
Pull Rate: 10-50 m/sec
Spin Rate: 1-3 rpm
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Si Crystal Puller for
300 mm Wafers
Note Size
of Person
Czochralski Crystal Growth
(CZ)
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Czochralski (CZ) crystal growing
All Si wafers come
from Czochralski
grown crystals.
The diameter of
the silicon ingot
produced can be
controlled by the
temperature and
pull rate.
The grooves on the
side of the ingot
are a caused by
changes in the
pulling rate of the
crystal.
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Czochralski (CZ) crystal growing
Here the high purity EGS is melted in a slowly rotating quartz
crucible at 1415C (just above the melting point of silicon 1414C).

A single crystal silicon seed rod is then mounted on a slowly rotating
chuck and lowered into the molten silicon.

The surface of the crystal begins to melt when it is submerged,
however the seed crystal temperature is precisely controlled to be just
below that of molten silicon.

When the system reaches thermal stability the seed crystal is
withdrawn very slowly, dragging some molten silicon to recondense
around it (with the same crystal orientation).
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Creating the Single Crystalline I ngot
(cont.)
The surface tension between the seed and the
molten silicon causes a small amount of the
liquid to rise with the seed and cool into a
single crystalline ingot with the same
orientation as the seed.
The ingot diameter is determined by a
combination of temperature and extraction
speed.

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Silicon Ingot Grown by CZ
Method
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Crystal Growing Theory (CZ)
L(dm/dt) +k
l
(dT/dx
1
)A
1
=k
s

(dT/dx2)A
2
k
l
and k
s
are thermal
conductivities,
A
1
and A
2
are area of isotherm at
1 and 2.
Max. growth rate can be deduced
under no thermal gradient in the
melt i.e. dT/dx
1
=0
Converting the mass solidification
rate to a growth rate using density
and area yeilds
V
max.=(
k
s
/Ld)(dT/dx), where V
max.
is max. pull rate, where d is the
density of solid silicon.

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Crystal Growth Theory (contd.)
Pull rate(net solidification rate), 30-
50% slower than theoretical
value(5.4mm/min).
Growth rate(instantaneous
solidification rate) can exceed pull rate
or be +Ve or Ve.
Growth rate influences defect the
defect structure & dopant distribution at
microscopic level.
Pull rate affects defects properties
due to condensation of thermal point
defects( above 950 C).
A pull rate above 2mm/min. eliminate
defects by quenching the point defects
in to lattice.
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Effect of solid solubility
C
s
& C
l
are equilibrium concentration of
impurity in solid & melt at interface, C
0
-initial
melt concentration, X- fraction of melt solidified,
and k
0
segregation coefficient.

K
e
=k
0
/{k
0
+(1-k
0
) exp(-VB/D)}is effective
segregation coefficient where V is growth velocity, D
diffusion coefficient of dopant in melt, B is
boundary/ stagnant layer thickness
K
0
=C
s
/C
l
(equilibrium segregation coefficient)
Concentration at tail end:?
Normal freezing relation
B=1.8D
1/3
V
1/6
W
-1/2
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Float-zone crystal growth
Molten silicon in float zone
is not contained in silica
crucibles thus not subject to
oxygen contaminations as
present in C-Z growth.

High resistivity (> 25 sqr-cm)
silicon are essentially grown
by this technique.
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Single-wafer epi reactor
Gasses: Trichlorosilane (SiHCl
3
), Dichlorosilane(SiH
2
Cl
3
)
Silane(SiH
4
)
SiH
4
Si(solid)+2H
2
(gas)

Epitaxial crystal growth
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Commercial Epi-reactor (Applied Materials)
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Molecular Beam Epitaxy (SiGe)
Similar for III-Vs or II-VIs
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Prof. Beans Si MBE Apparatus
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Defects in Crystals are classified by dimensionality
Class Dimension Types
Point 0 Instertial
Vacancy
Frenkel Pair
Line 1 Dislocations
Area 2 Surfaces, Twins, Stacking Faults,
GB
Volume 3 Precipitates, Voids
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Point Defects
Shottky Interstitial Frenkel Pair
Defect from Surface
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Schottky defects in thermal equilibrium
) / exp(
0
kT E N N
av v
=
N
v
= #lattice sites/cm
3
E
av
=activation energy~2.6 eV for Si
k= Boltzman constant
T= Temperature (K)
At room temp: N
v
~5x10
-12
/cm
3
1 hop in 10
4
sec
At 1000K N
v
~5x10
10
/cm
3
- 10
8
hops/sec

Defects frozen in when temp is lowered
i.e. crystal is not in equilibrium - # defects - large
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Other common point defects:

Interstitial extra atom not on lattice site
self-interstitial
interstitial dopants not usually active

Substitutional Impurities dopants

Frenkel Pair atom moves to nearby
interstitial site

Di-vacancy two adjacent missing atoms
only need to break 6 bonds
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Line defects
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ECE 663
One Dimensional Defects-Edge Dislocations
Positive edge dislocation extra half plane ABCD

Upper half compressive stress
Lower half - tensile stress
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ECE 663
Line Defects (1-D) Screw Dislocation
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ECE 663
Properties of Dislocations
Must end at surface or be closed curve
-dislocation loops

Impurities tend to migrate to dislocations
metallic impurities can short junctions

Effects carrier mobilities
- different or // to dislocations

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Area Defects
-Most important types:
Stacking Faults & Grain Boundaries, twin defects
-Can occur during epitaxy, implantation, and oxidation

Volume defects
-precipitates
-voids
-accumulations of point defects
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ECE 663
Properties of Dislocations
Must end at surface or be closed curve
-dislocation loops

Impurities tend to migrate to dislocations
metallic impurities can short junctions

Effects carrier mobilities
- different or // to dislocations

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Area Defects
-Most important type Stacking Faults
-Can occur during epitaxy, implantation,
and oxidation

Volume defects
-precipitates
-voids
-accumulations of point defects
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1. Reduce Contamination from environment

2. Wafer Cleaning

3. Gettering:
-try to trap impurities away from device
layers bad elements generally fast diffusers
-chemical bonds
-create crystal defects on purpose
Reduction of Impurities that Effect
Device Performance
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1. Free elements to be gettered from current
trapping sites

2. Diffuse to gettering site(s)

3. Trap them where they wont harm
devices
Gettering:
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Gettering of Alkali ions near the surface
of the device

Remove ions from oxides (GOX and FOX)

Deposit PSG (phosphosilicate glass)

Na and K are fast diffusers and are trapped
in the PSG layer during high temp
processing

Gettering- contd.
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Extrinsic Gettering

Put defects on backside of wafer to trap
metallic impurities and alkali ions
e.g. Fe, Au, Cu & Na
+
, K
+

Ex: Polysilicon (lots of defects) applied to
backside of wafer metal impurities
trapped at dislocations
Gettering- contd.
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Oxygen incorporated in Si when grown
using the CZ process

Growth at >1400C results in super-saturation
when cooled to room temp, causing
precipitates of SiO
2
throughout the wafer

Create SiO
2
surface region for devices
1. Epitaxy usually free from O
2
2. Out-diffusion thermal process
Intrinsic Gettering:
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Gettering Strategies
SiO
2
precipitates
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Electrical Characterization
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Silicon Wafer Manufacture
Objectives
1. Review in detail the purification process for the
silicon
2. The CZ method of silicon ingot production
3. Discuss silicon wafer shaping
1. Sawing
2. Edge Shaping and Lapping
3. Wafer Etch
4. Polishing
4. Epitaxial silicon; purpose and process

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I ngot Characterization
Single Crystal Silicon ingots are
characterized by the orientation of
their silicon crystals. Before the
ingot is cut into wafers, one or two
flats are ground into the diameter
of the ingot to mark this
orientation.

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The ingot is then ground
down to the correct
diameter to ensure a uniform
surface and notched along
one side. This notch will be
used to determine the wafer
orientation when it is being
processed later on in the fab
Ingot Grinding / Flats making
Flat grind
Diameter
grind
Notched grind
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Wafer Orientation
Plane of wafer is orientation
100 most common for Si VLSI
For Wafers 6 or less orientation and doping
Indicated by flats:
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Wafer Saw
The ingot is then sliced using a very fine diamond
saw or some steel wire.

The dominant state of the art slicing
technology is Multi-Wire Sawing (MWS).
Here, a thin wire is arranged over
cylindrical spools so that hundreds of
parallel wire segments simultaneously
travel through the ingot. While the saw
as a whole slowly moves through the
ingot, the individual wire segments
conduct a translational motion always
bringing fresh wire into contact with the
Silicon. The sawing effect is actually
achieved by SiC or other grinding agents
that run along the rotating wire.
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The wafers are sawn as thin as is possible
however they need to be thick enough to sustain
the mechanical handling of wafer processing.
Larger diameter wafers require a larger
thickness.
Given that wafers are generally processed in
batches of 25, the weight of a lot box of 300mm
is quite substantial !!!! (~3.2Kg)
Wafer Size (mm) Final Thickness (m) Area (cm
2
) Weight(g)
50.8 279 20.26 1.32
76.2 381 45.61 4.05
100 525 78.65 9.67
125 625 112.72 17.87
150 675 176.72 27.82
200 725 314.16 52.98
300 775 706.21 127.62
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Wafer Lapping
After the sawing processing the wafer edges are ground in a
mechanical process to round the sharp edges created through the
slicing process.
The round edges prevent chipping of the wafers in later processes.

After edge rounding the wafers are then rough polished to remove
most of the damage caused by the wafer sawing process.
This is known as lapping and is a double sided process performed
under pressure using a glycerine slurry with alumina (Al
2
O
3
) particles
suspended in it.

The lapping process removes about 50m of silicon from both sides of
the wafers but gives a flatness of ~2m across the wafer.
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Wafer Etch/Clean
After Sawing and Lapping the wafers are etched in a solution of nitric,
hydrofluoric and acetic acid.
The nitric acid oxides the silicon to form silicon dioxide on the
surface of the wafer, which the HF then dissolves and removes.
The acetic acid helps to control the reaction rate.

This etch of the wafer surface removes about 10m of silicon from
both sides of the wafer, but it helps to further smooth the surface of
the wafer while removing particles and defects from the wafers.

O H NO SiF H HF HNO Si
2 6 2 3
8 4 3 6 4 3 + + + +
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Wafer Polishing
A process called chemical mechanical polishing (CMP) is performed on the
wafers to improve their planarity and ensure that all the wafers are of the same
thickness.

Here the wafer is held in a rotating holder and pressed onto a rotating polishing
pad. Slurry and water are added to create an abrasive medium which slowly and
evenly grinds and smoothes down the surface of the wafer.

The slurry used is typically silica particles in a sodium hydroxide solution
(NaOH).
The particles have diameters of less than 100 so that scratches and gouges are
not an issue.

After polishing the wafers are cleaned using a mixture of HCL, H
2
O
2
and H
2
SO
4

to ensure the surface is contaminant free.
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Wafer polishing
Next, the wafers are
polished in a series of
combination chemical and
mechanical polish
processes called CMP
The wafers are held in a
hard ceramic chuck using
either wax bond or vacuum
and buffed with a slurry of
silica powder, RO/DI
Water and Sodium
hydroxide

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Wafer Cleaning
Most wafer manufacturers use a 3-step process
which starts with an SC1 solution (ammonia,
hydrogen peroxide and RO/DI water ) to remove
organic impurities and particles from the wafer
surface.
Next, natural oxides and metal impurities are
removed with hydrofluoric acid.
Finally, the SC2 solution, (hydrofluoric acid and
hydrogen peroxide), causes super clean new natural
oxides to grow on the surface.

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Wafer Thickness and Roughness Changes
After the CMP process the wafers are ready to ship to
customers.
The table below shows the changes in wafer thickness
and roughness through the various processes.
Procedure Thickness (m) Roughness (m)
Post Wafer Saw 914 76
Post Edge Rounding 914 76
Post Lapping 814 12.5
Post Etch 750 <2.5
Post CMP 725 Virtually defect free
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Crystal Planes denoted by
Miller I ndices h,k,l
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1. Determine where plane (or // plane) intersects axes:
a intersect is 2 units
b intersect is 2 units
c intersect is infinity (is // to c axis)
2. Take reciprocals of intersects in order
(1/2, 1/2, 1 / infinity) = (1/2, 1/2, 0)
3. Multiply by smallest number to make all integers
2 * (1/2, 1/2, 0) = " (1, 1, 0) plane"
a
b
c
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Equivalent planes denoted by {}
{100}=(100), (010), (001)
For Cubic structures:
[h,k,l] (h,k,l)
Crystal planes
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Angle Between Planes:

[h
1
k
1
l
1
] and [h
2
k
2
l
2
]
2
2
2
2
2
2
2
1
2
1
2
1
2 1 2 1 2 1
l k h l k h
l l k k h h
Cos
+ + + +
+ +
= u
Example: [100] and [111]
( )( ) 3
1
1 3
0 0 1
=
+ +
= u Cos
u=54.74
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Anisotropic Etching
KOH a crystallographically selective etch for
Si different planes etch at different rates
Surface atom densities different

Etch rate for [100] is 10 to 40 times higher than
For [111] depends on temperature
Si
SiO
2
(100) Wafer
[100]
V-groove very useful for MEMS
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Questions?
Textbooks :
1. VLSI Technology , Second Edition, By: S.M. Sze
2.VLSI Fabrication Principles, By S.K.Gandi

Other Useful Reference Material:
1. VLSI Technology by C.Y. Chang, McGraw-Hill Education, ISBN 0071141057(0-
07114105-7
2. Semiconductor Devices: Physics and Technology, S.M. Sze (2002)
3. Complete Guide to Semiconductor Devices 2
nd
ed., K.K. Ng (2002)

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