Science in China Series E: Technological Sciences

2009
SCIENCE IN CHINA PRESS

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Springer

A process study of electron beam nano-lithography and deep etching with an ICP system
LI QunQing, ZHANG LiHui, CHEN Mo & FAN ShouShan
Department of Physics and Tsinghua-Foxconn Nanotechnology Research Center, Tsinghua University, Beijing 100084, China

A systemic process study on an electron beam nanolithography system operating at 100 kV was present. The exposure conditions were optimized for resist ZEP520A. Grating structures with line/space of 50 nm/50 nm were obtained in a reasonably thick resist which is beneficial to the subsequent pattern transfer technique. The ICP etching process conditions was optimized. The role of etching parameters such as source power, gas pressure, and gas flow rate on the etching result was also discussed. A grating structure with line widths as small as 100 nm, duty cycles of 0.5, depth of 900 nm, and the side-wall scalloping as small as 5 nm on a silicon substrate was obtained. The silicon deep etching technique for structure sizes smaller than 100 nm is very important for the fabrication of nano-optical devices working in the visible regime.
electron beam lithography, ZEP520A resist, reactive ion etching, nanofabrication

1 Introduction
With the increasing integration of microelectronics, micro- and nano-fabrication techniques have developed quickly. The improved techniques enable the realization of nanoscale structures, making nano-optics a promising field of science. Lithographic techniques can break through the diffraction limit and produce structures smaller than the wavelength of visible light, so that the traditional micro-optics shift towards nano-optics and the subwavelength region. Advanced lithographic[1], etching, and film deposition techniques play important roles in nano-optics. There are several preconditions to realize a nanofabrication design. Nano-optical devices are primarily periodic or semi-periodic structures such as gratings (dense line structures), zone plates (ring structures), or photonic crystals (periodic pore structures). All these structures require high uniformity and error control over large areas. In addition, most nano-optical devices also imply high aspect ratio structures. All these requirements are fabrication challenges to both lithography and the subsequent pattern transfer techniques.

Subwavelength gratings are the typical structures in nano-optics. They are formed essentially by covering a surface area of several millimeters or more in length and 200 nm or less in width with dense lines that have a duty cycle (line width per period, DC) of 0.5 and are perpendicular to the long axis. Electron-beam (E-beam) lithography forms the essence of nanostructure fabrication at present because it offers benefits such as ease of control, high precision, and superior flexibility[2]. Currently, most laboratories use E-beam lithography techniques only to pattern small areas because of limitations due to system instability (caused by E-beam drift) and low exposure throughput. X-ray exposure techniques are widely used to fabricate complicated optical devices such as subwavelength gratings, but since X-ray techniques preclude generating patterns using the scanning method, they can only be used to replicate patterns. For X-ray exposure, the E-beam writer is still employed to fabricate the mask profile, which is usually a patterned
Received October 16, 2008; accepted March 2, 2009 doi: 10.1007/s11431-009-0156-7 Corresponding author (email: [email protected]) Supported by the National Basic Research Program of China (973 Program) (Grant No. 2007CB935301)

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metal film on a silicon substrate. Therefore, research on E-beam direct writing is still very important for the field of nanofabrication. Deep reactive ion etching of silicon has been used to fabricate microscale MEMS devices. However, when the trench width is on the order of several hundred nanometers, etching becomes difficult due to the high aspect ratio. To enhance anisotropic etching, inductive coupled plasma reactive ion etching (ICP) and the Bosch process were developed. A number of groups have reported silicon deep structures with feature sizes ranging from 200 nm to microns that were realized using ICP and the Bosch process[3 7]. The disadvantage of this process, however, is that after etching, the sidewall roughness of the trench is unacceptable and its width is usually enlarged. The results indicated that the degree of scalloping was approximately 20 nm with the Bosch process[8]. In this publication, we present a detailed study of the exposure process of an E-beam nanolithography system operating at 100 kV. The exposure conditions were optimized for dense structures and for the resist ZEP520A. High precision nano-grating structures were obtained using a reasonably thick resist (which is beneficial to the subsequent pattern transfer technique). We also performed a systematic study of the ICP etching process. A grating structure was obtained with a period of 200 nm and an aspect ratio of 9:1. The sidewall scalloping was as small as 5 nm on a silicon substrate.

lows: top coil RF power 250500 W; platen bias RF power 511 W; flow rate of etching gas SF6 20100 sccm; etching duration 26 s; flow rate of passivation gas C4F8 20100 sccm; passivation duration 211 s; and chamber pressure 0.61.0 Pa. The resist was removed by immersing in methyl ethyl ketone. We measured the E-beam resist thickness using an ellipsometer. After exposure and etching, an FEI Sirion200 field emission scanning electron microscope (SEM) was used to inspect the profile.

3 Study of the E-beam lithography process

3.1 E-beam lithography system A large accelerating voltage can be used to reduce the proximate effect, which arises from electrons scattering in the resist and from the reflection of electrons off the substrate. This technique is useful for fabricating ultra- fine micro- and nano-structures with high aspect ratios. The JBX-6300FS, which at 100 kV has the highest accelerating voltage, is a vector-scan type spot-beam E-beam lithography system equipped with a thermal field ZrO/W emitter electron gun and a 4-stage E-beam focusing system. The JBX-6300FS system offers benefits such as high efficiency and good stability, and it can work continuously for a long periods with guaranteed sample uniformity. It has two working modes: a high speed writing mode with the 4th lens, and nanometer mode with the 5th lens. Under both modes, the scanning rate can reach 12 MHz but the maximum field size is different for each mode. For example, at 100 kV, under the 4th lens mode, the JBX-6300FS has a maximum field size of 500 m 500 m, whereas under the 5th lens mode it has a maximum field size of 62.5 m 62.5 m. The respective beam addressing steps are 1 nm and 0.125 nm, respectively. During exposure, the beam addressing step (The minimum of which is limited by the scanning rate) is set as small as possible to obtain a smooth-edged pattern. Generally, the beam size determines the minimum line-width, which is typically at least 3 times the beam diameter[9]. The minimum beam diameter for this system is 2 nm, and we obtained 8 nm wide lines on 50 nm thick ZEP520A resist. This is also the minimum linewidth for the system. The beam size depends on the

2 Experimental conditions
We used a single-crystal silicon wafer as the substrate. The positive resist ZEP520A was spin-coated onto the substrate at a speed of 25007500 r/min for 60 s followed by a 120-s soft bake to remove the solvent from the resist. The exposure process was conducted using a 100 kV A JEOL JBX6300FS E-beam exposure system. The beam current was typically set at 100500 pA. The post exposure process included a 90-s ZED-N50 development step and a subsequent 30-s IPA rinse. Oxygen plasma treatment was used to descum the resist residue on the substrate to ensure the absence of resist on the exposed area. The silicon etch was carried out using an ICP etch system (Helicon etching system, Anelva) to perform a pattern transfer from the E-beam resist to the silicon substrate. The ranges of the ICP etch parameters used in the experiment were adjusted as fol1666

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beam current, the aperture, and the exposure mode. The exposure time is dictated by the beam current, the beam addressing step, etc. For this work, we considered all these factors to determine the beam current and the working mode. Figures 1(a) and (b) give the beam diameter dependence on beam current under two working modes. Under the 5th lens mode the minimum beam spot is 2 nm, achieved using a 25 m aperture, while under 4th lens mode the minimum beam spot is 6 nm, achieved using a 60 m aperture. We also found that these beam spot sizes were stable over a wide current range. 3.2 Study of the exposure process on the positive resist ZEP520A ZEP520A is a non-chemically amplified, positive Ebeam resist that offers high resolution[10]. The high sensitivity of ZEP520A reduces its exposure time by three times compared with that of PMMA[11,12]. The higher etch resistance allows us to transfer the ZEP520A resist pattern directly onto the substrate by dry etching. It is useful to study the exposure properties of ZEP520A for nanostructure fabrication. In studying E-

beam exposures, one finds that features of the fabricated pattern differ from that of the design pattern because of the proximate effect. To obtain the designed structure it is important to accurately control the E-beam deviation because this is closely related to pattern structure, pattern size, and exposure dose. This technology is called the E-beam exposure proximate effect geometric correction technology or dose correction technology. We performed numerous exposure experiments involving fabricating dense line arrays covering areas of 1 cm long by 100 nm wide with an line/space (L/S) of 1:1. The results indicated that the 330 nm thick resist, spun onto the substrate at 5500 r/min, was completely exposed only when the exposure dose reached 200 C/cm2. This dose is larger than that required in a 50 kV system, which is not surprising given that the higher voltage results in more highly penetrating electrons, leading to a reduced proximity effect[13]. For structures with other design line widths, both the minimum dose needed for complete exposure and the discrepancies between the exposed structure and the designed structure will vary (see Table 1). Using a reduced beam current (e.g., 100 pA), we found

Figure 1

The dependence of beam diameter on beam current. (a) 4th lens mode; (b) 5th lens mode.

Table 1 Actual line widths under different exposure doses for single lines and dense lines with different line widths, where indicates that pattern can not be exposed completely under this dose Designed line width (nm) 30 50 70 100 200 Structure single lines dense lines single lines dense lines single lines dense lines single lines dense lines single lines dense lines 200 122 120 220 208 240 90 128 118 240 225 Dose (C/cm2) 280 320 70 73 95 111 94 105 140 145 122 138 240 262 237 241 360 88 118 110 145 149 260 237 400 50 94 123 118 151 150 260 252

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a 20 nm discrepancy between the exposed and the designed structures, which is smaller than that using a 50 kV system[14], and this discrepancy increases with exposure dose. We also found that the range of acceptable exposure conditions was small, i.e., the process window is narrow for lines of less than 100 nm wide. If the exposure dose is too low, the exposed resist will not be completely dissolved by the developer, resulting in indiscernible graphics. On the other hand, a larger exposure dose leads to a reserved resist structure that is too narrow and easily collapses after developing,. For example, if we desire structures with an L/S of 70 nm/70 nm, the design size should be adjusted to an L/S of 50 nm/90 nm, and the exposure dose should be between 280 and 320 C/cm2. Figure 2 shows the variations in fabricated structures with increasing exposure dose. The experiments described below demonstrate that the minimum exposure doses needed for different design line widths change as a function of resist thickness. The results are illustrated in Table 2. For a given resist thickness there is a resolution limit that cannot be improved by modifying process parameters or by calibrating the exposure system. For example, using 330 nm thick ZEP520A resist, the minimum grating structure sizes that can be properly exposed are an L/S of 70 nm/70 nm under the 4th lens mode and an L/S of 50 nm/50 nm under the 5th lens mode, respectively. The only way to improve resolution is to use a thinner resist coating. According to the above results, design patterns will differ with target patterns. Hence, to obtain a dense line structure with an L/S of 90 nm/90 nm using 330 nm thick ZEP520A, the design structure is adjusted to

Figure 2 Exposed structures under different exposure doses for the designed pattern with L/S as 50 nm/90 nm.

an L/S of 70 nm/110 nm and the exposure dose set at 240 C/cm2. In Figure 3(a) we show an SEM crosssection image of an exposed grating resist structure with an L/S of 70 nm/70 nm in which exposure and development are both adequate and the structure sidewall is vertical. To get a grating structure with an L/S of 50 nm/50 nm (shown in Figure 3(b)), the design parameters must be adjusted to 30 nm/70 nm and 400 C/cm2. Figure 3(c) shows that it is difficult to obtain grating structures with an L/S of 50 nm/50 nm on 300 nm thick ZEP520A resist. High aspect ratio structures make correction of the

Table 2 The minimum exposure doses needed for single line and dense line with different line widths on different thickness resists and the actual line widths gotten under such exposure parameters. indicates that pattern cannot be exposed completely under this thickness Resist/Thickness 6500 rmin1/308 nm 5500 rmin1/330 nm 2500 rmin1/486 nm 7500 rmin1/285 nm Dose/Line-width 30 nm single lines L/S 30 nm/70 nm dense lines 50 nm single lines L/S 50 nm/90 nm dense lines 70 nm single lines L/S 70 nm/110 nm dense lines 100 nm single lines L/S 100 nm/140 nm dense lines 200 nm single lines L/S 200 nm/240 nm dense lines 340 C/52 nm (n-mode) 280 C/70 nm 240 C/60 nm 240 C/90 nm 240 C/90 nm 200 C/120 nm 200 C/107 nm 200 C/220 nm 200 C/220 nm 400 C/50 nm (n-mode) 280 C/75 nm 280 C/67 nm 240 C/90 nm 240 C/88 nm 200 C/120 nm 200 C/110 nm 200 C/220 nm 200 C/220 nm 400 C/50 nm (n-mode) 360 C/80 nm 280 C/70 nm 240 C/90 nm 240 C/90 nm 240 C/123 nm 240 C/120 nm 240 C/230 nm 240 C/225 nm 280 C/75 nm 280 C/70 nm 240 C/90 nm 240 C/90 nm 240 C/120 nm 240 C/120 nm 240 C/220 nm 240 C/220 nm

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Figure 3 E-beam exposure structures of ZEP520A fabricated by using optimized process parameters. (a) SEM cross-section image of a grating structure with L/S as 70/70 nm; (b) top SEM image of a grating structure with L/S as 50/50 nm; (c) too large exposure dose or too much pattern size adjustment made the pattern easy to collapse for high aspect ratio structure.

proximate effect technologically difficult. Slight variations in exposure parameters lead to results different from the target pattern for a 1:1 L/S and the pattern collapses easily.

4 Study of deep etching parameters with an ICP system

For this research, we adopted the ICP deep reactive ion etching (DRIE) technique to precisely transfer the exposure pattern to a silicon substrate. To obtain a high aspect ratio structure using the DRIE technique, a high etching rate and high selective ratio are necessary. The ICP system fulfills this requirement because it delivers a high density plasma and relatively low ion bombardment energy. In addition, the etching must be anisotropic to guarantee the verticality of the etching profile, otherwise the difference between the etched and design structures increases and the etching depth deepens. Because the DRIE process for silicon is essentially isotropic in nature, the side-wall must be protected by a polymer coating to prevent lateral etching by free radicals. The Bosch process addresses this demand by employing a sequential conversion between etching gas and passivation gas[15]. Although one can obtain structures with side-wall slope angles near 90 with this process, the side-wall becomes

scalloped due to the conversion between etching and passivation. As a result, the smoothing of the side-wall is not optimum with the Bosch process. For the ICP technique, the relevant parameters are etching and passivation gas flow, etching and passivation gas duration, chamber pressure, substrate platen bias RF power, top coil RF source power, and substrate temperature. For the research reported in this article, the substrate temperature was maintained at 0 and we investigated the effects of all the parameters except temperature on the etching quality. High coil RF power is widely used for micro-scale deep silicon etching because it facilitates the generation of high density plasma. However, we found that under high coil RF power the ZEP520A resist does not long withstand ion bombardment. Yet we also found that the low density plasma induced by low coil RF power renders the etching process slow and difficult. Upon experimentation, we found the optimum coil RF power to be 300 W. The influence of the platen bias RF power on the etching result is very apparent: Improper platen bias RF power results in poor trench morphology and side-wall verticality. Upon increasing the platen bias power the ion bombardment of the silicon substrate and the Ebeam resist increase, so that the discrepancy between the etching and the resist structures becomes large. However, when the platen bias power is decreased, the vertical ion velocity component is reduced so that the isotropic nature of the etching becomes apparent, resulting in a poor trench profile. After analyzing a series of experimental results, we found the optimum platen bias RF power to be 78 W. We distinctly observed the effect on etching of the chamber pressure. With increasing chamber pressure, the etching rate increases due to an increased plasma density. But a relatively large ion bombardment rate causes the trench morphology and the side-wall verticality to deteriorate and generates obvious lateral etching. Decreasing the chamber pressure reduces the selectivity and ion energy, which also results in an obvious lateral etching. Therefore, sub 100 nm trenches are unobtainable with improper chamber pressure. We found the optimum chamber pressure to be 0.8 Pa. After optimizing the three parameters just discussed, we found that etching and passivation gas flow and gas duration play the most significant role on side wall verticality and smoothness. Table 3 gives three typical
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Table 3 Etching parameters of nanoscale trench Recipe 1 2 3 Flow rate of SF6 (sccm) 100 20 20 Etching duration (s) 5 2 5 Flow rate of C4F8 (sccm) 100 20 50 Passivation duration (s) 11 4 6

process recipes based on a detailed study of these gas parameters. Gas flow rate and gas duration in Recipe 1 agree well with those found in the best recipe of micro-scale trench etching[8]. Figure 4 shows the etching result using Recipe 1. Good trench verticality with a side-wall slope angle of 90 was achieved, the etching rate reached 400 nm/min, and the sensitivity to ZEP520A was 6:1. However, a first problem with this recipe is that the lateral etching rate is as fast as 22 nm/min, which will enlarge the trench width. Consequently, the mask features will not be preserved. For example, to obtain a 2 micron deep trench we set the etching time to 5 min, resulting in a lateral extension that reached 110 nm. For this reason, the recipe can only be applied to structures with trench widths larger than 200 nm. The observed width extension in Figure 4 comes from lithography and etching. So a grating pattern with a 400 nm period and a duty cycle of 0.5 was achieved using an L/S of 100 nm/300 nm and 4 min etching time. The second problem with the recipe is the evident scalloping effect (see Figure 4). The scalloping value of 28 nm is unacceptable for some optical devices.

when the etching gas and passivation gas flow are simultaneously decreased, even if the passivation duration is increased. The trench width extension is obvious (It was enlarged from 80 to 180 nm within 5 min), and the side-wall smoothness became unacceptable. To optimize, we further increased the passivation gas flow and adjusted the etching and passivation duration simultaneously (Recipe 3), leading to the etching result shown in Figure 5(b). The trench width was enlarged from 80 to 100 nm within 5 min and the side-wall smoothness was improved, with scalloping at less than 5 nm. Compared with Recipe 1 we noted that the etching rate is decreased to 180 nm/min, but the selectivity is reduced to 4:1 for resist ZEP520A and lateral etching was only 20 nm within 5 min. More importantly, the advantage of this recipe is that the discrepancy between the resist structure and the silicon substrate structure is small during the

Figure 4 Etching structure achieved using recipe 1: 300 W top coil RF power, 8 W platen bias RF power, and 0.8 Pa chamber pressure (Despite obtaining a preferable duty cycle and vertical side wall, there is an obvious scalloping effect).

To address the two problems mentioned above, we first decreased the etching gas flow and etching duration (Recipe 2), giving the etching result shown in Figure 5(a). It is apparent that lateral etching cannot be restrained
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Figure 5 Experimental results when changing the recipes, with RF power as 300 W, flatten bias RF power as 8 W, and chamber pressure as 0.8 Pa. (a) The structure is not the desired one with Recipe 2; (b) perfect structure is achieved with Recipe 3 and the scalloping effect has been improved distinctly.

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transfer. Thus we obtained a silicon grating structure with a period of 200 nm, a DC of 1:1, and a depth of 900 nm by etching using an initial design pattern with an L/S of 60 nm/140 nm, which became an etched pattern with an L/S of 80 nm/120 nm after exposure. Relative to Recipe 1, Recipe 3 decreases the critical size of the pattern, making it possible to fabricate nano-optical devices adapted to the visible spectrum. However, we noted that ion bombardment of the E-beam resist due to the high density plasma cannot be ignored. Although lateral etching decreases using the optimized process parameters, it is not completely suppressed. In order to achieve high aspect ratio structures, the etching time is typically chosen to be at least 5 min. During this period, the lateral etching widens the trench that is targeted to be only tens of nanometers. Thus we cannot transfer the resist grating pattern with an L/S of 50 nm/50 nm to a silicon substrate using this deep etching technique. For grating periods less than 100 nm the pattern should first be transferred to a silicon dioxide or metal film, then this film is used as a mask to achieve deep silicon nano-gratings. Research in this area is undergoing.
1 Hohenau A, Ditlbacher H, Lamprecht B, et al. Electron beam lithography, a helpful tool for nanooptics. Microelectron Eng, 2006, 83(4-9): 14641467[DOI] 2 Liu M, Chen B Q, Wang Y X, et al. Fundamental technique of direct writing electron beam nano-lithography. Chin J Semicond, 2003, 24(Supp l): 226228 3 Ayon A A, Zhang X, Khanna R. Anisotropic silicon trenches 300 500 m deep employing time multiplexed deep etching (TMDE). Sens Actuators A, 2001, 91(3): 381385[DOI] 4 Ayazi F, Najafi K. High aspect-ratio combined poly and single-crystal silicon (HARPSS) MEMS technology. J Microelectromech Syst, 2000, 9(3): 288294[DOI] 5 McAuley S A, Ashraf H, Atabo L, et al. Silicon micromachining using a high-density plasma source: The future of technological plasmas. J Phys D, 2001, 34(18): 27692774[DOI] 6 Wang X D, Zeng W X, Lu G P, et al. High aspect ratio Bosch etching of sub-0.2 m trenches for hyperintegration applications. J Vac Sci Technol, 2007, B25(4): 13761381 7 Woldering L A, Tjerkstra R W, Jansen H V, et al. Periodic arrays of deep nanopores made in silicon with reactive ion etching and deep UV lithography. Nanotechnology, 2008, 19(14): 145304(111) [DOI]

5 Conclusion
We presented a systemic study of the fabrication of nanostructures with the integration of nanolithography processes on a 100 kV JBX-6300FS E-beam system and the ICP silicon deep etching technique. We discussed in detail the work on the exposure and etching processes employed for structures with dense lines. Well-rounded recipes were established for E-beam exposure and silicon deep etching processes with resist ZEP520A. We established geometric correction technology for the E-beam exposure proximate effect, in addition to lateral etching correction technology. Through careful optimization of the process parameters, grating structures with an L/S of 50 nm/50 nm were achieved in a reasonably thick resist. Simultaneously, grating structures were successfully transferred to silicon substrates and gratings were obtained with line widths of 100 nm, duty cycles of 0.5, depths of 900 nm, and sidewall scalloping as small as 5 nm. This silicon deep etching technique for structure feature sizes below 100 nm is very important for the fabrication of nano-optical devices that function in the visible regime.
8 9 10 Alcater. AMS200 I-Speeder: The Advanced Deep Plasma Etching System. Technical Report, Alcatel Vacuum Technology. 2003 Liu M, Chen B Q, Wang Y X, et al. Nano-level electron beam lithography. Chin J Semicond, 2003, 24(1): 2428 Kurihara K, Iwadate K, Namatsu H, et al. An electron beam nanolithography system and its application to Si nanofabrication. Jpn J Appl Phys, 1995, 34(12B): 69406946[DOI] 11 Nishida T, Notomi M, Iga R, et al. Quantum wire fabrication by E-beam lithography using high-resolution and high-sensitivity E-beam resist ZEP520. Jpn J Appl Phys, 1992, 31(12B): 45084514[DOI] 12 Tanenbaum D M, Lo C W, Isaacson M, et al. High resolution electron beam lithography using ZEP520 and KRS resists at low voltage. J Vac Sci Technol, 1996, B14(6): 38293833 13 Tennanta D M, Fullowan R, Takemura H, et al. Evaluation of a 100 kV thermal field emission electron-beam nanolithography system. J Vac Sci Technol, 2000, B18(6): 30893094 14 15 Long S B, Li Z G, Chen B Q, et al. Process study of ZEP520 positive electron beam resist. Microfabrication Technol, 2005, (1): 616 Bosch R B. Trench etch process for a single-wafer RIE dry etch reactor. US Patent, No. 4855017, 1994

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