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On Design and Implementation of a Decimation Filter for Multistandard Wireless Transceivers

AbstractIn this work, we deal with the design and implementation of a decimation filter to be used in wideband radio-frequency receiver. The paper outlines architecture considerations for multistandard wireless transceivers. Also, it describes the design steps and the tradeoffs concerning the hardware implementation. GSM and DECT standards specifications are met by the proposed filtering cascade structure. The filter processes six-bits data stream input from a fourth-order sigmadelta modulator and has been prototyped in a field-programmable gate array device. Index TermsDecimation filtering, hardware implementation, sigmadelta conversion, wireless communications.

I. INTRODUCTION HE development of single-chip receivers became absolutely necessary in the last years. In fact, an expanding growth of wireless communications systems accomplished of a multitude of standards has been observed [1][3]. Moreover, the competitive market imposes low-cost and low-power devices working with several standards. In order to assure the adaptability to different standards, digital processing is more advisable than analog processing. In reception process, when analog-to-digital conversion is performed before channel selection, it covers severe specifications due to the presence of strong adjacent channel blockers along with the desired signal. Because of the high in-band signal-to-noise ratio (SNR) proposed by sigmadelta converter, this kind of converter is currently included in transceivers schemes [4], [5]. Sigmadelta converters are designed to shape the noise away from the band of interest [6]. This oversampling based technique supposes the use of a digital filter to prevent quantization noise aliasing during sampling rate decreasing. This decimator filter needs to perform both filtering of the out of band quantization noise and the adjacent channel blockers. It means that is required from the filter design to exhibit a high-dynamic range, a programmable bandwidth to accommodate different standards, and precise tuning to select the desired channel within a standard. Decimation filters must be very efficient computationally since the filtering is usually performed at a high rate. Moreover, compactness and cost constraints impose low power and a small chip area.
Manuscript received October 24, 2001; revised December 8, 2001; accepted April 25, 2002. The editor coordinating the review of this paper and approving it for publication is S. S. Lawson. This work was supported in part by the TunisianFrench Technical Collaboration Program. A. Ghazel and K. Grati are with the UTIC, Ecole Suprieure des Communications de Tunis (SUPCOM), 2088 Tunis, Tunisia (e-mail: [email protected]; [email protected].). L. Naviner is with the ComElec, Ecole Nationale Suprieure des Tlcommunications de Paris (ENST-Paris), 75634, Paris Cedex 13, France (e-mail: [email protected]). Digital Object Identifier 10.1109/TWC.2002.805093

Several design and implementations of decimation filters for sigmadelta converters are presented in recent papers. White and Elmasry have proposed low-power design techniques for multimode multistage decimation filter adapted to both Mobitex and Ardix wireless networks specifications [7]. In their paper, a third order comb filter and a first-stage finite-impulse response (FIR) filter are common to the two standards and only a second-stage FIR filter has coefficients and frequencies depending on the mode. In [8], authors proposed filter structure with decimation and sampling rates adapted to global system for mobile communications (GSM) and digital european cordless telephone (DECT) applications, they described a low power implementation architecture by using nonrecursive architecture for the comb filter and by simplifying FIR filter multiplications to shifts and adds operations. Implementations based on scalability and on the use of the DECOR transformation to reduce power and area of decimation filters are respectively found in [9] and [10]. By considering GSM and DECT standards requirements, FIR and infinite impulse response (IIR) structures of digital filters have been studied, by authors in [11], then, compared in terms of performances and computational complexity. IIR filter solution with almost linear phase is designed and gives good results with less order than FIR filters. But analysis of computational complexity shows that, for a decimation factor less or equal to four, half-band polyphase FIR filters require less number of multiplications since their coefficients are symmetric and odd ones are equal to zero [11]. This paper deals with the design and implementation of a decimation filter to be used in wideband radio-frequency wireless systems. A decimation filter cascade structure is designed to meet the GSM and DECT standards specifications [1], [2] and to be very efficient computationally. Since the computation power depends on the filter order and this one depends on the filter specifications, the authors propose a practical method to look for relaxed filter specifications that take into consideration multistage structure. This paper is organized as follows. Section II deals with the receiver architecture choice. Considerations on filter design and its performance analysis are seen in Section III. Hardware implementation is presented in Section IV. Finally, some conclusions and future work are outlined in Section V. II. RECEIVER ARCHITECTURE CONSIDERATIONS A multistandard wireless system must meet the performance requirements for each standard and adjust to the different channel bandwidths and carrier frequencies. Many receivers architectures have been proposed: the conventional super-heterodyne architecture [12][15], the low intermediate frequency (Low-IF) architecture [4], the wideband intermediate frequency

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Fig. 2. Multistage decimation filter structure.

Fig. 1.

Direct conversion homodyne receiver.

with double conversion (WIF) architecture [5] and direct homodyne conversion [16], [17]. In this work, we consider the direct homodyne conversion receiver because it eliminates many off-chip components. In homodyne architecture, all of the channels are frequency translated to baseband before any channel filtering is performed [16][19]. Channel selection can be performed in the analog domain or in digital domain. Analog domain channel selection imposes an R-C high dynamic range, highly linear channel select filter and a difficult programmability, but a relatively easy analog-to-digital conversion [20], [21]. Inversely, digital channel selection imposes a high dynamic range of the analog-to-digital converter, but easier possibility of on-chip programmable filter structures to accommodate the variable channel bandwidth [22]. So, digital channel selection has been retained for this work (see Fig. 1). A fourth-order sigmadelta analog-to-digital converter with a 6-b data stream output is considered, with oversampling ratios (OSR) given by 64 (for GSM) and 32 (for DECT). With these oversampling rates, dynamic range requirement of 98 dB for GSM and 85 dB for DECT can be achieved [23]. III. FILTER STRUCTURE AND DESIGN Specification of the filter consists on specification of sam, passband frequency , stopband frepling frequency , transition band , passband ripples quency , stopband ripples and phase linearity. The stopband frequency is the half of the Nyquist rate. The ). Knowledge passband is as large as possible (ideally of the transmission processing allows efficient design by pertinently limit the passband. In fact, filters in the transmitter reduce effective information band. Passband ripples is dependent of the modulation scheme used in the transmission. Suppleness is obtained if the information is not on the signal amplitude (but on the frequency/phase). Stopband ripples is in report with the total noise present in the stopband (quantization noise and blockers/interferers channels). Many bands may be defined in order to optimize the stopband requirements, each one composed by blockers/interferers channels and quantization noise. If only one stopband is considered, the attenuation must to be enough to reduce the worst case blocker noise power according to carrier-to-noise radio (CNR) requirements [24]. The performance of a decimation filter depends on the type, the order, and the architecture of the filter. The filter order depends on the ratio between width of transition band and of the filter (see [25, eq. (1)]) sampling frequency (1) where function depending on and

Because sigmadelta converters are oversampled, carries to high order filters and so too high power computation. To overcome this problem, the filter can be implemented in a multistage approach [23]. Each stage implements a part of the filtering and is followed by a down sampling. The filters running at higher sampling rates have larger transition bands and filters presenting narrower transition bands run at lower sampling rates, carrying to lower overall computation needs. Both output noise power and decimation filter passband ripples can be calculated at the end of each stage using an equivalent low-pass transfer function and classic techniques of digital filtering processing [25]. Comb filters are very interesting for first-stage of decimation process because they need no multiplier (see [26, eq. (2)]). Unfortunately, they present two drawbacks: an insufficient attenuation in stopband and distortion in passband. Insufficient attenuation in stop band can be overcome by cascading several filters. Using a corrector filter can compensate distortion in passband. (2) The comb filter is an efficient way to decimate the converter output to four times the Nyquist rate [26]. For the remaining four times of decimation, previous works used a cascade composed of two half-band filters and a corrector FIR filter [8], [11], [27], [28]. After analyzing other possible filtering structures a low computation complexity for required specifications is obtained with a cascade structure composed of Comb filter followed by one half band filter and a FIR filter (Fig. 2). Because we consider a sigmadelta modulator with order , a cascade of comb filters is necessary [23]. This comb cascade performs a decimation for the GSM and for the DECT. For factor remaining stages the following method is defined to determine filters specifications. For half-band filter passband frequency is chosen equal is deto channel bandwidth. The stopband frequency . According fined by considering the symmetry to is calcuto blockers profiles the stopband attenuation lated to obtain an attenuation of out-of-band noise 10 dB below noise present in transition band. According to interis calculated ferers profiles the stopband attenuation to obtain an attenuation of in band aliased noise 10 dB below signal level. The worst case is considered for filter attenuation. is chosen For last stage FIR filter passband frequency equal to 82% channel bandwidth. The transition band is from 82% to 100% channel bandwidth. According to blockers and interferes profiles the stopband attenuation is calculated in order to obtain required CNR by considering in-band signal power and power of noise components aliased into Nyquist band. The worst case is considered for filter attenuation.

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Fig. 3. GSM and DECT blockers and interferers specifications at receiver antenna input.

Fig. 4. Comb filter implementation architecture.

By applying this method for decimation filters design to meet the carrier to noise requirement for the worst case blocking profile and adjacent channel interferers for GSM and DECT standards (Fig. 3) the following specifications are obtained for each filter. Half-band filter stage: For GSM standard, a transition dB band of 100 kHz and a stopband rejection of are considered. For DECT standard, a transition band dB are of 700 kHz and a stopband rejection of considered. FIR filter stage: For GSM standard, a transition band of dB are considered. 18 kHz and a stopband rejection of For DECT standard, a transition band of 126 kHz and a dB are considered. stopband rejection of

Fig. 5. FIR filter implementation architecture.

IV. FILTER IMPLEMENTATION CONSIDERATIONS Comb filter can be efficiently implemented by separating its into numerator and denominator secmagnitude response tions and by moving the numerator section after the down-sampling operation (Fig. 4). The denominator is a cascade of accumulators and the numerator is a cascade of subtractors. A 2s complement wrap-around arithmetic is used to avoid overflow problem as long as the register width is greater or equal to value given by (3) (3)

Half-band and FIR filters can be efficiently implemented with a polyphase direct-form filter, which allows the filter to run at the decimated rate instead of the input rate, reducing the computation complexity by approximately one-half. For FIR filters, which are based on multiplying operations, three hardware implementations have been envisaged [28]. In the first solution, a generic multiplier is in charge of all data-coefficient products. The second solution uses generic adders for multiplication. The third solution is based on wired adders for each coefficient. The differences among these solutions concern granularity (parallel multiplying for one and serial multiplying for two) and specificity (generality for onetwo and dedicated coefficients for three) of the processing. The filter has been prototyped in a field-programmable gate array (FPGA). FPGAs are composed of basic logic cells (LCELLs) and provide reconfigurable hardware, flexible interconnect, and field-programmable ability. Nevertheless,

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Fig. 6.

Experimental performances of decimation filter.

TABLE I FILTERS COMPUTATIONAL RESULTS

of all, we have evaluated the necessary computation power for the processing. After this, we have developed an FPGA-adapted model for the corresponding operators with VHDL. The chosen solution is those satisfying the demanded computation power and carrying to the lowest number of LCELLs. According to experimental results of this study the best compromise between cells number and propagation time, for GSM and DECT filters, is obtained with the generic multiplier-based implementation solution (Fig. 5) (Table I). Fig. 6 presents signal spectrum at the decimation filter input and at the decimation filter output. A 10-bit resolution for filter coefficients digital format representation is considered to represent coefficients variation range (0.05 to 0.451).

V. CONCLUSION In this paper, we have described the architecture, the synthesis and the hardware implementation of a decimation filter designed for 6-bit data stream input, from a fourth-order sigmadelta modulator adapted for multistandard wireless receiver. The prototyped filter is based on fifth-order comb filter, one half-band filter stages and a FIR correction filter. Obtained results show that the use of carry ripple adders allows minimizing LCELL amount for comb filter implementation. For half-band and FIR correction filters, which are based on multiplying operations, a single generic multiplier based architecture is the more suitable solution. Almost all of decimation filters for radio communications related in literature are using FIR filters because of the ease with which exactly linear phase could be achieved. However, linear phase over the entire band is not often required. Future works include looking for a simplified new method to design an almost linear phase IIR filters for a given specification of the allowed phase.

when implementing functions with FPGAs, we need to take into account two important factors: operative granularity and routing resources. Basic logic cells input width determinates the optimal granularity for the input functions to be implemented. Also, limited routing resources can carry to congestion problems, which increases propagation delay and degrades area efficiency. Both these limitations were taken into account in our oriented VHDL modeling [28]. The hardware-optimized implementation has obtained with the following approach. First

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