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    Shreyansh Rajput Resume

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    Shreyansh Rajput Resume

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    shreyansh.rajput1522
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    2 views1 page

    Shreyansh Rajput Resume

    Uploaded by

    shreyansh.rajput1522

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    Shreyansh Rajput

    UG Final Year - Electronics and Telecommunication Engineering


    •[email protected] • +91-8815894365 • linkedin.com/in/shreyansh-rajput
    Education
    •B.Tech., Electronics and Telecommunication Engineering 2022- 2025
    Shri G. S. Institute of Technology and Science, Indore (RGPV) 61.2%
    •Diploma in Electronics Engineering 2019 - 2022
    Govt. Polytechnic College, Itarsi (RGPV) 86.2%
    •Senior Secondary (12th) 2018 - 2019
    West Central Railway SR SEC School, Itarsi (CBSE) 52.8%
    •Secondary (10th) 2016 - 2017
    West Central Railway SR SEC School, Itarsi (CBSE) 76%

    Experience
    •Chip Design Intern using Cadence June 2024 – July 2024
    E&I Department SGSITS, Indore
    – Gained hands-on experience in chip design, simulation, and verification of integrated circuits.
    – Focused on using Cadence Virtuoso for analog and mixed-signal chip design.
    – Performed Design Rule Checks (DRC) and Layout vs. Schematic (LVS) verification to ensure design integrity.

    Academic Projects
    •Smart Dustbin with Waste Separation Aug 2023 – Dec 2023
    SGSITS, Indore
    – Developed a smart dustbin using Arduino for waste type detection with ultrasonic and soil moisture sensors.
    – Programmed an Arduino Uno to classify and process waste based on sensor input, controlling a servomotor for
    waste flap operation.
    •SR Latch Using Cadence Jun 2024 – Jul 2024
    SGSITS, Indore
    – Designed an SR Latch schematic using NAND gates in Cadence Virtuoso.
    – Simulated latch behavior to validate functionality under different input conditions.
    •LED Blinking Using FPGA Jan 2024 – Apr 2024
    SGSITS, Indore
    – Designed and implemented a basic LED blinking circuit on the Basys3 FPGA board.
    – Implemented the design using Verilog for precise control over FPGA to demonstrate understanding of digital
    circuit design.

    Technical Skills
    •Programming: C, Verilog
    •Tools: VS Code, Cadence, Vivado, Canva, Eagle
    •Operating Systems: Windows, Ubuntu

    Achievements
    •Scout & Guide: Qualified Pratham, Dwitiya, and Tritiya Sopan levels.
    •Mathematics Olympiad: Secured School Rank 11, City Rank 28, State Rank 1876, International Rank 8122 in
    IMO.
    •Science Olympiad: Secured School Rank 19, City Rank 36, State Rank 764, International Rank 1696 in NSO.

    Positions of Responsibility
    •AAYAM 2023, SGSITS: Organized games and managed department resources and budgets.
    •Departmental Activities: Led a team to organize workshops and inter-branch competitions.

    Extracurricular Activities
    •Sports: Member of department volleyball and football teams at SGSITS.
    •Alumni Lectures: Attended alumni lecture sessions to gain insights into industry practices.

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