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    Model Question Paper Templet 7 Sem (2021 Scheme)

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    Model Question Paper Templet 7 Sem (2021 Scheme)

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    2K views2 pages

    Model Question Paper Templet 7 Sem (2021 Scheme)

    Uploaded by

    sachhusachin277

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    21EC71

    Model Question Paper-1/2 with effect from 2021(CBCS Scheme)


    USN

    7th Semester B.E. Degree Examination


    Subject Title Advanced VLSI
    TIME: 03 Hours Max. Marks: 100

    Note: 01. 02. Answer any FIVE full questions, choosing at least ONE question from each
    MODULE.
    03.
    04.

    *Bloom’s
    Module -1 Taxonomy COs Marks
    Level
    Q.01 a With a neat diagram, explain ASIC design flow L2 CO1 7
    b Explain Booth multiplier encoding by considering unsigned L2 CO1 5
    number as one of the example
    c Explain the following with relevant diagram L2 CO1 8
    a. Standard Cell based ASIC
    b. Gate array based ASIC
    OR
    Q.02 a Explain the working of a. Carry skip and b. Carry bypass adders L2 CO1 7
    with necessary diagrams
    b Define data path and explain any 8 data path elements with neat L2 CO1 8
    diagram
    c Explain I/O cells with neat diagram. L2 CO1 5
    Module-2
    Q. 03 a Explain about the following: Goals and objectives of 1.Floor L2 CO2 8
    planning 2. Placement and 3. Routing &
    CO3
    b Explain the global routing methods in an ASIC physical design L2 CO2 7
    &
    CO3
    c Explain the following in ASIC floor plan 1. Clock planning 2. L2 CO2 5
    Power planning in brief &
    CO3
    OR
    Q.04 a Explain the following placement algorithms: 1. Min-cut placement L2 CO2 8
    2. Iterative placement improvement &
    CO3
    b Explain global routing between blocks with neat diagram L2 CO2 7
    &
    CO3
    c Explain the concept of measurement of delay in floor planning L2 CO2 5
    &
    CO3
    Module-3
    Q. 05 a Explain the verification process of system verilog L2 CO5 7
    b Explain the different types of array methods used in unpacked L2 CO5 8
    arrays
    c Write a short note on built in data types of system verilog with L2 CO5 5
    examples

    Page 01 of 02
    21EC71
    OR
    Q. 06 a Explain the factors in randomizing the stimulus to design L2 CO5 8
    b Explain the various test bench components L2 CO5 7
    c Explain the constants and strings in system verilog with examples L2 CO5 5
    Module-4
    Q. 07 a Explain tasks and void functions with examples L2 CO4 7
    b Explain with examples the various system verilog assertions L2 CO4 8
    c Explain the 1.Returning of array from a function 2. Passing an L2 CO4 5
    array to a function in system verilog
    OR
    Q. 08 a Explain the routine arguments with necessary examples L2 CO4 8
    b Explain the concept of separating the test bench and design in L2 CO4 7
    system verilog with an example
    c Write a short note on procedural statements in system verilog L2 CO4 5
    Module-5
    Q. 09 a Write about the common randomization problems in system L2 CO4 7
    verilog
    b List the various coverage types in system verilog and explain them L2 CO4 8
    c Write a short note on measuring coverage statistics during L2 CO4 5
    simulation
    OR
    Q. 10 a Explain about the various random number generators in system L2 CO4 8
    verilog
    b Which are the various functional coverage strategies? Explain them L2 CO4 7
    in detail
    c List the various random number functions and explain them in L2 CO4 5
    brief.
    *Bloom’s Taxonomy Level: Indicate as L1, L2, L3, L4, etc. It is also desirable to indicate the COs and POs to be
    attained by every bit of questions.

    Page 02 of 02

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