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UltraScale and

UltraScale+ FPGAs
Packaging and Pinouts

Product Specification

UG575 (v1.19) May 10, 2023

AMD Adaptive Computing is creating an environment where


employees, customers, and partners feel welcome and included.
To that end, we’re removing non-inclusive language from our
products and related collateral. We’ve launched an internal
initiative to remove language that could exclude people or
reinforce historical biases, including terms embedded in our
software and IPs. You may still find examples of non-inclusive
language in our older products as we work to make these
changes and align with evolving industry standards. Follow this
link for more information.
Table of Contents
Chapter 1: Packaging Overview
Introduction to the UltraScale Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Introduction to UltraScale and UltraScale+ FPGAs Packaging and Pinouts . . . . . . . . . . . . . . . . . . . 10
Differences from Previous Generations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device/Package Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Gigabit Transceiver Channels by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
User I/O Pins by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Footprint Compatibility between Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Die Level Bank Numbering Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Chapter 2: Package Files


About ASCII Package Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Package Specifications Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
ASCII Pinout Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Chapter 3: Device Diagrams


Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
FBVA676 Package–XCKU035 and XCKU040 and RBA676 Package–XQKU040 . . . . . . . . . . . . . . . . 204
SFVA784 (XCKU035 and XCKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
FBVA900 (XCKU035 and XCKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
FFVA1156 (XCKU025) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
FFVA1156 (XCKU035) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
FFVA1156 (XCKU040) and RFA1156 (XQKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
FFVA1156 (XCKU060) and RFA1156 (XQKU060) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
FFVA1156 (XCKU095) and RFA1156 (XQKU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
FFVA1517 (XCKU060) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
FLVA1517 (XCKU085 and XCKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
FFVC1517 (XCKU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
FLVD1517 (XCKU115) and RLD1517 (XQKU115). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
FFVB1760 (XCKU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
FLVB1760 (XCKU085) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
FLVB1760 (XCKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

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FLVD1924 (XCKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
FLVF1924 (XCKU085) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
FLVF1924 (XCKU115) and RLF1924 (XQKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
FLVA2104 (XCKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
FFVB2104 (XCKU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
FLVB2104 (XCKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
FFVC1517 (XCVU065) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
FFVC1517 (XCVU080 and XCVU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
FFVD1517 (XCVU080 and XCVU095). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
FLVD1517 (XCVU125). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
FFVB1760 (XCVU080 and XCVU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
FLVB1760 (XCVU125) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
FFVA2104 (XCVU080 and XCVU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
FLVA2104 (XCVU125) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
FFVB2104 (XCVU080 and XCVU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
FLVB2104 (XCVU125) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
FLGB2104 (XCVU160 and XCVU190) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
FFVC2104 (XCVU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
FLVC2104 (XCVU125) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
FLGC2104 (XCVU160 and XCVU190) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
FLGB2377 (XCVU440). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
FLGA2577 (XCVU190). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
FLGA2892 (XCVU440). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
SBVC484 (XCAU7P and XAAU7P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
FFVB676 (XCAU10P and XAAU10P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
FFVB676 (XCAU15P and XAAU15P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
FFVB676 (XCAU20P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
FFVB676 (XCAU25P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
SBVB484 (XCAU10P and XAAU10P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
SBVB484 (XCAU15P and XAAU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
SFVB784 (XCAU20P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
SFVB784 (XCAU25P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
UBVA368 (XCAU10P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
UBVA368 (XCAU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
FFVA676 (XCKU3P and XCKU5P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
FFVB676 (XCKU3P and XCKU5P) and FFRB676 (XQKU5P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
SFVB784 (XCKU3P and XCKU5P) and SFRB784 (XQKU5P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
FFVD900 (XCKU3P and XCKU5P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
FFVD900 (XCKU11P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
FFVE900 (XCKU9P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

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FFVE900 (XCKU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
FFVA1156 (XCKU11P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
FFVA1156 (XCKU15P) and FFRA1156 (XQKU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
FFVE1517 (XCKU11P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
FFVE1517 (XCKU15P) and FFRE1517 (XQKU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
FFVA1760 (XCKU15P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
FFVE1760 (XCKU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
FFVJ1760 (XCKU19P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
FFVB2104 (XCKU19P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
FFVC1517 (XCVU3P) and FFRC1517 (XQVU3P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
FFVC1517 (XCVU3P) and FFRC1517 (XQVU3P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
FSVJ1760 (XCVU23P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
FLGF1924 (XCVU11P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
FSVH1924 (XCVU31P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
FLVA2104 (XCVU5P and XCVU7P) and FLRA2104 (XQVU7P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
FLGA2104 (XCVU9P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
FHGA2104 (XCVU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
FLVB2104 (XCVU5P and XCVU7P) and FLRB2104 (XQVU7P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
FLGB2104 (XCVU9P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
FLGB2104 (XCVU11P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
FHGB2104 (XCVU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
FLVC2104 (XCVU5P and XCVU7P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
FLGC2104 (XCVU9P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
FLGC2104 (XCVU11P) and FLRC2104 (XQVU11P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
FHGC2104 (XCVU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
FSGD2104 (XCVU9P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
FSGD2104 (XCVU11P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
FIGD2104 (XCVU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
FIGD2104 (XCVU27P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
FIGD2104 (XCVU29P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
FSVH2104 (XCVU33P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
FSVH2104 (XCVU35P and XCVU45P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
FLGA2577 (XCVU9P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
FLGA2577 (XCVU11P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
FLGA2577 and FSGA2577 (XCVU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
FSGA2577 (XCVU27P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
FSGA2577 (XCVU29P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
FSVH2892 (XCVU35P and XCVU45P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
FSVH2892 (XCVU37P and XCVU47P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
FSVK2892 (XCVU57P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

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FSVA3824 (XCVU19P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
FSVB3824 (XCVU19P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
VSVA1365 (XCVU23P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

Chapter 4: Mechanical Drawings


Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
UBVA368 Flip-Chip, Fine-Pitch BGA (XCAU10P and XCAU15P). . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
SBVB484 Flip-Chip, Chip-Scale (0.8 mm) BGA
(XCAU10P, XAAU10P, XCAU15P, and XAAU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
SBVC484 Flip-Chip, Chip-Scale (0.8 mm) BGA
(XCAU7P and XAAU7P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
FBVA676 Bare-die Flip-Chip, Fine-Pitch BGA
(XCKU035 and XCKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
FFVA676 and FFVB676 Flip-Chip, Fine-Pitch BGA
(XCAU10P, XAAU10P, XCAU15P, XAAU15P, XCAU20P, XCAU25P, XCKU3P, and XCKU5P) . . . 407
FFRB676 Ruggedized Flip-Chip, Fine-Pitch BGA (XQKU5P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
RBA676 Ruggedized Flip-Chip, Fine-Pitch BGA (XQKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
SFVA784 Flip-Chip, Chip-Scale (0.8 mm) BGA
(XCKU035 and XCKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
SFVB784 Flip-Chip, Super-Fine Pitch (0.8 mm) BGA
(XCAU20P, XCAU25P, XCKU3P, and XCKU5P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
SFRB784 Ruggedized Flip-Chip, Super Fine-Pitch BGA (XQKU5P) . . . . . . . . . . . . . . . . . . . . . . . . . . 412
FBVA900 Bare-die Flip-Chip, Fine-Pitch BGA
(XCKU035 and XCKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
FFVD900 (XCKU3P, XCKU5P, and XCKU11P) and FFVE900 (XCKU9P and XCKU13P) . . . . . . . . . . . 415
FFVA1156 Flip-Chip, Fine-Pitch BGA
(XCKU025, XCKU035, and XCKU040). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
FFVA1156 Flip-Chip, Fine-Pitch BGA
(XCKU060, XCKU095, and XCKU11P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
FFVA1156 Flip-Chip, Fine-Pitch BGA (XCKU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
FFRA1156 Ruggedized Flip-Chip, Fine-Pitch BGA (XQKU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
RFA1156 Ruggedized Flip-Chip, Fine-Pitch BGA
(XQKU040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
RFA1156 Ruggedized Flip-Chip, Fine-Pitch BGA
(XQKU060 and XQKU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
VSVA1365 Flip-Chip, Fine-Pitch BGA (XCVU23P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
FFVA1517, FFVC1517, and FFVD1517 Flip-Chip, Fine-Pitch BGA (XCKU060, XCKU095, XCVU065,
XCVU080, XCVU095) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
FFVC1517 (XCVU3P) and FFVE1517 (XCKU11P and XCKU15P) Flip-Chip, Fine-Pitch BGA . . . . . . . 424
FFRC1517 (XQVU3P) and FFRE1517 (XQKU15P) Ruggedized Flip-Chip, Fine-Pitch BGA . . . . . . . . 425
FLVA1517 (XCKU085 and XCKU115) and FLVD1517 (XCKU115 and XCVU125) Flip-Chip, Fine-Pitch
BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

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RLD1517 Ruggedized Flip-Chip, Fine-Pitch BGA
(XQKU115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
FFVA1760 Flip-Chip, Fine-Pitch BGA (XCKU15P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
FFVB1760 Flip-Chip, Fine-Pitch BGA (XCKU095, XCVU080, and XCVU095) . . . . . . . . . . . . . . . . . . 429
FLVB1760 Flip-Chip, Fine-Pitch BGA (XCKU085, XCKU115, and XCVU125) . . . . . . . . . . . . . . . . . . 430
FFVE1760 Flip-Chip, Fine-Pitch BGA (XCKU15P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
FFVJ1760 Flip-Chip, Fine-Pitch BGA (XCKU19P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
FSVJ1760 Flip-Chip, Fine-Pitch BGA (XCVU23P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
FLVD1924 (XCKU115) and FLVF1924 (XCKU085 and XCKU115) Flip-Chip, Fine-Pitch BGA . . . . . . 434
FLGF1924 (XCVU11P) Flip-Chip, Fine-Pitch BGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
RLF1924 (XQKU115) Ruggedized Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
FSVH1924 (XCVU31P) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring, BGA . . . . . . . . . . . . . . . . 437
FFVA2104 (XCVU080 and XCVU095) and FFVB2104 (XCKU095, XCVU080, and XCVU095) Flip-Chip,
Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
FFVB2104 (XCKU19P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
FHGA2104 (XCVU13P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
FHGB2104 (XCVU13P) and FHGC2104 (XCVU13P) Flip-Chip, Fine-Pitch BGA. . . . . . . . . . . . . . . . . 441
FLVA2104 (XCKU115 and XCVU125) and FLVB2104 (XCKU115 and XCVU125) Flip-Chip, Fine-Pitch
BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
FLVA2104 (XCVU5P and XCVU7P) and FLVB2104 (XCVU5P and XCVU7P) Flip-Chip, Fine-Pitch BGA. .
443
FLRA2104 (XQVU7P) and FLRB2104 (XQVU7P) Ruggedized Flip-Chip, Fine-Pitch BGA . . . . . . . . . 444
FLGA2104 (XCVU9P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
FLGB2104 (XCVU160 and XCVU190) and FLGC2104 (XCVU160 and XCVU190) Flip-Chip, Fine-Pitch
BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
FLGB2104 (XCVU9P and XCVU11P) and
FLGC2104 (XCVU11P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
FLRC2104 (XQVU11P) Ruggedized Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
FFVC2104 (XCVU095) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
FLGC2104 (XCVU9P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
FLVC2104 (XCVU125) Flip-Chip, Fine-Pitch BGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
FLVC2104 (XCVU5P and XCVU7P) Flip-Chip, Fine-Pitch BGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
FIGD2104 (XCVU13P, XCVU27P, and XCVU29P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . 453
FSGD2104 (XCVU9P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
FSGD2104 (XCVU11P) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
FSVH2104 (XCVU33P) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring, BGA . . . . . . . . . . . . . . . . 456
FSVH2104 (XCVU35P and XCVU45P) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring, BGA . . . . 457
FLGB2377 Flip-Chip, Fine-Pitch BGA (XCVU440) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
FLGA2577 Flip-Chip, Fine-Pitch BGA (XCVU190) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
FLGA2577 Flip-Chip, Fine-Pitch BGA (XCVU9P and XCVU13P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
FLGA2577 Flip-Chip, Fine-Pitch BGA (XCVU11P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

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FSGA2577 Flip-Chip, Fine-Pitch BGA
(XCVU13P, XCVU27P, and XCVU29P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
FLGA2892 Flip-Chip, Fine-Pitch BGA (XCVU440) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
FSVH2892 (XCVU35P and XCVU45P) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring, BGA . . . . 464
FSVH2892 (XCVU37P and XCVU47P) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring, BGA . . . . 465
FSVK2892 (XCVU57P) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring, BGA . . . . . . . . . . . . . . . . 466
FSVA3824 and FSVB3824 (XCVU19P) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring, BGA. . . . 467

Chapter 5: Package Marking


Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

Chapter 6: Packing and Shipping


Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Chapter 7: Soldering Guidelines


Soldering Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
Strain Gauge Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
Solder Paste . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Chapter 8: Recommended PCB Design Rules for BGA Packages


BGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Stencil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

Chapter 9: Edge Bonding


Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
Edge Bonding Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
Edge Bond Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Underfill Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Conformal Coating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

Chapter 10: Thermal Specifications


Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Thermal Resistance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Support for Thermal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

Chapter 11: Thermal Management Strategy


Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Thermal Interface Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Heat Sink Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Measurement Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

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Chapter 12: Heat Sink Guidelines for Bare-die Flip-Chip Packages
Heat Sink Attachments for Bare-die FB Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
Types of Heat Sink Attachments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

Chapter 13: Mechanical and Thermal Design Guidelines for Lidless Flip-chip
Packages
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Lidless Flip-Chip Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

Appendix A: Additional Resources and Legal Notices


Finding Additional Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

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Chapter 1

Packaging Overview

Introduction to the UltraScale Architecture


The AMD UltraScale™ architecture is the first ASIC-class architecture to enable
multi-hundred gigabit-per-second levels of system performance with smart processing,
while efficiently routing and processing data on-chip. UltraScale architecture-based devices
address a vast spectrum of high-bandwidth, high-utilization system requirements by using
industry-leading technical innovations, including next-generation routing, ASIC-like
clocking, 3D-on-3D ICs, multiprocessor SoC (MPSoC) technologies, and new power
reduction features. The devices share many building blocks, providing scalability across
process nodes and product families to leverage system-level investment across platforms.

AMD Virtex™ UltraScale+™ devices provide the highest performance and integration
capabilities in a FinFET node, including both the highest serial I/O and signal processing
bandwidth, as well as the highest on-chip memory density. As the industry's most capable
FPGA family, the Virtex UltraScale+ devices are ideal for applications including 1+Tb/s
networking and data center and fully integrated radar/early-warning systems.

AMD Virtex UltraScale devices provide the greatest performance and integration at 20 nm,
including serial I/O bandwidth and logic capacity. As the industry's only high-end FPGA at
the 20 nm process node, this family is ideal for applications including 400G networking,
large scale ASIC prototyping, and emulation.

AMD Kintex™ UltraScale+ devices provide the best price/performance/watt balance in a


FinFET node, delivering the most cost-effective solution for high-end capabilities, including
transceiver and memory interface line rates as well as 100G connectivity cores. Our newest
mid-range family is ideal for both packet processing and DSP-intensive functions and is well
suited for applications including wireless MIMO technology, Nx100G networking, and data
center.

AMD Artix™ UltraScale+ devices provide high serial bandwidth and signal compute density
in a cost-optimized device for critical networking applications, vision and video processing,
and secured connectivity. Coupled with the innovative InFO packaging, which provides
excellent thermal and power distribution, Artix UltraScale+ devices are perfectly suited to
applications requiring high compute density in a small footprint.

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Kintex UltraScale devices provide the best price/performance/watt at 20 nm and include


the highest signal processing bandwidth in a mid-range device, next-generation
transceivers, and low-cost packaging for an optimum blend of capability and
cost-effectiveness. The family is ideal for packet processing in 100G networking and data
centers applications as well as DSP-intensive processing needed in next-generation medical
imaging, 8k4k video, and heterogeneous wireless infrastructure.

AMD Zynq™ UltraScale+ MPSoC devices provide 64-bit processor scalability while
combining real-time control with soft and hard engines for graphics, video, waveform, and
packet processing. Integrating an Arm®-based system for advanced analytics and on-chip
programmable logic for task acceleration creates unlimited possibilities for applications
including 5G Wireless, next generation ADAS, and Industrial Internet-of-Things.

This packaging and pinout specification user guide is part of the UltraScale Architecture
documentation suite available at: www.xilinx.com/ultrascale.

Introduction to UltraScale and UltraScale+ FPGAs


Packaging and Pinouts
This section describes the packages and pinouts for the UltraScale architecture-based
FPGAs in various organic flip-chip 0.8 mm and 1.0 mm pitch BGA packages.

• Kintex UltraScale, Kintex UltraScale+, and Artix UltraScale+ devices are offered in
low-cost, space-saving flip-chip and bare-die flip-chip packages that are optimally
designed for high performance-to-price ratio.
• Virtex UltraScale and Virtex UltraScale+ devices are offered exclusively in high
performance flip-chip BGA packages that are optimally designed for highest system
capacity, bandwidth and signal performance. Package inductance is minimized as a
result of optimal placement and even distribution as well as an increased number of
power and GND pins.
• Zynq UltraScale+ MPSoCs are further described in the Zynq UltraScale+ MPSoC
Packaging and Pinouts User Guide (UG1075).

IMPORTANT: Many of the standard packages for commercial (XC) devices are lead-free (signified by an
additional V in the package name). All of the UltraScale or UltraScale+ devices supported in a
particular package are footprint compatible. Each device is split into I/O banks to allow for flexibility in
the choice of I/O standards. See the UltraScale Architecture SelectIO Resources User Guide (UG571).

UltraScale and UltraScale+ device’s flip-chip assembly materials are manufactured using
ultra-low alpha (ULA) materials defined as <0.002 cph/cm2 or materials that emit less than
0.002 alpha-particles per square centimeter per hour.

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Differences from Previous Generations


The packaging and pinout specifications for UltraScale architecture-based FPGAs differ
from past generations, including the 7 series devices. These details are outlined in this
section.

• All packages are constructed on organic laminate substrates.


• Many of the package and die components, including flip-chip solder bumps, are
lead-free. The FLGx devices have lead in their bumps.
• Package names contain a single-character alphabetic designator followed by the exact
number of pins found on the package.
• VCCAUX_IO pins are not divided into bank groups. VCCAUX_IO must be connected to
VCCAUX at the board level.
• Internal logic is separated from I/O logic by the addition of the VCCINT_IO power pins.
VCCINT_IO must be connected to VCCINT at the board level.
• Groups of gigabit serial transceiver (GT) power pins are separated by column for each
column of GT Quads/Duals.
• Standard I/O banks each have a total of 52 SelectIO™ pins, optionally configurable as
up to 24 differential pairs.
• Each bank has one dedicated VREF pin. These pins cannot be used as user I/Os.
• Four differential clock pin pairs per bank (two per 26-pin bank) consist of a single type
of global clock (GC) input.
• Four memory byte groups per I/O bank (two per 26-pin bank) are each separated into
an upper and a lower memory byte group.
• All configuration pins are located in bank 0 and bank 65.
• A POR_OVERRIDE pin is used to override the default power-on-reset delay. See
Table 1-5.

Device/Package Combinations
Table 1-1 shows the size and BGA pitch of the UltraScale and UltraScale+ device packages.
The devices with stacked-silicon interconnect (SSI) technology are labeled.

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IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC, and the third digit in the package name is Q (for example: FFQA1156).

Table 1-1: Package Specifications


Package Specifications
Packages(1) Description
Package Type Pitch (mm) Size (mm)
UBVA368 Flip-chip, integrated fan out (InFO), bare-die 0.5 11.5 x 9.5
SBVB484
Flip-chip, super-fine-pitch 0.8 19 x 19
SBVC484
FBVA676 Bare-die, flip-chip, fine-pitch
FFVA676
Flip-chip, fine-pitch
FFVB676 1.0 27 x 27
FFRB676
Ruggedized, flip-chip, fine-pitch
RBA676
SFVA784
Flip-chip, super-fine-pitch
SFVB784 0.8 23 x 23
SFRB784 Ruggedized, flip-chip, super-fine pitch
FBVA900 Bare-die, flip-chip, fine-pitch
FFVD900 31 x 31
Flip-chip, fine-pitch
FFVE900 BGA
1.0
FFVA1156 Flip-chip, fine-pitch
FFRA1156
Ruggedized, flip-chip, fine-pitch 35 x 35
RFA1156
VSVA1365 Flip-chip, fine-pitch lidless with stiffener ring 0.92
FFVA1517
FFVC1517
Flip-chip, fine-pitch
FFVD1517
FFVE1517
FFRC1517 1.0 40 x 40
Ruggedized, flip-chip, fine-pitch
FFRE1517
RLD1517 Ruggedized, SSI, flip-chip, fine-pitch
FLVA1517
SSI, flip-chip, fine-pitch
FLVD1517

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Table 1-1: Package Specifications (Cont’d)


Package Specifications
Packages(1) Description
Package Type Pitch (mm) Size (mm)
FFVA1760
FFVB1760
Flip-chip, fine-pitch
FFVE1760
42.5 x 42.5
FFVJ1760
FLVB1760 SSI, flip-chip, fine-pitch
FSVJ1760 SSI, flip-chip, fine-pitch, lidless with stiffener ring
FLGF1924
FLVD1924 SSI, flip-chip, fine-pitch
FLVF1924 45 x 45
FSVH1924 SSI, flip-chip, fine-pitch, lidless with stiffener ring
RLF1924 Ruggedized, SSI, flip-chip, fine-pitch
FFVA2104
FFVB2104 Flip-chip, fine-pitch
FFVC2104
47.5 x 47.5
FLVA2104
FLVB2104 SSI, flip-chip, fine-pitch
FLVC2104
BGA 1.0
FLGA2104
FLGB2104 SSI, flip-chip, fine-pitch, RoHS 6/6 with exemption 15 47.5 x 47.5
FLGC2104
FLRA2104
FLRB2104 Ruggedized, SSI, flip-chip, fine-pitch 47.5 x 47.5
FLRC2104
SSI, flip-chip, fine-pitch, lidless with stiffener ring,
FSGD2104 47.5 x 47.5
RoHS 6/6 with exemption 15
FSVH2104 SSI, flip-chip, fine-pitch, lidless with stiffener ring 47.5 x 47.5
FHGA2104 (2)
SSI, flip-chip, fine-pitch, overhang, RoHS 6/6 with
FHGB2104 (2) 52.5 x 52.5
exemption 15
FHGC2104 (2)
SSI, flip-chip, fine-pitch, overhang, lidless with
FIGD2104(2) 52.5 x 52.5
stiffener ring, RoHS 6/6 with exemption 15
FLGB2377 SSI, flip-chip, fine-pitch, RoHS 6/6 with exemption 15 50 x 50
FLGA2577 SSI, flip-chip, fine-pitch, RoHS 6/6 with exemption 15 52.5 x 52.5
SSI, flip-chip, fine-pitch, lidless with stiffener ring,
FSGA2577 52.5 x 52.5
RoHS 6/6 with exemption 15

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Table 1-1: Package Specifications (Cont’d)


Package Specifications
Packages(1) Description
Package Type Pitch (mm) Size (mm)
FLGA2892 SSI, flip-chip, fine-pitch, RoHS 6/6 with exemption 15 55 x 55
FSVH2892 55 x 55
SSI, flip-chip, fine-pitch, lidless with stiffener ring
FSVK2892 BGA 1.0 55 x 55
FSVA3824 SSI, flip-chip, fine-pitch, lidless with stiffener ring 65 x 65
FSVB3824 SSI, flip-chip, fine-pitch, lidless with stiffener ring 65 x 65

Notes:
1. FFV, FLV, and FLG packages are footprint compatible when the package code letter designator and pin count are identical.
See the UltraScale Architecture and Product Overview (DS890) for specific letter codes and ordering code information.
2. These 52.5 x 52.5 packages have the same PCB ball footprint as the 47.5 x 47.5 packages and are footprint compatible.

Gigabit Transceiver Channels by Device/Package


Table 1-2 lists the quantity of gigabit transceiver channels for the UltraScale and
UltraScale+ devices. In all devices, a gigabit transceiver channel is one set of MGTRXP,
MGTRXN, MGTTXP, and MGTTXN pins. For transceiver data rate limitations on specific
device/package combinations, see UltraScale Device Data Sheets.

Table 1-2: Serial Transceiver Channels (GTH/GTY) by Device/Package


Device Package GTH Channels GTY Channels
Kintex UltraScale Devices
XCKU035 16 0
FBVA676
XCKU040 16 0
XCKU035 8 0
SFVA784
XCKU040 8 0
XCKU035 16 0
FBVA900
XCKU040 16 0
XCKU025 12 0
XCKU035 16 0
XCKU040 FFVA1156 20 0
XCKU060 28 0
XCKU095 20 8
XCKU060 FFVA1517 32 0
XCKU085 48 0
FLVA1517
XCKU115 48 0
XCKU095 FFVC1517 20 20

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Table 1-2: Serial Transceiver Channels (GTH/GTY) by Device/Package (Cont’d)


Device Package GTH Channels GTY Channels
XCKU115 FLVD1517 64 0
XCKU095 FFVB1760 32 16
XCKU085 44 0
FLVB1760
XCKU115 52 0
XCKU115 FLVD1924 52 0
XCKU085 56 0
FLVF1924
XCKU115 64 0
XCKU115 FLVA2104 52 0
XCKU095 FFVB2104 32 32
XCKU115 FLVB2104 64 0
XQKU040 RBA676 16 0
XQKU040 20 0
XQKU060 RFA1156 28 0
XQKU095 20 0
XQKU115 RLD1517 64 0
XQKU115 RLF1924 64 0
Virtex UltraScale Devices
XCVU065 20 20
XCVU080 FFVC1517 20 20
XCVU095 20 20
XCVU080 32 32
FFVD1517
XCVU095 32 32
XCVU125 FLVD1517 40 32
XCVU080 32 16
FFVB1760
XCVU095 32 16
XCVU125 FLVB1760 36 16
XCVU080 28 24
FFVA2104
XCVU095 28 24
XCVU125 FLVA2104 28 24
XCVU080 32 32
FFVB2104
XCVU095 32 32
XCVU125 FLVB2104 40 36
XCVU160 40 36
FLGB2104
XCVU190 40 36
XCVU095 FFVC2104 32 32

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Table 1-2: Serial Transceiver Channels (GTH/GTY) by Device/Package (Cont’d)


Device Package GTH Channels GTY Channels
XCVU125 FLVC2104 40 40
XCVU160 52 52
FLGC2104
XCVU190 52 52
XCVU440 FLGB2377 36 0
XCVU190 FLGA2577 60 60
XCVU440 FLGA2892 48 0
Artix UltraScale+ Devices
XCAU7P 4 0
SBVC484
XAAU7P 4 0
XCAU10P 8 0
UBVA368
XCAU15P 8 0
XCAU10P 12 0
XAAU10P 12 0
SBVB484
XCAU15P 12 0
XAAU15P 12 0
XCAU10P 12 0
XAAU10P 12 0
XCAU15P 12 0
FFVB676
XAAU15P 12 0
XCAU20P 0 12
XCAU25P 0 12
XCAU20P 0 12
SFVB784
XCAU25P 0 12
Kintex UltraScale+ Devices
XCKU3P 0 16
FFVA676
XCKU5P 0 16
XCKU3P 0 16
FFVB676
XCKU5P 0 16
XCKU3P 0 16
SFVB784
XCKU5P 0 16
XCKU3P 0 16
XCKU5P FFVD900 0 16
XCKU11P 16 0

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Table 1-2: Serial Transceiver Channels (GTH/GTY) by Device/Package (Cont’d)


Device Package GTH Channels GTY Channels
XCKU9P 28 0
FFVE900
XCKU13P 28 0
XCKU11P 20 8
FFVA1156
XCKU15P 20 8
XCKU11P 32 20
FFVE1517
XCKU15P 32 24
XCKU15P FFVA1760 44 32
XCKU15P FFVE1760 32 24
XCKU19P FFVJ1760 0 32
XCKU19P FFVB2104 0 32
XQKU5P FFRB676 0 16
XQKU5P SFRB784 0 16
XQKU15P FFRA1156 20 8
XQKU15P FFRE1517 32 24
Virtex UltraScale+ Devices
XCVU3P FFVC1517 0 40
XCVU11P FLGF1924 0 64
XCVU31P FSVH1924 0 32

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Table 1-2: Serial Transceiver Channels (GTH/GTY) by Device/Package (Cont’d)


Device Package GTH Channels GTY Channels
XCVU5P 0 52
FLVA2104
XCVU7P 0 52
XCVU9P FLGA2104 0 52
XCVU13P FHGA2104 0 52
XCVU5P 0 76
FLVB2104
XCVU7P 0 76
XCVU9P 0 76
FLGB2104
XCVU11P 0 76
XCVU13P FHGB2104 0 76
XCVU5P 0 80
FLVC2104
XCVU7P 0 80
XCVU9P 0 104
FLGC2104
XCVU11P 0 96
XCVU13P FHGC2104 0 104
XCVU9P 0 76
FSGD2104
XCVU11P 0 76
XCVU13P FIGD2104 0 76
XCVU33P 0 32
XCVU35P FSVH2104 0 64
XCVU45P 0 64
XCVU9P 0 120
XCVU11P FLGA2577 0 96
XCVU13P 0 128
XCVU13P FSGA2577 0 128
XCVU35P 0 64
XCVU37P 0 96
FSVH2892
XCVU45P 0 64
XCVU47P 0 96
XCVU19P FSVA3824 0 48
XCVU19P FSVB3824 0 80
XQVU3P FFRC1517 0 40
XQVU7P FLRA2104 0 52
XQVU7P FLRB2104 0 76
XQVU11P FLRC2104 0 96

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Table 1-3: Serial Transceiver Channels (GTH/GTY/GTM) by Device/Package


Device Package GTH Channels GTY Channels GTM Channels
Virtex UltraScale+ Devices
XCVU23P VSVA1365 0 34 4
XCVU23P FSVJ1760 0 34 4
XCVU27P 0 16 30
FIGD2104
XCVU29P 0 16 30
XCVU27P 0 32 48
FSGA2577
XCVU29P 0 32 48
XCVU57P FSVK2892 0 32 32

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User I/O Pins by Device/Package


Table 1-4 lists the number of available 3.3V-capable high-range (HR), 3.3V-capable
high-density (HD), and 1.8V-capable high-performance (HP) I/Os and the number of
differential I/O pairs for each UltraScale and UltraScale+ device/package combination.

IMPORTANT: Because of package inductance, each device/package supports a limited number of


simultaneous switching outputs. Limitations for specific applications can be determined using the AMD
Vivado ™ Design Suite report_ssn tool. See the Simultaneous Switching Outputs section of the
UltraScale Architecture SelectIO Resources User Guide (UG571) for more information.

Table 1-4: Available I/O Pins by Device/Package


Total User I/O Differential I/O
Device Package
HD(1) HR(1) HP(1) HD HR HP
Kintex UltraScale Devices
XCKU035 0 104 208 0 96 192
FBVA676
XCKU040 0 104 208 0 96 192
XCKU035 0 104 364 0 96 336
SFVA784
XCKU040 0 104 364 0 96 336
XCKU035 0 104 364 0 96 336
FBVA900
XCKU040 0 104 364 0 96 336
XCKU025 0 104 208 0 96 192
XCKU035 0 104 416 0 96 384
XCKU040 FFVA1156 0 104 416 0 96 384
XCKU060 0 104 416 0 96 384
XCKU095 0 52 468 0 48 432
XCKU060 FFVA1517 0 104 520 0 96 480
XCKU085 0 104 520 0 96 480
FLVA1517
XCKU115 0 104 520 0 96 480
XCKU095 FFVC1517 0 52 468 0 48 432
XCKU115 FLVD1517 0 104 234 0 96 216
XCKU095 FFVB1760 0 52 650 0 48 600
XCKU085 0 104 572 0 96 528
FLVB1760
XCKU115 0 104 650 0 96 600
XCKU115 FLVA2104 0 156 676 0 144 624
XCKU095 FFVB2104 0 52 650 0 48 600
XCKU115 FLVB2104 0 104 650 0 96 600
XCKU115 FLVD1924 0 156 676 0 144 624

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Table 1-4: Available I/O Pins by Device/Package (Cont’d)


Total User I/O Differential I/O
Device Package
HD(1) HR(1) HP(1) HD HR HP
XCKU085 0 104 520 0 96 480
FLVF1924
XCKU115 0 104 624 0 96 576
XQKU040 RBA676 0 104 208 0 96 192
XQKU040 0 104 416 0 96 384
XQKU060 RFA1156 0 104 416 0 96 384
XQKU095 0 52 468 0 48 432
XQKU115 RLD1517 0 104 234 0 96 216
XQKU115 RLF1924 0 104 624 0 96 576
Virtex UltraScale Devices
XCVU065 0 52 468 0 48 432
XCVU080 FFVC1517 0 52 468 0 48 432
XCVU095 0 52 468 0 48 432
XCVU080 0 52 286 0 48 264
FFVD1517
XCVU095 0 52 286 0 48 264
XCVU125 FLVD1517 0 52 286 0 48 264
XCVU080 0 52 650 0 48 600
FFVB1760
XCVU095 0 52 650 0 48 600
XCVU125 FLVB1760 0 52 650 0 48 600
XCVU080 0 52 780 0 48 720
FFVA2104
XCVU095 0 52 780 0 48 720
XCVU125 FLVA2104 0 52 780 0 48 720
XCVU080 0 52 650 0 48 600
FFVB2104
XCVU095 0 52 650 0 48 600
XCVU125 FLVB2104 0 52 650 0 48 600
XCVU160 0 52 650 0 48 600
FLGB2104
XCVU190 0 52 650 0 48 600
XCVU095 FFVC2104 0 52 364 0 48 336
XCVU125 FLVC2104 0 52 364 0 48 336
XCVU160 0 52 364 0 48 336
FLGC2104
XCVU190 0 52 364 0 48 336
XCVU440 FLGB2377 0 52 1248 0 48 1152
XCVU190 FLGA2577 0 0 448 0 0 412
XCVU440 FLGA2892 0 52 1404 0 48 1296

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Table 1-4: Available I/O Pins by Device/Package (Cont’d)


Total User I/O Differential I/O
Device Package
HD(1) HR(1) HP(1) HD HR HP
Artix UltraScale+ Devices
XCAU7P 144 0 104 144 0 96
SBVC484
XAAU7P 144 0 104 144 0 96
XCAU10P 24 0 104 24 0 96
UBVA368
XCAU15P 24 0 104 24 0 96
XCAU10P 48 0 156 48 0 144
XAAU10P 48 0 156 48 0 144
SBVB484
XCAU15P 48 0 156 48 0 144
XAAU15P 48 0 156 48 0 144
XCAU10P 72 0 156 72 0 144
XAAU10P 72 0 156 72 0 144
XCAU15P 72 0 156 72 0 144
FFVB676
XAAU15P 72 0 156 72 0 144
XCAU20P 72 0 156 72 0 144
XCAU25P 72 0 208 72 0 192
XCAU20P 72 0 156 72 0 144
SFVB784
XCAU25P 96 0 208 96 0 192
Kintex UltraScale+ Devices
XCKU3P 48 0 208 48 0 192
FFVA676
XCKU5P 48 0 208 48 0 192
XCKU3P 72 0 208 72 0 192
FFVB676
XCKU5P 72 0 208 72 0 192
XCKU3P 96 0 208 96 0 192
SFVB784
XCKU5P 96 0 208 96 0 192
XCKU3P 96 0 208 96 0 192
XCKU5P FFVD900 96 0 208 96 0 192
XCKU11P 96 0 312 96 0 288
XCKU9P 96 0 208 96 0 192
FFVE900
XCKU13P 96 0 208 96 0 192
XCKU11P 48 0 416 48 0 384
FFVA1156
XCKU15P 48 0 468 48 0 432
XCKU11P 96 0 416 96 0 384
FFVE1517
XCKU15P 96 0 416 96 0 384

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Table 1-4: Available I/O Pins by Device/Package (Cont’d)


Total User I/O Differential I/O
Device Package
HD(1) HR(1) HP(1) HD HR HP
XCKU15P FFVA1760 96 0 416 96 0 384
XCKU15P FFVE1760 96 0 572 96 0 528
XCKU19P FFVJ1760 72 0 468 72 0 432
XCKU19P FFVB2104 72 0 468 72 0 432
XQKU5P FFRB676 72 0 208 72 0 192
XQKU5P SFRB784 96 0 208 96 0 192
XQKU15P FFRA1156 48 0 468 48 0 432
XQKU15P FFRE1517 96 0 416 96 0 384
Virtex UltraScale+ Devices
XCVU3P FFVC1517 0 0 520 0 0 480
XCVU23P VSVA1365 0 0 364 0 0 336
XCVU23P FSVJ1760 72 0 572 72 0 528
XCVU11P FLGF1924 0 0 624 0 0 576
XCVU31P FSVH1924 0 0 208 0 0 192
XCVU5P 0 0 832 0 0 768
FLVA2104
XCVU7P 0 0 832 0 0 768
XCVU9P FLGA2104 0 0 832 0 0 768
XCVU13P FHGA2104 0 0 832 0 0 768
XCVU5P 0 0 702 0 0 648
FLVB2104
XCVU7P 0 0 702 0 0 648
XCVU9P 0 0 702 0 0 648
FLGB2104
XCVU11P 0 0 572 0 0 528
XCVU13P FHGB2104 0 0 702 0 0 648
XCVU5P 0 0 416 0 0 384
FLVC2104
XCVU7P 0 0 416 0 0 384
XCVU9P 0 0 416 0 0 384
FLGC2104
XCVU11P 0 0 416 0 0 384
XCVU13P FHGC2104 0 0 416 0 0 384
XCVU9P 0 0 676 0 0 624
FSGD2104
XCVU11P 0 0 572 0 0 528
XCVU13P FIGD2104 0 0 676 0 0 624
XCVU27P 0 0 520 0 0 240
FIGD2104
XCVU29P 0 0 676 0 0 312

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Table 1-4: Available I/O Pins by Device/Package (Cont’d)


Total User I/O Differential I/O
Device Package
HD(1) HR(1) HP(1) HD HR HP
XCVU33P 0 0 208 0 0 192
XCVU35P FSVH2104 0 0 416 0 0 384
XCVU45P 0 0 416 0 0 384
XCVU9P 0 0 448 0 0 414
XCVU11P FLGA2577 0 0 448 0 0 414
XCVU13P 0 0 448 0 0 414
XCVU13P FSGA2577 0 0 448 0 0 414
XCVU27P 0 0 292 0 0 134
FSGA2577
XCVU29P 0 0 448 0 0 206
XCVU35P 0 0 416 0 0 384
XCVU37P 0 0 624 0 0 576
FSVH2892
XCVU45P 0 0 416 0 0 384
XCVU47P 0 0 624 0 0 576
XCVU57P FSVK2892 0 0 624 0 0 576
FSVA3824 0 0 1976 0 0 1824
XCVU19P
FSVB3824 1 1 1664 0 0 1536
XQVU3P FFRC1517 0 0 520 0 0 480
XQVU7P FLRA2104 0 0 832 0 0 768
XQVU7P FLRB2104 0 0 702 0 0 648
XQVU11P FLRC2104 0 0 416 0 0 384

Notes:
1. The maximum user I/O numbers do not include pins in the configuration bank 0 or the GT serial transceivers.

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Pin Definitions
Table 1-5 lists the pin definitions used in UltraScale and UltraScale+ device packages.

Table 1-5: Pin Definitions


Pin Name Type Direction Description
User I/O Pins
IO_L[1 to 24][P or N]_T[0 to 3] [U or L]_N[0 to 12]_ [multi-function]_[bank number] or
IO_T[0 to 3][U or L]_N[0 to 12]_[multi-function]_[bank number]
Most user I/O pins are capable of differential signaling
and can be implemented as pairs. Each user I/O pin name
consists of several indicator labels, where:
• IO indicates a user I/O pin.
• L[1 to 24] indicates a unique differential pair with P
(positive) and N (negative) sides. User I/O pins without
the L indicator are single-ended.
Multi- Input/ • T[0 to 3][U or L] indicates the assigned byte group and
function Output nibble location (upper or lower portion) within that
group for the pin.
• N[0 to 12] the number of the I/O within its byte group.
• [multi-function] indicates any other functions that the
pin can provide. If not used for this function, the pin can
be a user I/O.
• [bank number] indicates the assigned bank for the user
I/O pin.
Four global clock (GC) pin pairs are in each bank. HDGC
pins have direct access to the global clock buffers. GC pins
have direct access to the global clock buffers, MMCMs,
and PLLs that are in the clock management tile (CMT)
adjacent to the same I/O bank. GC and HDGC inputs
provide dedicated, high-speed access to the internal
Multi- Input/ global and regional clock resources. GC and HDGC inputs
GC or HDGC
function Output use dedicated routing and must be used for clock inputs
where the timing of various clocking features is
imperative. GC or HDGC pins can be treated as user I/O
when not used as input clocks.
Up-to-date information about designing with the GC
(or HDGC) pin is available in the UltraScale Architecture
Clocking Resources User Guide (UG572).
This pin is for the DCI voltage reference resistor of P
Multi-
VRP (1) N/A transistor (per bank, to be pulled Low with a reference
function
resistor).

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Table 1-5: Pin Definitions (Cont’d)


Pin Name Type Direction Description
Byte lane clock (DBC and QBC) input pin pairs are clock
inputs directly driving source synchronous clocks to the
DBC Multi- bit slices in the I/O banks. In memory applications, these
Input
QBC function are also known as DQS. For more information, consult the
UltraScale Architecture SelectIO Resources User Guide
(UG571).
Multi- Default reset pin locations for the integrated block for PCI
PERSTN[0 to 1] Input
function Express.
User I/O Multi-Function Configuration Pins
For further descriptions, including configuration modes and recommended external pull-up/pull-down resistors,
see the UltraScale Architecture Configuration User Guide (UG570).
Multi-
EMCCLK Input External master configuration clock.
function
Multi- Data output for serial daisy-chaining or active-Low
DOUT_CSO_B Output
function chip-select output for SelectMAP daisy-chaining.
Multi-
D[04 to 31] Bidirectional Configuration data pins.
function
Multi-
A[00 to 28] Output Address output.
function
Multi- Input or
CSI_ADV_B Active-Low chip-select input or address valid output.
function Output
Multi-
FOE_B Output Active-Low flash output enable.
function
Multi- Active-Low flash write-enable for BPI flash or flash
FWE_FCS2_B Output
function chip-select for second SPI (x8) flash.
Multi-
RS[0 to 1] Output Revision select outputs.
function
Dedicated (Bank 0) Configuration Pins(2)
For more information see the UltraScale Architecture Configuration User Guide (UG570).
M[0 to 2]_0 Dedicated Input Configuration mode selection.
Bidirectional
INIT_B_0 Dedicated Active-Low initialization
(open-drain)

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Table 1-5: Pin Definitions (Cont’d)


Pin Name Type Direction Description
Bank 0 and bank 65 voltage select. This pin determines the
I/O voltage operating range and voltage tolerance for the
dedicated configuration bank 0 and multi-function
bank 65. Connect CFGBVS High or Low per the bank
voltage requirements.
• V CCO_0 = 2.5V or 3.3V, tie CFGBVS High (connect to
CFGBVS_0 Dedicated Input V CCO_0).
• V CCO_0 = 1.5V or 1.8V, tie CFGBVS Low (connect to GND)

CAUTION! To avoid device damage, this pin must be


connected correctly to either VCCO_0 or GND.

Active-Low input enables internal pull-ups during


configuration on all SelectIO pins:
PUDC_B_0 Dedicated Input 0 = Weak preconfiguration I/O pull-up resistors enabled.
1 = Weak preconfiguration I/O pull-up resistors disabled.
All configuration modes
Power-on reset delay override.

CAUTION! Do not allow this pin to float before and

POR_OVERRIDE Dedicated Input during configuration. This pin must be tied to V CCINT or
GND. Do not connect to VCCO_0.

Information about designing with the POR_OVERRIDE pin


is available in the UltraScale Architecture Configuration
User Guide (UG570).
Active-High, DONE indicates successful completion of
DONE_0 Dedicated Bidirectional
configuration.
PROGRAM_B_0 Dedicated Input Active Low, asynchronous reset to configuration logic.
TDO_0 Dedicated Output JTAG test data output.
TDI_0 Dedicated Input JTAG test data input.
Input control signal for SelectMAP data bus direction:
Input/ High for reading or Low for writing configuration data.
RDWR_FCS_B_0 Dedicated
Output
Or, active-Low flash chip-select output.
TMS_0 Dedicated Input JTAG test mode data select.
TCK_0 Dedicated Input JTAG test clock
Input/ Configuration clock. Output in Master mode or input in
CCLK_0 Dedicated
Output Slave mode.
D00_MOSI_0 Dedicated Bidirectional Data Bit 0 or SPI master-output
D01_DIN_0 Dedicated Bidirectional Data Bit 1 or serial mode data input
D02_0 Dedicated Bidirectional Data Bit 2
D03_0 Dedicated Bidirectional Data Bit 3

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Table 1-5: Pin Definitions (Cont’d)


Pin Name Type Direction Description
Other Dedicated Pins
DXN Temperature-sensing diode pins (Anode: DXP; Cathode:
DXN). The thermal diode is accessed by using the DXP and
DXN pins in bank 0. When not used, tie to GND.
Dedicated N/A
To use the thermal diode an appropriate external thermal
monitoring IC must be added. Consult the external
DXP thermal monitoring IC data sheet for usage guidelines.

System Monitor Pins(3)


Multi-
AD[0 to 15][P or N] Input System Monitor differential auxiliary analog inputs 0–15.
function
VCCADC Dedicated N/A System Monitor analog positive supply voltage.
GNDADC Dedicated N/A System Monitor analog ground reference.
VREFP Dedicated N/A Voltage reference input.
VREFN Dedicated N/A Voltage reference GND.
System Monitor dedicated differential analog input
VP Dedicated Input
(positive side).
System Monitor dedicated differential analog input
VN Dedicated Input
(negative side).
I2C serial clock. Directly connected to the System Monitor
DRP interface for I2C operation configuration.

Multi-
I2C_SCLK Bidirectional
function IMPORTANT: Because the SYSMON I2C interface is
active after power-on, this pin should only be used for
I2C access until after configuration.

I2C serial data line. Directly connected to the System


Monitor DRP interface for I2C operation configuration.

Multi-
I2C_SDA Bidirectional
function IMPORTANT: Because the SYSMON I2C interface is
active after power-on, this pin should only be used for
I2C access until after configuration.

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Table 1-5: Pin Definitions (Cont’d)


Pin Name Type Direction Description
Optional PMBus alert, interrupt signal. When Low,
indicates a system fault that must be cleared using PMBus
commands. Connect to SMBALERT_TS.
For more information, see the UltraScale Architecture
System Monitor User Guide (UG580).

Multi-
SMBALERT Bidirectional
function IMPORTANT: By default, the PMBus is active prior to
configuration. Only use as a multi-functional I/O pin in
designs that can tolerated this pin being driven prior to
configuration.

This pin is present on Artix UltraScale+, Kintex


UltraScale+, and Virtex UltraScale+ devices.
Power/Ground Pins
For more information on voltage specifications see the UltraScale Device Data Sheets.
GND Dedicated N/A Ground.
VCCINT Dedicated N/A Power-supply pins for the internal logic.
Power-supply pins for the I/O banks. For Kintex and
UltraScale Architecture PCB and Pin Planning User Guide
devices, connect VCCINT_IO to VCCINT. For Kintex and
Virtex UltraScale+ devices, connect VCCINT_IO to
VCCINT_IO Dedicated N/A VCCBRAM. Both migration and lower voltage differences
(-1LI and -2LE at 0.72V) are discussed in the UltraScale
Architecture PCB Design Guide (UG583). See the
connection matrix in the Power Supply Voltage Levels and
VCCINT_IO Connection section.
VCCINT_GT_[L or R] Dedicated N/A GTM core power-supply pins.
VCCAUX Dedicated N/A Power-supply pins for auxiliary circuits.
Auxiliary power-supply pins for the I/O banks. VCCAUX_IO
must be connected to VCCAUX on the board.

VCCAUX_IO Dedicated N/A Note: Package files for XQ ruggedized Kintex and Virtex
UltraScale+devices (for example: FFRB676) have unique
pin names for VCCAUX_HPIO and VCCAUX_HDIO. These
pins can be connected to a common VCCAUX_IO supply.
VCCIO_HBM_[HBM bank
Dedicated N/A HBM component I/O power supply (VDDQ)
number]
VCC_HBM_[HBM bank
Dedicated N/A HBM component core power supply (VDDC)
number]
VCCAUX_HBM_[HBM
Dedicated N/A HBM component word line voltage pump (VPP)
bank number]
VCCBRAM Dedicated N/A Block RAM power supply pins.

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Table 1-5: Pin Definitions (Cont’d)


Pin Name Type Direction Description
Decryptor key memory backup supply; this pin should be
VBATT Dedicated N/A
tied to the appropriate V CC or GND when not used.
VCCO_[bank number] (4) Dedicated N/A Power-supply pins for the output drivers (per bank).
VREF_[bank number] Dedicated N/A These are input threshold voltage pins.
Reserved pins—must be tied to GND.
These pins are present on Artix UltraScale+, Kintex
UltraScale+, and Virtex UltraScale+ devices.

RSVDGND Dedicated N/A


TIP: In footprint compatible devices, this pin can be
labeled differently and serve different purposes. When
planning migration between devices, include the
functionality between all footprint compatible devices.

Reserved pins—leave floating.

RSVD Dedicated N/A TIP: In footprint compatible devices, this pin can be
labeled differently and serve different purposes. When
planning migration between devices, include the
functionality between all footprint compatible devices.

Multi-gigabit Serial Transceiver Pins (GTHE3 and GTYE3)


For more information on the GTH and GTY transceivers see the UltraScale Architecture GTH Transceivers User
Guide (UG576) or UltraScale Architecture GTY Transceivers User Guide (UG578).
MGTHRX[P or N][0 to 3]
Dedicated Input Differential receive port GTH Quad.
_[GT quad number]
MGTHTX[P or N][0 to 3]
Dedicated Output Differential transmit port GTH Quad.
_[GT quad number]
MGTYRX[P or N][0 to 3]
Dedicated Input Differential receive port GTY Quad.
_[GT quad number]
MGTYTX[P or N][0 to 3]
Dedicated Output Differential transmit port GTY Quad.
_[GT quad number]
MGTYRX[P or N][0 to 3]
Dedicated Input Differential receive port GTM Dual.
_[GT dual number]
MGTYTX[P or N][0 to 3]
Dedicated Output Differential transmit port GTM Dual.
_[GT dual number]
MGTAVCC_[L or R] Analog power-supply pin for the receiver and transmitter
Dedicated Input
[N, UC, C, LC, or S] (5) internal circuits.

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Table 1-5: Pin Definitions (Cont’d)


Pin Name Type Direction Description
MGTAVTT_[L or R]
Dedicated Input Analog power-supply pin for the transmit driver.
[N, UC, C, LC, or S] (5)
MGTVCCAUX_[L or R] Auxiliary analog Quad PLL (QPLL) voltage supply for the
Dedicated Input
[N, UC, C, LC, or S] (5) transceivers.
MGTREFCLK[0 or 1]
Dedicated Input Differential reference clock for the transceivers.
[P or N]
MGTAVTTRCAL_[L or R] Precision reference resistor pin for internal calibration
Dedicated N/A
[N, UC, C, LC, or S] (5) termination.
MGTRREF_[L or R] Precision reference resistor pin for internal calibration
Dedicated Input
[N, UC, C, LC, or S] (5) termination.

Notes:
1. See the DCI sections in UltraScale Architecture SelectIO Resources User Guide (UG571) for more information on the VRP pins.
2. All dedicated configuration pins are powered by V CCO_0.
3. See the UltraScale Architecture System Monitor User Guide (UG580) for the default connections required to support on-chip
monitoring.
4. V CCO pins in unbonded banks must be connected to the V CCO for that bank (for package migration). Do NOT connect
unbonded V CCO pins to different supplies. Without a package migration requirement, V CCO pins in unbonded banks can be
tied to a common supply (V CCO or GND).
5. L (left) or R (right) plus N (north), UC (upper center), C (center), LC (lower center), and S (south) signify the GT transceiver
quad power supply groups. For example, RUC signifies the right-upper-center power supply group and LLC signifies the
left-lower-center power supply group in the FLGA2577 package.

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Footprint Compatibility between Packages


UltraScale and UltraScale+ devices are footprint compatible only with other UltraScale and UltraScale+ devices with the same
number of package pins and the same preceding alphabetic designator. For example, XCKU060-FFVA1517 is compatible with
XCKU085-FLVA1517 and XCKU115-FLVA1517, but not with XCKU115-FLVD1517. Pins that are available in one device but are not
available in another device with a compatible package include the other device's name in the No Connect column of the
package file. These pins are labeled as No Connects in the other device's package file.

IMPORTANT: Footprint compatibility does not necessarily imply that all pins will function in the same manner for different devices in a
package. For limitations and guidelines on designing for footprint compatible packages, refer to the Migration Between UltraScale Devices and
Packages section of UltraScale Architecture PCB Design Guide (UG583).

Table 1-6 shows the footprint compatible devices available for each UltraScale and UltraScale+ device package. See UltraScale
Architecture and Product Overview (DS890) for specific package letter code options.

IMPORTANT: The height dimensions of footprint compatible packages can vary since some devices contain SSI technology.

Table 1-6: Footprint Compatibility


Packages Footprint Compatible Devices
A368 XCAU10P XCAU15P
B484 XCAU10P XCAU15P XAAU10P XAAU15P

C484 XCAU7P XAAU7P

A676 XCKU035 XCKU040 XQKU040 XCKU3P XCKU5P

B676 XCAU10P (2) XCAU15P(2) XCAU20P(2) XCAU25P (2) XAAU10P (2) XAAU15P(2) XCKU3P XCKU5P XQKU5P

A784 XCKU035 XCKU040

B784 XCAU20P XCAU25P XCKU3P XCKU5P XQKU5P

A900 XCKU035 XCKU040

D900 XCKU3P XCKU5P XCKU11P

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Table 1-6: Footprint Compatibility (Cont’d)


Packages Footprint Compatible Devices
E900 XCKU9P XCKU13P

A1156 XCKU025 XCKU035 XCKU040 XQKU040 XCKU060 XQKU060 XCKU095 XQKU095 XCKU11P XCKU15P XQKU15P

A1365 XCVU23P

A1517 XCKU060 XCKU085 XCKU115

C1517 XCKU095 XCVU065 XCVU080 XCVU095 XCVU3P XQVU3P

D1517 XCKU115 XQKU115 XCVU080 XCVU095 XCVU125

E1517 XCKU11P XCKU15P XQKU15P

A1760 XCKU15P

B1760 XCKU085 XCKU095 XCKU115 XCVU080 XCVU095 XCVU125


E1760 XCKU15P

J1760 XCKU19P XCVU23P

D1924 XCKU115
F1924 XCKU085 XCKU115 XQKU115 XCVU11P

H1924 XCVU31P

A2104 XCKU115 XCVU080 XCVU095 XCVU125 XCVU5P XCVU7P XCVU9P XCVU13P(1) XQVU7P
B2104 XCKU095 XCKU115 XCKU19P XCVU080 XCVU095 XCVU125 XCVU160 XCVU190 XCVU5P XCVU7P XCVU9P XCVU11P XCVU13P(1) XQVU7P

C2104 XCVU095 XCVU125 XCVU160 XCVU190 XCVU5P XCVU7P XCVU9P XCVU11P XCVU13P (1) XQVU11P

D2104 XCVU9P XCVU11P XCVU13P XCVU27P (1) XCVU29P (1)


H2104 XCVU33P XCVU35P XCVU45P

B2377 XCVU440

A2577 XCVU190 XCVU9P XCVU11P XCVU13P XCVU27P XCVU29P

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Table 1-6: Footprint Compatibility (Cont’d)


Packages Footprint Compatible Devices
A2892 XCVU440

H2892 XCVU35P XCVU37P XCVU45P XCVU47P

K2892 XCVU57P

A3824 XCVU19P

B3824 XCVU19P

Notes:
1. While footprint compatible, the body size for the VU13P, VU27P, and VU39P is 52.5 mm, which is larger than the 47.5 mm for a 2104 ball package.
2. While footprint compatible, incompatibilities exist between banks 85/86 (AU10P and AU15P) and 86/87 (AU20P and AU25P) with regards to the System Monitor analog
inputs (AD pins). This incompatibility should be considered when designing for migration between these devices.

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Many UltraScale and UltraScale+ devices that are footprint compatible in a package have different I/O bank and transceiver
quad numbers connected to the same package pins. Due to these differences, when migrating between devices in a specific
package, the type of bank (HP vs. HR) or quad (GTH vs. GTY), whether a bank is connected or NC at the package pins, and where
the bank or quad is located on the die must be taken into consideration. Table 1-7 and Table 1-9 show how the banks and
transceiver quads are numbered between devices in each package.

For all grouped-together footprint compatible packages, the bank and quad numbers in the same column for each device are
connect to the same package pins. For example, in the FFVD1517 and FLVD1517 packages, bank 69 for the XCVU095 is
connected to the same pins as bank 71 for the XCVU125.

A limited number of banks have fewer than 52 SelectIO pins. For a visual representation of all of this information, see the Die
Level Bank Numbering Overview section.

Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray(1)
Package to Device I/O Mapping
Package Device Unbonded I/O Banks
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC
XCAU10P 84 65 66 64, 85, 86
UBVA368
XCAU15P 84 65 66 64, 85, 86

XCAU10P 64 65 66 84 85 86

XAAU10P 64 65 66 84 85 86
SBVB484
XCAU15P 64 65 66 84 85 86
XAAU15P 64 65 66 84 85 86

XCAU7P 65 66 84 85 86 104 105 106 86


SBVC484
XAAU7P 65 66 84 85 86 104 105 106 86

XCKU035 65 66 44 45 46 64 47, 48, 67, 68


FBVA676
XCKU040 65 66 44 45 46 64 47, 48, 67, 68

RBA676 XQKU040 65 66 44 45 46 64 47, 48, 67, 68


XCKU3P 65 66 64 67 84/85 86, 87
FFVA676
XCKU5P 65 66 64 67 84/85 86, 87

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Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray(1) (Cont’d)
Package to Device I/O Mapping
Package Device Unbonded I/O Banks
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC
XCAU10P (2) 84 64 65 66 85 86

XAAU10P (2) 84 64 65 66 85 86

XCAU15P (2) 84 64 65 66 85 86

XAAU15P (2) 84 64 65 66 85 86
FFVB676
XCAU20P (2) 84 64 65 66 86 87 67, 85

XCAU25P (2) 84 64 65 66 67 86 87 85

XCKU3P 84 64 65 66 67 86 87 85

XCKU5P 84 64 65 66 67 86 87 85

FFRB676 XQKU5P 84 64 65 66 67 86 87 85

XCKU035 65 44 45 46 47 66 68 67 64 48
SFVA784
XCKU040 65 44 45 46 47 66 68 67 64 48

XCAU20P 64 65 66 86 84 85 67, 87
XCAU25P 64 65 66 67 87 86 84 85
SFVB784
XCKU3P 64 65 66 67 87 86 84 85

XCKU5P 64 65 66 67 87 86 84 85
SFRB784 XQKU5P 64 65 66 67 87 86 84 85

XCKU035 65 66 67 44 45 46 47 48 64 68
FBVA900
XCKU040 65 66 67 44 45 46 47 48 64 68

XCKU3P 65 66 64 67 84 85 87 86

FFVD900 XCKU5P 65 66 64 67 84 85 87 86

XCKU11P 65 66 67 68 69 70 88 89 91 90 71, 64

XCKU9P 64 65 66 67 44 47 48 49 50
FFVE900
XCKU13P 64 65 66 67 44 47 48 49 50

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Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray(1) (Cont’d)
Package to Device I/O Mapping
Package Device Unbonded I/O Banks
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC
XCKU025 65 66 44 45 46 64

XCKU035 65 66 67 68 44 45 46 47 48 64

XCKU040 65 66 67 68 44 45 46 47 48 64

FFVA1156 XCKU060 65 66 67 68 44 45 46 47 48 64 24, 25

XCKU095 65 66 68 67 45 44 46 47 48 64 49, 50, 51, 69, 70, 71

XCKU11P 65 66 70 71 67 64 68 69 88/89 90, 91

XCKU15P 65 66 71 72 67 64 68 69 70 90/91 73, 74, 93, 94

FFRA1156 XQKU15P 65 66 71 72 67 64 68 69 70 90/91 73, 74, 93, 94

XQKU040 65 66 67 68 44 45 46 47 48 64
RFA1156 XQKU060 65 66 67 68 44 45 46 47 48 64 24, 25

XQKU095 65 66 68 67 45 44 46 47 48 64 49, 50, 51, 69, 70, 71

VSVA1365 XCVU23P 65 66 67 68 72 73 74 71, 70, 69, 64, 92, 90, 88

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Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray(1) (Cont’d)
Package to Device I/O Mapping
Package Device Unbonded I/O Banks
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC
FFVA1517 XCKU060 65 44 45 24 25 66 67 68 46 47 48 64

29, 30, 49, 50, 51, 52, 69, 70,


XCKU085 65 44 45 24 25 66 67 68 46 47 48 64
71, 72
FLVA1517
29, 30, 49, 50, 51, 52, 69, 70,
XCKU115 65 44 45 24 25 66 67 68 46 47 48 64
71, 72

XCKU095 84/94 65 66 67 68 44 45 46 47 48 51, 50, 49, 71, 70, 69

XCVU080 84/94 65 66 67 68 44 45 46 47 48 51, 50, 49, 71, 70, 69

FFVC1517 XCVU065 84/94 65 66 67 68 44 45 46 47 48

XCVU095 84/94 65 66 67 68 44 45 46 47 48 51, 50, 49, 71, 70, 69


XCVU3P 64 65 66 67 68 44 45 46 47 48

FFRC1517 XQVU3P 64 65 66 67 68 44 45 46 47 48

44, 45, 46, 47, 48, 49, 50, 51,


XCVU080 84/94 65 66 67 (3) 69 70 71
68
FFVD1517
44, 45, 46, 47, 48, 49, 50, 51,
XCVU095 84/94 65 66 67 (3) 69 70 71
68

24, 25, 29, 30, 44, 45, 46, 47,


XCKU115 84/94 65 66 67 (3) 71 72 73 48, 49, 50, 51, 52, 53, 68, 69,
FLVD1517 70

44, 45, 46, 47, 48, 49, 50, 51,


XCVU125 84/94 65 66 67 (3) 71 72 73
52, 53, 68, 69, 70

24, 25, 29, 30, 44, 45, 46, 47,


RLD1517 XQKU115 84/94 65 66 67 (3) 71 72 73 48, 49, 50, 51, 52, 53, 68, 69,
70

XCKU11P 65 64 66 67 68 91 90 89 88 71 70 69
FFVE1517
XCKU15P 65 64 66 67 68 94 93 91 90 71 70 69 74, 73, 72

FFRE1517 XQKU15P 65 64 66 67 68 94 93 91 90 71 70 69 74, 73, 72

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Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray(1) (Cont’d)
Package to Device I/O Mapping
Package Device Unbonded I/O Banks
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC
FFVA1760 XCKU15P 65 64 66 67 68 94 93 91 90 72 71 70 74, 73, 69

24, 25, 29, 30, 68, 69, 70, 71,


XCKU085 84/94 65 66 67 44 45 46 47 48 49 50 51 52
72
FLVB1760
24, 25, 29, 30, 68, 69, 70, 71,
XCKU115 84/94 65 66 67 44 45 46 47 48 49 50 51 52 53 (3)
72, 73
XCKU095 84/94 65 66 67 44 45 46 47 48 70 71 49 50 51 (3) 68, 69

FFVB1760 XCVU080 84/94 65 66 67 44 45 46 47 48 70 71 49 50 51 (3) 68, 69

XCVU095 84/94 65 66 67 44 45 46 47 48 70 71 49 50 51 (3) 68, 69

FLVB1760 XCVU125 84/94 65 66 67 44 45 46 47 48 49 50 51 52 53 (3) 68, 69, 70, 71, 72, 73

FFVE1760 XCKU15P 65 64 66 67 68 69 94 93 91 90 74 73 72 71 70

FFVJ1760 XCKU19P 65 66 67 68 69 88 90 92 70 71 72 73 74, 64

FSVJ1760 XCVU23P 64 65 66 67 68 69 88 90 92 70 71 72 73 74

FLVD1924 XCKU115 84/94 65 66 67 44 45 46 47 50 51 52 53 70 71 72 73 24, 25, 29, 30, 48, 49, 68, 69

30, 29, 25, 24, 50, 49, 48, 47,


XCKU085 65 66 67 68 44 45 46 51 52 70 71 72
69, 64
FLVF1924
30, 29, 25, 24, 50, 49, 48, 47,
XCKU115 65 66 67 68 44 45 46 51 52 53 70 71 72 73
69, 64

30, 29, 25, 24, 50, 49, 48, 47,


RLF1924 XQKU115 65 66 67 68 44 45 46 51 52 53 70 71 72 73
69, 64

FLGF1924 XCVU11P 65 66 67 68 64 69 70 71 72 73 74 75

FSVH1924 XCVU31P 64 65 66 67

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Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray(1) (Cont’d)
Package to Device I/O Mapping
Package Device Unbonded I/O Banks
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC
XCVU080 84/94 65 66 67 44 45 46 47 48 49 50 51 68 69 70 71
FFVA2104
XCVU095 84/94 65 66 67 44 45 46 47 48 49 50 51 68 69 70 71

XCKU115 84/94 65 66 67 44 45 46 47 50 51 52 53 70 71 72 73 30, 29, 25, 24, 49, 48, 69, 68

XCVU125 84/94 65 66 67 44 45 46 47 50 51 52 53 70 71 72 73 49, 48, 69, 68


FLVA2104
XCVU5P 64 65 66 67 44 45 46 47 50 51 52 53 70 71 72 73 49, 48, 69, 68

XCVU7P 64 65 66 67 44 45 46 47 50 51 52 53 70 71 72 73 49, 48, 69, 68

FLRA2104 XQVU7P 64 65 66 67 44 45 46 47 50 51 52 53 70 71 72 73 49, 48, 69, 68

53, 52, 51, 50, 49, 44, 39, 69,


FLGA2104 XCVU9P 64 65 66 67 40 41 42 43 45 46 47 48 70 71 72 73
68, 63, 62, 61, 60, 59

FHGA2104 XCVU13P 64 65 66 67 60 61 62 63 68 69 70 71 72 73 74 75

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Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray(1) (Cont’d)
Package to Device I/O Mapping
Package Device Unbonded I/O Banks
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC
XCKU095 84/94 65 66 67 68 (3) 44 45 46 49 50 51 69 70 71 48, 47

XCVU080 84/94 65 66 67 68 (3) 44 45 46 49 50 51 69 70 71 48, 47


FFVB2104
XCVU095 84/94 65 66 67 68 (3) 44 45 46 49 50 51 69 70 71 48, 47

XCKU19P 90/92 65 66 67 88 73 72 71 68 69 70 74, 64

30, 29, 25, 24, 50, 49, 48, 47,


XCKU115 84/94 65 66 67 68 (3) 44 45 46 51 52 53 71 72 73
70, 69

FLVB2104 XCVU125 84/94 65 66 67 68 (3) 44 45 46 50 51 52 70 71 72 53, 49, 48, 47, 73, 69

XCVU5P 64 65 66 67 68 (3) 44 45 46 50 51 52 70 71 72 53, 49, 48, 47, 73, 69

XCVU7P 64 65 66 67 68 (3) 44 45 46 50 51 52 70 71 72 53, 49, 48, 47, 73, 69


FLRB2104 XQVU7P 64 65 66 67 68 (3) 44 45 46 50 51 52 70 71 72 53, 49, 48, 47, 73, 69

53, 49, 48, 47, 43, 42, 41, 40,


XCVU160 84/94 65 66 67 68 (3) 44 45 46 50 51 52 70 71 72
73, 69, 63, 62, 61, 60

53, 49, 48, 47, 43, 42, 41, 40,


XCVU190 84/94 65 66 67 68 (3) 44 45 46 50 51 52 70 71 72
FLGB2104 39, 73, 69, 63, 62, 61, 60, 59

53, 52, 51, 50, 49, 45, 44, 43,


XCVU9P 64 65 66 67 68 (3) 40 41 42 46 47 48 70 71 72
39, 73, 69, 63, 62, 61, 60, 59

XCVU11P 64 65 66 67 68 69 70 71 72 73 74 75

FHGB2104 XCVU13P 64 65 66 67 68 (3) 61 62 63 69 70 71 72 73 74 75, 60

UltraScale Device Packaging and Pinouts 41


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray(1) (Cont’d)
Package to Device I/O Mapping
Package Device Unbonded I/O Banks
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC
FFVC2104 XCVU095 84/94 65 66 67 68 69 70 71 51, 50, 49, 48, 47, 46, 45, 44

53, 52, 51, 50, 49, 48, 47, 46,


XCVU125 84/94 65 66 67 68 70 71 72
45, 44, 73, 69

53, 52, 51, 50, 49, 48, 47, 46,


FLVC2104 XCVU5P 64 65 66 67 68 70 71 72
45, 44, 73, 69
53, 52, 51, 50, 49, 48, 47, 46,
XCVU7P 64 65 66 67 68 70 71 72
45, 44, 73, 69

52, 51, 50, 49, 48, 47, 46, 45,


XCVU160 84/94 65 66 67 68 70 71 72 44, 43, 42, 41, 40, 69, 63, 62,
61, 60

53, 52, 51, 50, 49, 48, 47, 46,


XCVU190 84/94 65 66 67 68 70 71 72 45, 44, 43, 42, 41, 40, 39, 73,
FLGC2104 69, 63, 62, 61, 60, 59

53, 52, 51, 50, 49, 48, 47, 46,


XCVU9P 64 65 66 67 68 70 71 72 45, 44, 43, 42, 41, 40, 39, 73,
69, 63, 62, 61, 60, 59

XCVU11P 64 65 66 67 68 69 70 71 75, 74, 73, 72

FLRC2104 XQVU11P 64 65 66 67 68 69 70 71 75, 74, 73, 72

FHGC2104 XCVU13P 64 65 66 67 68 69 70 71 75, 74, 73, 72, 63, 62, 61, 60

53, 52, 51, 50, 49, 45, 44, 43,


XCVU9P 64 65 66 67 40 41 42 46 47 48 70 71 72 39, 73, 69, 68, 63, 62, 61, 60,
FSGD2104 59

XCVU11P 64 65 66 67 68 69 70 71 72 73 74 75

XCVU13P 64 65 66 67 61 62 63 69 70 71 72 73 74 75, 68, 60


FIGD2104 XCVU27P 64 65 66 67 61 62 63 69 70 71 72 73 74 75, 68, 60

XCVU29P 64 65 66 67 61 62 63 69 70 71 72 73 74 75, 68, 60

XCVU33P 64 65 66 67
FSVH2104 XCVU35P 64 65 66 67 68 69 70 71

XCVU45P 64 65 66 67 68 69 70 71

UltraScale Device Packaging and Pinouts 42


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-7: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray(1) (Cont’d)
Package to Device I/O Mapping
Package Device Unbonded I/O Banks
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC
FLGB2377 XCVU440 84/94 65 66 67 68 60 61 62 63 40 41 42 43 45 46 47 48 50 51 52 53 70 71 72 73 39, 44, 49, 59, 69

53, 52, 51, 50, 49, 48, 47, 46,


XCVU190 66 (3) 65 61 62 63 67 68 (3) 70 71 72 45, 44, 43, 42, 41, 40, 39, 73,
69, 64, 60, 59

53, 52, 51, 50, 49, 48, 47, 46,


FLGA2577 XCVU9P 66 (3) 65 61 62 63 67 68 (3) 70 71 72 45, 44, 43, 42, 41, 40, 39, 73,
69, 64, 60, 59

XCVU11P 66 (3) 65 68 69 70 71 72 (3) 73 74 75 67, 64

XCVU13P 66 (3) 65 61 62 63 70 71 (3) 73 74 75 72, 69, 68, 67, 64, 60


XCVU13P 66 (3) 65 61 62 63 70 71 (3) 73 74 75 72, 69, 68, 67, 64, 60

FSGA2577 XCVU27P 66 (3) 65 61 62 63 70 71 (3) 73 74 75 72, 69, 68, 67, 64, 60

XCVU29P 66 (3) 65 61 62 63 70 71 (3) 73 74 75 72, 69, 68, 67, 64, 60

FLGA2892 XCVU440 84/94 65 66 67 68 60 61 62 63 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 70 71 72 73 59, 69

XCVU35P 64 65 66 67 68 69 70 71

XCVU37P 64 65 66 67 68 69 70 71 72 73 74 75
FSVH2892
XCVU45P 64 65 66 67 68 69 70 71

XCVU47P 64 65 66 67 68 69 70 71 72 73 74 75

FSVK2892 XCVU57P 64 65 66 67 68 69 75 74 73 70 71 72

Notes:
1. See the Die Level Bank Numbering Overview for specific changes in column numbering.
2. While footprint compatible, incompatibilities exist between banks 85/86 (AU10P and AU15P) and 86/87 (AU20P and AU25P) with regards to the System Monitor analog
inputs (AD pins). This incompatibility should be considered when designing for migration between these devices.
3. A limited number of banks have fewer than 52 SelectIO pins. These banks are labeled as partial.

UltraScale Device Packaging and Pinouts 43


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-8: I/O Bank Migration for VU19P devices: HP I/O Banks are Unshaded and HD I/O Banks are in Dark Gray
Package to Device I/O Mapping Unbonded I/O
Package Device
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP Banks
FSVA3824 XCVU19P 59 60 65 61 62 63 64 66 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 69 70 71 72 73 74 75 76 77 78 98 93 88 83 68, 67

FSVB3824 XCVU19P 60 61 65 62 66 67 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 70 71 72 75 76 77 98 93 88 83 78, 74, 73, 69, 68, 64, 63, 59

UltraScale Device Packaging and Pinouts 44


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

For each grouped set of footprint compatible packages listed in Table 1-9, there is a row detailing the power supply group for
each quad. These groups are labeled according to the regions for the transceiver power supply pins, as listed in the ASCII
Pinout Files linked from Chapter 2, Package Files. For a visual representation of all of this information, see the Die Level Bank
Numbering Overview section.

Table 1-9: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray)
Package to Device Transceiver Mapping Unbonded
Package Device
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF GT Quads
Power Supply Group R

XCAU10P 224 225 226


UBVA368
XCAU15P 224 225 226

Power Supply Group R

XCAU10P 224 225 226


XAAU10P 224 225 226
SBVB484
XCAU15P 224 225 226

XAAU15P 224 225 226

Power Supply Group R

XCAU7P 124
SBVC484
XAAU7P 124
Power Supply Group —

XCAU10P 224 225 226


FFVB676
XCAU15P 224 225 226
Power Supply Group —

XCKU035 224 225 226 227 228


FBVA676
XCKU040 224 225 226 227 228
RBA676 XQKU040 224 225 226 227 228

Power Supply Group R

XCKU3P 224 225 226 227


FFVA676
XCKU5P 224 225 226 227

UltraScale Device Packaging and Pinouts 45


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-9: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package to Device Transceiver Mapping Unbonded
Package Device
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF GT Quads
Power Supply Group R
XCAU10P 224 225 226

XAAU10P 224 225 226

XCAU15P 224 225 226

XAAU15P 224 225 226


FFVB676
XCAU20P 224 225 226 227

XCAU25P 224 225 226 227

XCKU3P 224 225 226 227

XCKU5P 224 225 226 227

FFRA676 XQKU5P 224 225 226 227

Power Supply Group —

XCKU035 224 225 228,227,226


SFVA784
XCKU040 224 225 228,227,226

Power Supply Group R

XCAU20P 224 225 226

XCAU25P 224 225 226


SFVB784
XCKU3P 224 225 226 227

XCKU5P 224 225 226 227

SFRB784 XQKU5P 224 225 226 227

UltraScale Device Packaging and Pinouts 46


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-9: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package to Device Transceiver Mapping Unbonded
Package Device
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF GT Quads
Power Supply Group —

XCKU035 224 225 226 227 228


FBVA900
XCKU040 224 225 226 227 228

Power Supply Group R

XCKU3P 224 225 226 227

XCKU5P 224 225 226 227


FFVD900
131, 130, 129,
XCKU11P 224 225 226 227 128, 127, 231,
230, 229, 228

Power Supply Group R L

XCKU9P 228 229 230 127 128 129 130


FFVE900
XCKU13P 228 229 230 127 128 129 130

UltraScale Device Packaging and Pinouts 47


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-9: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package to Device Transceiver Mapping Unbonded
Package Device
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF GT Quads
Power Supply Group R L

XCKU025 224 225 226

XCKU035 224 225 226 227 228

XCKU040 224 225 226 227 228

XCKU060 224 225 226 227 228 127 128 126

131, 128, 127,


FFVA1156 XCKU095 224 225 226 227 228 129 130 126, 125, 124,
231, 230, 229

131, 128, 127,


XCKU11P 224 225 226 227 228 129 130
231, 230

134, 133, 132,


131, 128, 127,
XCKU15P 224 225 226 227 228 129 130
234, 233, 232,
231, 230, 229

134, 133, 132,


131, 128, 127,
FFRA1156 XQKU15P 224 225 226 227 228 129 130
234, 233, 232,
231, 230, 229

XQKU040 224 225 226 227 228

XQKU060 224 225 226 227 228 127 128 126


RFA1156
131, 128, 127,
XQKU095 224 225 226 227 228 129 130 126, 125, 124,
231, 230, 229

Power Supply Group RS RC RN

VSVA1365 XCVU23P 224 225 226 227 228 229 230 231 232 233 234

UltraScale Device Packaging and Pinouts 48


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-9: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package to Device Transceiver Mapping Unbonded
Package Device
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF GT Quads
Power Supply Group RS RN L

FFVA1517 XCKU060 224 225 226 227 228 126 127 128

XCKU085 224 225 226 227 228 229 230 231 232 126 127 128 132,131
FLVA1517
XCKU115 224 225 226 227 228 229 230 231 232 126 127 128 132,131

Power Supply Group R L

131, 130, 124,


XCKU095 224 225 226 227 228 125 126 127 128 129
231, 230, 229

131, 130, 124,


XCVU080 224 225 226 227 228 125 126 127 128 129
231, 230, 229
FFVC1517
XCVU065 224 225 226 227 228 124 125 126 127 128

131, 130, 124,


XCVU095 224 225 226 227 228 125 126 127 128 129
231, 230, 229

XCVU3P 224 225 226 227 228 124 125 126 127 128

FFRC1517 XQVU3P 224 225 226 227 228 124 125 126 127 128

Power Supply Group RS RN LS LN

XCVU080 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131
FFVD1517
XCVU095 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131
XCVU125 224 225 226 227 228 229 230 231 232 233 124 125 126 127 129 130 131 132 133,128
FLVD1517
XCKU115 224 225 226 227 228 229 230 231 232 233 126 127 128 131 132 133

RLD1517 XQKU115 224 225 226 227 228 229 230 231 232 233 126 127 128 131 132 133

Power Supply Group RS RN L

XCKU11P 224 225 226 227 228 229 230 231 127 128 129 130 131
FFVE1517 134, 133, 234,
XCKU15P 224 225 226 227 228 229 230 231 127 128 129 130 131 132
233, 232

134, 133, 234,


FFRE1517 XQKU15P 224 225 226 227 228 229 230 231 127 128 129 130 131 132
233, 232

UltraScale Device Packaging and Pinouts 49


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-9: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package to Device Transceiver Mapping Unbonded
Package Device
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF GT Quads
Power Supply Group RS RN LS LN

FFVA1760 XCKU15P 224 225 226 227 228 229 230 231 232 233 234 127 128 129 130 131 132 133 134

Power Supply Group RS RN L

XCKU085 224 225 226 227 228 230 231 232 128 131 132 127,126,229
FLVB1760
XCKU115 224 225 226 227 228 230 231 232 233 128 131 132 133 127,126,229

127,126,125,1
XCKU095 224 225 226 227 228 229 230 231 128 129 130 131
24

127,126,125,1
FFVB1760 XCVU080 224 225 226 227 228 229 230 231 128 129 130 131
24

127,126,125,1
XCVU095 224 225 226 227 228 229 230 231 128 129 130 131
24

133, 128, 127,


FLVB1760 XCVU125 224 225 226 227 228 230 231 232 233 129 130 131 132
126, 125, 229

Power Supply Group RS RN L

134, 133, 234,


FFVE1760 XCKU15P 224 225 226 227 228 229 230 231 127 128 129 130 131 132
233, 232

Power Supply Group RS RC RN

FFVJ1760 XCKU19P 225 226 227 228 229 230 231 232

FSVJ1760 XCVU23P 224 225 226 227 228 229 230 231 232 233 234

UltraScale Device Packaging and Pinouts 50


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-9: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package to Device Transceiver Mapping Unbonded
Package Device
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF GT Quads
Power Supply Group RS RN LS LN

FLVD1924 XCKU115 224 225 226 227 231 232 233 126 127 128 131 132 133 230,229,228

Power Supply Group RS RN LS LN

XCKU085 224 225 226 227 228 229 230 231 232 126 127 128 131 132
FLVF1924
XCKU115 224 225 226 227 228 229 230 231 232 233 126 127 128 131 133 132

RLF1924 XQKU115 224 225 226 227 228 229 230 231 232 233 126 127 128 131 133 132

135, 134, 133,


FLGF1924 XCVU11P 224 225 226 227 228 229 230 231 232 233 125 126 127 129 131 130 132, 128, 124,
235, 234

Power Supply Group R L

FSVH1924 XCVU31P 224 225 226 227 124 125 126 127

UltraScale Device Packaging and Pinouts 51


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-9: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package to Device Transceiver Mapping Unbonded
Package Device
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF GT Quads
Power Supply Group RS RN LS LN

XCVU080 224 225 226 227 228 229 230 125 126 127 128 129 130 131, 124, 231
FFVA2104
XCVU095 224 225 226 227 228 229 230 125 126 127 128 129 130 131, 124, 231

XCKU115 224 225 226 227 231 232 233 126 127 128 131 132 133 230, 229, 228

133, 129, 128,


XCVU125 224 225 226 227 231 232 233 125 126 127 130 131 132 124, 230, 229,
228

FLVA2104 133, 129, 128,


XCVU5P 224 225 226 227 231 232 233 125 126 127 130 131 132 124, 230, 229,
228

133, 129, 128,


XCVU7P 224 225 226 227 231 232 233 125 126 127 130 131 132 124, 230, 229,
228

133, 129, 128,


FLRA2104 XQVU7P 224 225 226 227 231 232 233 125 126 127 130 131 132 124, 230, 229,
228

133, 132, 131,


130, 129, 128,
124, 123, 119,
FLGA2104 XCVU9P 224 225 226 227 231 232 233 120 121 122 125 126 127
230, 229, 228,
223, 222, 221,
220, 219

135, 134, 133,


132, 128, 124,
123, 122, 121,
FHGA2104 XCVU13P 224 225 226 227 229 230 231 125 126 127 129 130 131 120, 235, 234,
233, 232, 228,
223, 222, 221,
220

UltraScale Device Packaging and Pinouts 52


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-9: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package to Device Transceiver Mapping Unbonded
Package Device
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF GT Quads
Power Supply Group RS RN LS LN

XCKU095 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131

XCVU080 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131
FFVB2104
XCVU095 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131

XCKU19P 225 226 227 228 229 230 231 232

XCKU115 224 225 226 227 228 229 230 231 232 233 126 127 128 131 132 133

XCVU125 224 225 226 227 228 229 230 231 232 233 125 126 127 128 129 130 131 132 133 124
FLVB2104
XCVU5P 224 225 226 227 228 229 230 231 232 233 125 126 127 128 129 130 131 132 133 124
XCVU7P 224 225 226 227 228 229 230 231 232 233 125 126 127 128 129 130 131 132 133 124

FLRB2104 XQVU7P 224 225 226 227 228 229 230 231 232 233 125 126 127 128 129 130 131 132 133 124

124, 123, 122,


XCVU160 224 225 226 227 228 229 230 231 232 233 125 126 127 128 129 130 131 132 133 121, 120, 223,
222, 221, 220

124, 123, 122,


121, 120, 119,
XCVU190 224 225 226 227 228 229 230 231 232 233 125 126 127 128 129 130 131 132 133
223, 222, 221,
FLGB2104 220, 219

133, 132, 131,


130, 129, 119,
XCVU9P 224 225 226 227 228 229 230 231 232 233 120 121 122 123 124 125 126 127 128
223, 222, 221,
220, 219

135, 134, 132,


XCVU11P 224 225 226 227 228 229 230 231 232 233 124 125 126 127 128 129 130 131 133
235, 234

135, 134, 132,


123, 122, 121,
FHGB2104 XCVU13P 224 225 226 227 228 229 230 231 232 233 124 125 126 127 128 129 130 131 133 120, 235, 234,
223, 222, 221,
220

UltraScale Device Packaging and Pinouts 53


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-9: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package to Device Transceiver Mapping Unbonded
Package Device
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF GT Quads
Power Supply Group RC RN RS LC LN LS

FFVC2104 XCVU095 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131

XCVU125 224 225 226 227 228 229 230 231 232 233 124 125 126 127 128 129 130 131 132 133

FLVC2104 XCVU5P 224 225 226 227 228 229 230 231 232 233 124 125 126 127 128 129 130 131 132 133

XCVU7P 224 225 226 227 228 229 230 231 232 233 124 125 126 127 128 129 130 131 132 133

XCVU160 224 225 226 227 228 229 230 231 232 233 220 221 222 124 125 126 127 128 129 130 131 132 133 120 121 122 123, 223

123, 119, 223,


XCVU190 224 225 226 227 228 229 230 231 232 233 220 221 222 124 125 126 127 128 129 130 131 132 133 120 121 122
219
FLGC2104
123, 119, 223,
XCVU9P 224 225 226 227 228 229 230 231 232 233 220 221 222 124 125 126 127 128 129 130 131 132 133 120 121 122
219

XCVU11P 226 227 228 229 230 231 232 233 234 235 224 225 126 127 128 129 130 131 132 133 134 135 124 125
FLRC2104 XQVU11P 226 227 228 229 230 231 232 233 234 235 224 225 126 127 128 129 130 131 132 133 134 135 124 125

135, 134, 120,


FHGC2104 XCVU13P 224 225 226 227 228 229 230 231 232 233 221 222 223 124 125 126 127 128 129 130 131 132 133 121 122 123
235, 234, 220

UltraScale Device Packaging and Pinouts 54


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-9: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package to Device Transceiver Mapping Unbonded
Package Device
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF GT Quads
Power Supply Group RS RN LS LN
133, 132, 130,
129, 128, 119,
XCVU9P 224 225 226 227 228 229 230 231 232 233 120 121 122 123 124 125 126 127 131
223, 222, 221,
FSGD2104 220, 219

135, 134,
XCVU11P 224 225 226 227 228 229 230 231 232 233 124 125 126 127 128 129 130 131 133
132, 235, 234

135, 134, 132,


127, 126, 125,
XCVU13P 224 225 226 227 228 229 230 231 232 233 120 121 122 123 128 129 130 131 133 124, 235, 234,
223, 222, 221,
220

135, 134, 132,


127, 126, 125,
FIGD2104 XCVU27P 224 225 226 227 228 229 230 231 232 233 120 121 122 123 128 129 130 131 133 124, 235, 234,
223, 222, 221,
220

135, 134, 132,


127, 126, 125,
XCVU29P 224 225 226 227 228 229 230 231 232 233 120 121 122 123 128 129 130 131 133 124, 235, 234,
223, 222, 221,
220

Power Supply Group RS RN LS LN

XCVU33P 224 225 226 227 124 125 126 127

FSVH2104 XCVU35P 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131

XCVU45P 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131

Power Supply Group RC RN RS

233, 232, 231,


FLGB2377 XCVU440 224 225 226 231 232 233 221 222 223 226, 225, 224,
223, 222, 221

UltraScale Device Packaging and Pinouts 55


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Table 1-9: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) (Cont’d)
Package to Device Transceiver Mapping Unbonded
Package Device
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF GT Quads
Power Supply Group RLC RUC RN RS RLC LLC LUC LN LS LLC

XCVU190 224 225 226 227 228 229 230 231 232 233 219 220 221 222 223 124 125 126 127 128 129 130 131 132 133 119 120 121 122 123

XCVU9P 224 225 226 227 228 229 230 231 232 233 219 220 221 222 223 124 125 126 127 128 129 130 131 132 133 119 120 121 122 123
FLGA2577
XCVU11P 225 226 227 228 229 230 231 232 233 234 235 224 125 126 127 128 129 130 131 132 133 134 135 124

XCVU13P 225 226 227 228 229 230 231 232 233 234 235 220 221 222 223 224 125 126 127 128 129 130 131 132 133 134 135 120 121 122 123 124

XCVU13P 225 226 227 228 229 230 231 232 233 234 235 220 221 222 223 224 125 126 127 128 129 130 131 132 133 134 135 120 121 122 123 124

FSGA2577 XCVU27P 225 226 227 228 229 230 231 232 233 234 235 220 221 222 223 224 125 126 127 128 129 130 131 132 133 134 135 120 121 122 123 124

XCVU29P 225 226 227 228 229 230 231 232 233 234 235 220 221 222 223 224 125 126 127 128 129 130 131 132 133 134 135 120 121 122 123 124

Power Supply Group RC RN RS

FLGA2892 XCVU440 224 225 226 227 229 230 231 232 219 220 221 222 233, 228, 223

Power Supply Group RS RC RN LS LC LN

XCVU35P 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131

XCVU37P 224 225 226 227 228 229 230 231 232 233 234 235 124 125 126 127 128 129 130 131 132 133 134 135
FSVH2892
XCVU45P 224 225 226 227 228 229 230 231 124 125 126 127 128 129 130 131
XCVU47P 224 225 226 227 228 229 230 231 232 233 234 235 124 125 126 127 128 129 130 131 132 133 134 135

Power Supply Group RS RC RN LS LC LN

FSVK2892 XCVU57P 224 225 226 227 228 229 230 231 232 233 234 235 124 125 126 127 128 129 130 131 132 133 134 135

Power Supply Group RLC RUC RN RS

238, 234, 233,


FSVA3824 XCVU19P 225 226 227 230 231 232 235 236 237 220 221 222 229, 228, 224,
223, 219

Power Supply Group RLC RUC RN RS

FSVB3824 XCVU19P 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 219 220 221 222 223

UltraScale Device Packaging and Pinouts 56


UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

Die Level Bank Numbering Overview


Banking and Clocking Summary
• For each device, not all banks are bonded out in every package.

GTH/GTY/GTM Columns
• One GTH/GTY Quad = Four transceivers = Four GTHE3 or GTYE3 primitives.
• One GTM Dual = Two transceivers = Two GTME3 primitives
• Not all GT Quads/Duals are bonded out in every package.
• Also shown are quads/duals labeled with RCAL. This specifies the location of the RCAL
masters for each device. With respect to the package, the RCAL masters are located on
the same package pin for each package, regardless of the device.
• The XY coordinates shown in each quad/dual correspond to the transceiver channel
number found in the pin names for that quad/dual, as shown in Figure 1-1.
• An alphabetic designator is shown in each quad/dual. Each letter corresponds to the
columns in Table 1-7 and Table 1-9.
• The power supply group is shown in brackets [ ] for each quad/dual.

I/O Banks
• Each user I/O bank has a total of 52 I/Os where 48 can be used as differential
(24 differential pairs) or single-ended I/Os. The remaining four function only as
single-ended I/Os. All 52 pads of a bank are not always bonded out to pins.
• A limited number of banks have fewer than 52 SelectIO pins. These banks are labeled as
partial.
• Adjacent to each bank is a physical layer (PHY) containing a CMT and other clock
resources.
• Adjacent to each bank and PHY is a tile of logic resources that makes up a clock region.
• Banks are arranged in columns and separated into rows which are pitch-matched with
adjacent PHY, clock regions, and GT blocks.
• An alphabetic designator is shown in each bank. Each letter corresponds to the
columns in Table 1-7 and Table 1-9.

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Clocking
• Each bank has four pairs of global clock (GC) inputs for four differential or four
single-ended clock inputs. Single-ended clock inputs should be connected to the P side
of the differential pair.
• Clock signals are distributed through global buffers driving routing and distribution
networks to reach any clock region, I/O, or GT.
• Global clock inputs can connect to an MMCM and two PLLs within the horizontally
adjacent CMT.

Bank Locations of Dedicated and Multi-Function Pins


• In all UltraScale and UltraScale+ devices, bank 65 contains the multi-function
configuration pins. Bank 0 contains the dedicated configuration pins.
• In Figure 1-2 through Figure 1-134, the multi-function configuration bank 65 is shown
adjacent to the SYSMON/CFG blocks. For devices with multiple super logic regions
(SLRs), banks 60 and 70 are also shown adjacent to the SYSMON/CFG blocks. Due to
the architectural differences between these and other banks, special consideration
must be taken when using them under certain conditions. See the State of I/Os During
and After Configuration and the Special DCI Requirements in Some Banks sections of
UltraScale Architecture SelectIO Resources User Guide (UG571) for details.
• For UltraScale devices, all dedicated configuration I/Os (bank 0) and HR I/Os are 1.5V
to 3.3V capable.
• For UltraScale+ devices, all dedicated configuration I/Os (bank 0) and HR I/Os are 1.5V
to 1.8V capable.

SYSMON, Configuration, PCIe, Interlaken, and 100GE Integrated Blocks


• CFG: Configuration block
• SYSMON/CFG: Block shared between SYSMON and configuration
• PCIe: Integrated block for PCIe
Note: Do not connect the integrated block for PCIe to transceiver channels through an SLR
crossing. For further details, refer to the Placement Rules section of the UltraScale Devices Gen3
Integrated Block for PCI Express Product Guide (PG156) and UltraScale+ Devices Integrated Block
for PCI Express Product Guide (PG213). Blocks with an additional (Tandem) label support Tandem
configuration.
• ILKN: Interlaken block
Note: Do not connect the Interlaken block to transceiver channels through an SLR crossing. For
further details, refer to the Transceiver Interface section of the Integrated Interlaken 150G Product
Guide ( PG169).

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• CMAC: 100G Ethernet block


Note: Do not connect the 100G Ethernet block to transceiver channels through an SLR crossing.
For further details, refer to the Transceiver Selection Rules section of the UltraScale Devices
Integrated Block for 100G Ethernet Product Guide ( PG165) or UltraScale+ Devices Integrated 100G
Ethernet Subsystem Product Guide (PG203).

Device Diagrams
Figure 1-1 shows an example diagram with a brief explanation for each component.
X-Ref Target - Figure 1-1

;<ĺ0*7+>7;RU5;@>3RU1@B
GTH Quad 226 ;<ĺ0*7+>7;RU5;@>3RU1@B
HD I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y12-X0Y15 ;<ĺ0*7+>7;RU5;@>3RU1@B
E D Configuration
D[R] ;<ĺ0*7+>7;RU5;@>3RU1@B
;<ĺ0*7+>7;RU5;@>3RU1@B
GTH Quad 225
HD I/O Bank 45 HP I/O Bank 65 ;<ĺ0*7+>7;RU5;@>3RU1@B
Configuration X0Y8-X0Y11 ;<ĺ0*7+>7;RU5;@>3RU1@B
F C
C[R] ;<ĺ0*7+>7;RU5;@>3RU1@B
;<ĺ0*7+>7;RU5;@>3RU1@B
PCIE4 GTH Quad 224
HD I/O Bank 44 HP I/O Bank 64 ;<ĺ0*7+>7;RU5;@>3RU1@B
X0Y1 X0Y4-X0Y7
G J ;<ĺ0*7+>7;RU5;@>3RU1@B
(tandem) B [R] (RCAL) ;<ĺ0*7+>7;RU5;@>3RU1@B
;<ĺ0*7+>7;RU5;@>3RU1@B
GTH Quad 223
HD I/O Bank 43 HP I/O Bank 63 PCIE4 ;<ĺ0*7+>7;RU5;@>3RU1@B
X0Y0-X0Y3
H I X0Y0 ;<ĺ0*7+>7;RU5;@>3RU1@B
A[R] ;<ĺ0*7+>7;RU5;@>3RU1@B

Alphabetic Bank/Quad I/O Bank Type Integrated Blocks


Transceiver Power
Designator. Corresponds {HP, HR, or HD] and Transceiver
Supply Group
to columns in Table 1-6 XY Coordinates
and Table 1-7.
X16518-083020

Figure 1-1: Example Device Diagram

TIP: Due to design limitations, the device resources might be less than what is shown in the device
diagrams. The actual available resources by device and package are listed in the UltraScale
Architecture and Product Overview (DS890).

The following figures show a die view of each device followed by a view with respect to
each available package.

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XCKU025 Bank Diagrams


X-Ref Target - Figure 1-2

SYSMON GTH Quad 226


HP I/O Bank 46 HP I/O Bank 66
Configuration X0Y8-X0Y11

GTH Quad 225


HP I/O Bank 45 HR I/O Bank 65 Configuration X0Y4-X0Y7
(RCAL)
PCIe
GTH Quad 224
HP I/O Bank 44 HR I/O Bank 64 X0Y0
X0Y0-X0Y3
(tandem)
X16426-012917

Figure 1-2: XCKU025 Banks


X-Ref Target - Figure 1-3

GTH Quad 226


HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11
I D Configuration
C [R]
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
Configuration X0Y4-X0Y7
H C
B [R] (RCAL)
PCIe GTH Quad 224
HP I/O Bank 44 HR I/O Bank 64
X0Y0 X0Y0-X0Y3
G R
(tandem) A [R]
X16427-012917

Figure 1-3: XCKU025 Banks in FFVA1156 Package

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XCKU035 Bank Diagrams


X-Ref Target - Figure 1-4

PCIe GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y2 X0Y16-X0Y19

PCIe GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y1 X0Y12-X0Y15

SYSMON GTH Quad 226


HP I/O Bank 46 HP I/O Bank 66
Configuration X0Y8-X0Y11

GTH Quad 225


HP I/O Bank 45 HR I/O Bank 65 Configuration X0Y4-X0Y7
(RCAL)
PCIe
GTH Quad 224
HP I/O Bank 44 HR I/O Bank 64 X0Y0
X0Y0-X0Y3
(tandem)
X16429-012917

Figure 1-4: XCKU035 Banks


X-Ref Target - Figure 1-5

PCIe GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y2 X0Y16-X0Y19

GTH Quad 227


PCIe
HP I/O Bank 47 HP I/O Bank 67 X0Y12-X0Y15
X0Y1
D [R]
GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11
G D Configuration
C [R]
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
Configuration X0Y4-X0Y7
F C
B [R] (RCAL)
PCIe GTH Quad 224
HP I/O Bank 44 HR I/O Bank 64
X0Y0 X0Y0-X0Y3
E R
(tandem) A [R]
X16430-012917

Figure 1-5: XCKU035 Banks in FBVA676 Package

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X-Ref Target - Figure 1-6

HP I/O Bank 68 PCIe GTH Quad 228


HP I/O Bank 48
I X0Y2 X0Y16-X0Y19

HP I/O Bank 47 HP I/O Bank 67 PCIe GTH Quad 227


G J X0Y1 X0Y12-X0Y15

HP I/O Bank 46 HP I/O Bank 66 SYSMON GTH Quad 226


F H Configuration X0Y8-X0Y11

GTH Quad 225


HP I/O Bank 45 HR I/O Bank 65
Configuration X0Y4-X0Y7
E C
B [R] (RCAL)
PCIe GTH Quad 224
HP I/O Bank 44 HR I/O Bank 64
X0Y0 X0Y0-X0Y3
D R
(tandem) A [R]
X16432-012917

Figure 1-6: XCKU035 Banks in SFVA784 Package


X-Ref Target - Figure 1-7

HP I/O Bank 48 PCIe GTH Quad 228


HP I/O Bank 68
J X0Y2 X0Y16-X0Y19

GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y12-X0Y15
I E X0Y1
D [R]
GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11
H D Configuration
C [R]
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
Configuration X0Y4-X0Y7
G C
B [R] (RCAL)
PCIe GTH Quad 224
HP I/O Bank 44 HR I/O Bank 64
X0Y0 X0Y0-X0Y3
F R
(tandem) A [R]
X16433-012917

Figure 1-7: XCKU035 Banks in FBVA900 Package

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X-Ref Target - Figure 1-8

HP I/O Bank 48 HP I/O Bank 68 PCIe GTH Quad 228


K F X0Y2 X0Y16-X0Y19

GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y12-X0Y15
J E X0Y1
D [R]
GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11
I D Configuration
C [R]
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
Configuration X0Y4-X0Y7
H C
B [R] (RCAL)
PCIe GTH Quad 224
HP I/O Bank 44 HR I/O Bank 64
X0Y0 X0Y0-X0Y3
G R
(tandem) A [R]
X16434-062117

Figure 1-8: XCKU035 Banks in FFVA1156 Package

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XCKU040 and XQKU040 Bank Diagrams


X-Ref Target - Figure 1-9

PCIe GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y2 X0Y16-X0Y19

PCIe GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y1 X0Y12-X0Y15

SYSMON GTH Quad 226


HP I/O Bank 46 HP I/O Bank 66
Configuration X0Y8-X0Y11

GTH Quad 225


HP I/O Bank 45 HR I/O Bank 65 Configuration X0Y4-X0Y7
(RCAL)
PCIe
GTH Quad 224
HP I/O Bank 44 HR I/O Bank 64 X0Y0
X0Y0-X0Y3
(tandem)
X16435-012917

Figure 1-9: XCKU040 and XQKU040 Banks


X-Ref Target - Figure 1-10

PCIe GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y2 X0Y16-X0Y19

GTH Quad 227


PCIe
HP I/O Bank 47 HP I/O Bank 67 X0Y12-X0Y15
X0Y1
D [R]
GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11
G D Configuration
C [R]
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
Configuration X0Y4-X0Y7
F C
B [R] (RCAL)
PCIe GTH Quad 224
HP I/O Bank 44 HR I/O Bank 64
X0Y0 X0Y0-X0Y3
E R
(tandem) A [R]
X16436-012917

Figure 1-10: XCKU040 Banks in FBVA676 Package and XQKU040 Banks in RBA676 Package

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X-Ref Target - Figure 1-11

HP I/O Bank 68 PCIe GTH Quad 228


HP I/O Bank 48
I X0Y2 X0Y16-X0Y19

HP I/O Bank 47 HP I/O Bank 67 PCIe GTH Quad 227


G J X0Y1 X0Y12-X0Y15

HP I/O Bank 46 HP I/O Bank 66 SYSMON GTH Quad 226


F H Configuration X0Y8-X0Y11

GTH Quad 225


HP I/O Bank 45 HR I/O Bank 65
Configuration X0Y4-X0Y7
E C
B [R] (RCAL)
PCIe GTH Quad 224
HP I/O Bank 44 HR I/O Bank 64
X0Y0 X0Y0-X0Y3
D R
(tandem) A [R]
X16437-012917

Figure 1-11: XCKU040 Banks in SFVA784 Package


X-Ref Target - Figure 1-12

HP I/O Bank 48 PCIe GTH Quad 228


HP I/O Bank 68
J X0Y2 X0Y16-X0Y19

GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y12-X0Y15
I E X0Y1
D [R]
GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11
H D Configuration
C [R]
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
Configuration X0Y4-X0Y7
G C
B [R] (RCAL)
PCIe GTH Quad 224
HP I/O Bank 44 HR I/O Bank 64
X0Y0 X0Y0-X0Y3
F R
(tandem) A [R]
X16438-012917

Figure 1-12: XCKU040 Banks in FBVA900 Package

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X-Ref Target - Figure 1-13

GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y16-X0Y19
K F X0Y2
E [R]
GTH Quad 227
HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y12-X0Y15
J E X0Y1
D [R]
GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11
I D Configuration
C [R]
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
Configuration X0Y4-X0Y7
H C
B [R] (RCAL)
PCIe GTH Quad 224
HP I/O Bank 44 HR I/O Bank 64
X0Y0 X0Y0-X0Y3
G R
(tandem) A [R]
X16439-062117

Figure 1-13: XCKU040 Banks in FFVA1156 Package and XQKU040 in RFA1156 Package

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XCKU060 and XQKU060 Bank Diagrams


X-Ref Target - Figure 1-14

GTH Quad 128 PCIe GTH Quad 228


X0Y16-X0Y19 HP I/O Bank 48 HP I/O Bank 68
X0Y2 X1Y16-X1Y19
(RCAL)

GTH Quad 127 PCIe GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y12-X0Y15 X0Y1 X1Y12-X1Y15

GTH Quad 226


GTH Quad 126 SYSMON
HP I/O Bank 46 HP I/O Bank 66 X1Y8-X1Y11
X0Y8-X0Y11 Configuration
(RCAL)

GTH Quad 225


HP I/O Bank 25 HP I/O Bank 45 HR I/O Bank 65 Configuration
X1Y4-X1Y7

PCIe
GTH Quad 224
HP I/O Bank 24 HP I/O Bank 44 HR I/O Bank 64 X0Y0
X1Y0-X1Y3
(tandem)
X16440-012917

Figure 1-14: XCKU060 and XQKU060 Banks


X-Ref Target - Figure 1-15

GTH Quad 128 GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y16-X0Y19 X1Y16-X1Y19
K F X0Y2
G [L] (RCAL) E [R]
GTH Quad 127 GTH Quad 227
HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y12-X0Y15 X1Y12-X1Y15
J E X0Y1
F [L] D [R]
GTH Quad 226
GTH Quad 126 HP I/O Bank 46 HP I/O Bank 66 SYSMON
X1Y8-X1Y11
X0Y8-X0Y11 I D Configuration
C [R] (RCAL)
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
HP I/O Bank 25 Configuration X1Y4-X1Y7
H C
B [R]
PCIe GTH Quad 224
HP I/O Bank 44 HR I/O Bank 64
HP I/O Bank 24 X0Y0 X1Y0-X1Y3
G R
(tandem) A [R]
X16441-062117

Figure 1-15: XCKU060 Banks in FFVA1156 Package and XQKU060 Banks in RFA1156 Package

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X-Ref Target - Figure 1-16

GTH Quad 128 GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y16-X0Y19 X1Y16-X1Y19
M J X0Y2
L [L] (RCAL) E [RS]
GTH Quad 127 GTH Quad 227
HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y12-X0Y15 X1Y12-X1Y15
L I X0Y1
K [L] D [RS]
GTH Quad 126 GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
K H Configuration
J [L] C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 25 HP I/O Bank 45 HR I/O Bank 65
Configuration X1Y4-X1Y7
G E C
B [RS]
PCIe GTH Quad 224
HP I/O Bank 24 HP I/O Bank 44 HR I/O Bank 64
X0Y0 X1Y0-X1Y3
F D R
(tandem) A [RS]
X16442-012917

Figure 1-16: XCKU060 Banks in FFVA1517 Package

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XCKU085 Bank Diagrams


X-Ref Target - Figure 1-17

GTH
GTHQuad
Quad132
132 PCIe
PCIe GTH
GTHQuad
Quad232
232
HP
HPI/O
I/OBank
Bank5252 HP
HPI/O
I/OBank
Bank7272
X0Y32-X0Y35
X0Y16-X0Y19 X0Y4
X0Y4 X1Y32-X1Y35
X1Y32-X1Y35

GTH
GTHQuad
Quad231
231
GTH
GTHQuad
Quad131
131 SYSMON
SYSMON
HP
HPI/O
I/OBank
Bank5151 HP
HPI/O
I/OBank
Bank7171 X1Y28-X1Y31
X1Y28-X1Y31
X0Y28-X0Y31
X0Y12-X0Y15 Configuration
Configuration
(RCAL)
(RCAL)

GTH
GTHQuad
Quad230
230
HP
HPI/O
I/OBank
Bank3030 HP
HPI/O
I/OBank
Bank5050 HR
HRI/O
I/OBank
Bank7070 Configuration
Configuration
X1Y24-X1Y27
X1Y24-X1Y27

PCIe
PCIe GTH
GTHQuad
Quad229
229
HP
HPI/O
I/OBank
Bank2929 HP
HPI/O
I/OBank
Bank4949 HR
HRI/O
I/OBank
Bank6969
X0Y3
X0Y3 X1Y20-X1Y23
X1Y20-X1Y23

SLR
SLR Crossing
Crossing
GTH
GTHQuad
Quad128
128
PCIe
PCIe GTH
GTHQuad
Quad228
228
X0Y16-X0Y19
X0Y8-X0Y11 HP
HPI/O
I/OBank
Bank4848 HP
HPI/O
I/OBank
Bank6868
X0Y2
X0Y2 X1Y16-X1Y19
X1Y16-X1Y19
(RCAL)
(RCAL)

GTH
GTHQuad
Quad127
127 PCIe
PCIe GTH
GTHQuad
Quad227
227
HP
HPI/O
I/OBank
Bank4747 HP
HPI/O
I/OBank
Bank6767
X0Y12-X0Y15
X0Y4-X0Y7 X0Y1
X0Y1 X1Y12-X1Y15
X1Y12-X1Y15

GTH
GTHQuad
Quad226
226
GTH
GTHQuad
Quad126
126 SYSMON
SYSMON
HP
HPI/O
I/OBank
Bank4646 HP
HPI/O
I/OBank
Bank6666 X1Y8-X1Y11
X1Y8-X1Y11
X0Y8-X0Y11
X0Y0-X0Y3 Configuration
Configuration
(RCAL)
(RCAL)

GTH
GTHQuad
Quad225
225
HP
HPI/O
I/OBank
Bank2525 HP
HPI/O
I/OBank
Bank4545 HR
HRI/O
I/OBank
Bank6565 Configuration
Configuration
X1Y4-X1Y7
X1Y4-X1Y7

PCIe
PCIe
GTH
GTHQuad
Quad224
224
HP
HPI/O
I/OBank
Bank2424 HP
HPI/O
I/OBank
Bank4444 HR
HRI/O
I/OBank
Bank6464 X0Y0
X0Y0
X1Y0-X1Y3
X1Y0-X1Y3
(tandem)
(tandem)
X16443-012917

Figure 1-17: XCKU085 Banks

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X-Ref Target - Figure 1-18

GTH Quad 232


GTH Quad 132 PCIe
HP I/O Bank 52 HP I/O Bank 72 X1Y32-X1Y35
X0Y32-X0Y35 X0Y4
I [RN]
GTH Quad 231
GTH Quad 131 SYSMON
HP I/O Bank 51 HP I/O Bank 71 X1Y28-X1Y31
X0Y28-X0Y31 Configuration
H [RN] (RCAL)
GTH Quad 230
HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70 Configuration X1Y24-X1Y27
G [RN]
GTH Quad 229
PCIe
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 X1Y20-X1Y23
X0Y3
F [RN]
SLR Crossing
GTH Quad 128 GTH Quad 228
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y16-X0Y19 X1Y16-X1Y19
M J X0Y2
L [L] (RCAL) E [RS]
GTH Quad 127 GTH Quad 227
HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y12-X0Y15 X1Y12-X1Y15
L I X0Y1
K [L] D [RS]
GTH Quad 126 GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
K H Configuration
J [L] C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 25 HP I/O Bank 45 HR I/O Bank 65
Configuration X1Y4-X1Y7
G E C
B [RS]
PCIe GTH Quad 224
HP I/O Bank 24 HP I/O Bank 44 HR I/O Bank 64
X0Y0 X1Y0-X1Y3
F D R
(tandem) A [RS]
X16444-012917

Figure 1-18: XCKU085 Banks in FLVA1517 Package

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X-Ref Target - Figure 1-19

GTH Quad 132 GTH Quad 232


HP I/O Bank 52 PCIe
X0Y32-X0Y35 HP I/O Bank 72 X1Y32-X1Y35
N X0Y4
L [L] H [RN]
GTH Quad 131 GTH Quad 231
HP I/O Bank 51 SYSMON
X0Y28-X0Y31 HP I/O Bank 71 X1Y28-X1Y31
M Configuration
K [L] G [RN] (RCAL)
GTH Quad 230
HP I/O Bank 50
HP I/O Bank 30 HR I/O Bank 70 Configuration X1Y24-X1Y27
L
F [RN]

HP I/O Bank 49 PCIe GTH Quad 229


HP I/O Bank 29 HR I/O Bank 69
K X0Y3 X1Y20-X1Y23

SLR Crossing
GTH Quad 128 GTH Quad 228
HP I/O Bank 48 PCIe
X0Y16-X0Y19 HP I/O Bank 68 X1Y16-X1Y19
J X0Y2
J [L] (RCAL) E [RS]
GTH Quad 227
GTH Quad 127 HP I/O Bank 47 HP I/O Bank 67 PCIe
X1Y12-X1Y15
X0Y12-X0Y15 I E X0Y1
D [RS]
GTH Quad 226
GTH Quad 126 HP I/O Bank 46 HP I/O Bank 66 SYSMON
X1Y8-X1Y11
X0Y8-X0Y11 H D Configuration
C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
HP I/O Bank 25 Configuration X1Y4-X1Y7
G C
B [RS]
HR I/O Bank PCIe GTH Quad 224
HP I/O Bank 44
HP I/O Bank 24 84/94 X0Y0 X1Y0-X1Y3
F
B (tandem) A [RS]
X16445-031820

Figure 1-19: XCKU085 Banks in FLVB1760 Package

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X-Ref Target - Figure 1-20

GTH Quad 132 GTH Quad 232


HP I/O Bank 52 HP I/O Bank 72 PCIe
X0Y32-X0Y35 X1Y32-X1Y35
K O X0Y4
O [LN] I [RN]
GTH Quad 131 GTH Quad 231
HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y28-X0Y31 X1Y28-X1Y31
J N Configuration
N [LN] H [RN] (RCAL)
GTH Quad 230
HR I/O Bank 70
HP I/O Bank 30 HP I/O Bank 50 Configuration X1Y24-X1Y27
M
G [RN]
GTH Quad 229
PCIe
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 X1Y20-X1Y23
X0Y3
F [RN]
SLR Crossing
GTH Quad 128 GTH Quad 228
HP I/O Bank 68 PCIe
X0Y16-X0Y19 HP I/O Bank 48 X1Y16-X1Y19
F X0Y2
M [LS] (RCAL) E [RS]
GTH Quad 127 GTH Quad 227
HP I/O Bank 67 PCIe
X0Y12-X0Y15 HP I/O Bank 47 X1Y12-X1Y15
E X0Y1
L [LS] D [RS]
GTH Quad 126 GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
I D Configuration
K [LS] C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
HP I/O Bank 25 Configuration X1Y4-X1Y7
H C
B [RS]
PCIe GTH Quad 224
HP I/O Bank 44 HR I/O Bank
HP I/O Bank 24 X0Y0 X1Y0-X1Y3
G 84/94
(tandem) A [RS]
X16446-012917

Figure 1-20: XCKU085 Banks in FLVF1924 Package

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XCKU095 and XQKU095 Bank Diagrams


X-Ref Target - Figure 1-21

GTY Quad 131 PCIe GTH Quad 231


HP I/O Bank 51 HP I/O Bank 71
X0Y28-X0Y31 X0Y3 X0Y28-X0Y31

GTY Quad 130 ILKN GTH Quad 230


HP I/O Bank 50 HP I/O Bank 70
X0Y24-X0Y27 X0Y2 X0Y24-X0Y27
GTY Quad 129
CMAC PCIe GTH Quad 229
X0Y20-X0Y23 HP I/O Bank 49 HP I/O Bank 69
X0Y1 X0Y2 X0Y20-X0Y23
(RCAL)

GTY Quad 128 PCIe GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y16-X0Y19 X0Y1 X0Y16-X0Y19

GTY Quad 127 CMAC ILKN GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y12-X0Y15 X0Y0 X0Y0 X0Y12-X0Y15

GTY Quad 126 SYSMON GTH Quad 226


HP I/O Bank 46 HP I/O Bank 66
X0Y8-X0Y11 Configuration X0Y8-X0Y11

GTH Quad 225


GTY Quad 125
HP I/O Bank 45 HP I/O Bank 65 Configuration X0Y4-X0Y7
X0Y4-X0Y7
(RCAL)
PCIe
GTY Quad 124 HR I/O Bank GTH Quad 224
HP I/O Bank 44 X0Y0
X0Y0-X0Y3 84/94 X0Y0-X0Y3
(tandem)
X16448-012917

Figure 1-21: XCKU095 and XQKU095 Banks

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X-Ref Target - Figure 1-22

GTY Quad 131 PCIe GTH Quad 231


HP I/O Bank 51 HP I/O Bank 71
X0Y28-X0Y31 X0Y3 X0Y28-X0Y31

GTY Quad 130


ILKN GTH Quad 230
X0Y24-X0Y27 HP I/O Bank 50 HP I/O Bank 70
X0Y2 X0Y24-X0Y27
G [L]
GTY Quad 129
CMAC PCIe GTH Quad 229
X0Y20-X0Y23 HP I/O Bank 49 HP I/O Bank 69
X0Y1 X0Y2 X0Y20-X0Y23
F [L] (RCAL)
GTH Quad 228
GTY Quad 128 HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y16-X0Y19
X0Y16-X0Y19 K D X0Y1
E [R]
GTH Quad 227
GTY Quad 127 CMAC HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15
X0Y12-X0Y15 X0Y0 J F X0Y0
D [R]
GTH Quad 226
GTY Quad 126 HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11
X0Y8-X0Y11 I D Configuration
C [R]
GTH Quad 225
GTY Quad 125 HP I/O Bank 45 HP I/O Bank 65
Configuration X0Y4-X0Y7
X0Y4-X0Y7 G C
B [R] (RCAL)
PCIe GTH Quad 224
GTY Quad 124 HP I/O Bank 44 HR I/O Bank 64
X0Y0 X0Y0-X0Y3
X0Y0-X0Y3 H R
(tandem) A [R]
X16449-012917

Figure 1-22: XCKU095 Banks in FFVA1156 Package and XQKU095 in RFA1156 Package

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X-Ref Target - Figure 1-23

GTY Quad 131 PCIe GTH Quad 231


HP I/O Bank 51 HP I/O Bank 71
X0Y28-X0Y31 X0Y3 X0Y28-X0Y31

GTY Quad 130 ILKN GTH Quad 230


HP I/O Bank 50 HP I/O Bank 70
X0Y24-X0Y27 X0Y2 X0Y24-X0Y27

GTY Quad 129


CMAC PCIe GTH Quad 229
X0Y20-X0Y23 HP I/O Bank 49 HP I/O Bank 69
X0Y1 X0Y2 X0Y20-X0Y23
J [L] (RCAL)
GTY Quad 128 GTH Quad 228
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y16-X0Y19 X0Y16-X0Y19
K F X0Y1
I [L] E [R]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15 X0Y12-X0Y15
X0Y0 J E X0Y0
H [L] D [R]
GTY Quad 126 GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X0Y8-X0Y11
I D Configuration
G [L] C [R]
GTY Quad 125 GTH Quad 225
HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X0Y4-X0Y7
H C
F [L] B [R] (RCAL)
HR I/O Bank PCIe GTH Quad 224
GTY Quad 124 HP I/O Bank 44
84/94 X0Y0 X0Y0-X0Y3
X0Y0-X0Y3 G
B (tandem) A [R]
X16450-012917

Figure 1-23: XCKU095 Banks in FFVC1517 Package

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X-Ref Target - Figure 1-24

GTY Quad 131 GTH Quad 231


HP I/O Bank 51 HP I/O Bank 71 PCIe
X0Y28-X0Y31 X0Y28-X0Y31
O (Partial) L X0Y3
M [L] H [RN]
GTY Quad 130 GTH Quad 230
HP I/O Bank 50 HP I/O Bank 70 ILKN
X0Y24-X0Y27 X0Y24-X0Y27
N K X0Y2
L [L] G [RN]
GTY Quad 129 GTH Quad 229
CMAC HP I/O Bank 49 PCIe
X0Y20-X0Y23 HP I/O Bank 69 X0Y20-X0Y23
X0Y1 M X0Y2
K [L] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
HP I/O Bank 48 PCIe
X0Y16-X0Y19 HP I/O Bank 68 X0Y16-X0Y19
J X0Y1
J [L] E [RS]
GTH Quad 227
GTY Quad 127 CMAC HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15
X0Y12-X0Y15 X0Y0 I E X0Y0
D [RS]
GTH Quad 226
GTY Quad 126 HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11
X0Y8-X0Y11 H D Configuration
C [RS]
GTH Quad 225
GTY Quad 125 HP I/O Bank 45 HP I/O Bank 65
Configuration X0Y4-X0Y7
X0Y4-X0Y7 G C
B [RS] (RCAL)
HR I/O Bank PCIe GTH Quad 224
GTY Quad 124 HP I/O Bank 44
84/94 X0Y0 X0Y0-X0Y3
X0Y0-X0Y3 F
B (tandem) A [RS]
X16451-012917

Figure 1-24: XCKU095 Banks in FFVB1760 Package

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X-Ref Target - Figure 1-25

GTY Quad 131 GTH Quad 231


HP I/O Bank 51 HP I/O Bank 71 PCIe
X0Y28-X0Y31 X0Y28-X0Y31
L O X0Y3
R [LN] H [RN]
GTY Quad 130 GTH Quad 230
HP I/O Bank 50 HP I/O Bank 70 ILKN
X0Y24-X0Y27 X0Y24-X0Y27
K N X0Y2
Q [LN] G [RN]
GTY Quad 129 GTH Quad 229
CMAC HP I/O Bank 49 HP I/O Bank 69 PCIe
X0Y20-X0Y23 X0Y20-X0Y23
X0Y1 J M X0Y2
P [LN] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
HP I/O Bank 68 PCIe
X0Y16-X0Y19 HP I/O Bank 48 X0Y16-X0Y19
F (Partial) X0Y1
O [LN] E [RS]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y12-X0Y15 HP I/O Bank 47 X0Y12-X0Y15
X0Y0 E X0Y0
N [LS] D [RS]
GTY Quad 126 GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X0Y8-X0Y11
I D Configuration
M [LS] C [RS]
GTY Quad 125 GTH Quad 225
HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X0Y4-X0Y7
H C
L [LS] B [RS] (RCAL)
GTY Quad 124 HR I/O Bank PCIe GTH Quad 224
HP I/O Bank 44
X0Y0-X0Y3 84/94 X0Y0 X0Y0-X0Y3
G
K [LS] B (tandem) A [RS]
X16452-012917

Figure 1-25: XCKU095 Banks in FFVB2104 Package

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XCKU115 and XQKU115 Bank Diagrams


X-Ref Target - Figure 1-26

GTH Quad 133


PCIe GTH Quad 233
X0Y36-X0Y39 HP I/O Bank 53 HP I/O Bank 73
X0Y5 X1Y36-X1Y39
(RCAL)

GTH Quad 132 PCIe GTH Quad 232


HP I/O Bank 52 HP I/O Bank 72
X0Y32-X0Y35 X0Y4 X1Y32-X1Y35

GTH Quad 231


GTH Quad 131 SYSMON
HP I/O Bank 51 HP I/O Bank 71 X1Y28-X1Y31
X0Y28-X0Y31 Configuration
(RCAL)

GTH Quad 230


HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70 Configuration
X1Y24-X1Y27

PCIe GTH Quad 229


HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69
X0Y3 X1Y20-X1Y23

SLR Crossing
GTH Quad 128
PCIe GTH Quad 228
X0Y16-X0Y19 HP I/O Bank 48 HP I/O Bank 68
X0Y2 X1Y16-X1Y19
(RCAL)

GTH Quad 127 PCIe GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y12-X0Y15 X0Y1 X1Y12-X1Y15

GTH Quad 226


GTH Quad 126 SYSMON
HP I/O Bank 46 HP I/O Bank 66 X1Y8-X1Y11
X0Y8-X0Y11 Configuration
(RCAL)

GTH Quad 225


HP I/O Bank 25 HP I/O Bank 45 HR I/O Bank 65 Configuration
X1Y4-X1Y7

PCIe
GTH Quad 224
HP I/O Bank 24 HP I/O Bank 44 HR I/O Bank 64 X0Y0
X1Y0-X1Y3
(tandem)
X16453-012917

Figure 1-26: XCKU115 and XQKU115 Banks

TIP: Bank 64 is labeled as 84/94 in some packages.

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X-Ref Target - Figure 1-27

GTH Quad 133


PCIe GTH Quad 233
X0Y36-X0Y39 HP I/O Bank 53 HP I/O Bank 73
X0Y5 X1Y36-X1Y39
(RCAL)
GTH Quad 232
GTH Quad 132 PCIe
HP I/O Bank 52 HP I/O Bank 72 X1Y32-X1Y35
X0Y32-X0Y35 X0Y4
I [RN]
GTH Quad 231
GTH Quad 131 SYSMON
HP I/O Bank 51 HP I/O Bank 71 X1Y28-X1Y31
X0Y28-X0Y31 Configuration
H [RN] (RCAL)
GTH Quad 230
HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70 Configuration X1Y24-X1Y27
G [RN]
GTH Quad 229
PCIe
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 X1Y20-X1Y23
X0Y3
F [RN]
SLR Crossing
GTH Quad 128 GTH Quad 228
HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y16-X0Y19 X1Y16-X1Y19
M J X0Y2
L [L] (RCAL) E [RS]
GTH Quad 127 GTH Quad 227
HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y12-X0Y15 X1Y12-X1Y15
L I X0Y1
K [L] D [RS]
GTH Quad 126 GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
K H Configuration
J [L] C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 25 HP I/O Bank 45 HR I/O Bank 65
Configuration X1Y4-X1Y7
G E C
B [RS]
PCIe GTH Quad 224
HP I/O Bank 24 HP I/O Bank 44 HR I/O Bank 64
X0Y0 X1Y0-X1Y3
F D R
(tandem) A [RS]
X16454-012917

Figure 1-27: XCKU115 Banks in FLVA1517 Package

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X-Ref Target - Figure 1-28

GTH Quad 133 GTH Quad 233


HP I/O Bank 73 PCIe
X0Y36-X0Y39 HP I/O Bank 53 X1Y36-X1Y39
H X0Y5
R [LN] (RCAL) J [RN]
GTH Quad 132 GTH Quad 232
HP I/O Bank 72 PCIe
X0Y32-X0Y35 HP I/O Bank 52 X1Y32-X1Y35
G X0Y4
Q [LN] I [RN]
GTH Quad 131 GTH Quad 231
HP I/O Bank 71 SYSMON
X0Y28-X0Y31 HP I/O Bank 51 X1Y28-X1Y31
F Configuration
P [LN] H [RN] (RCAL)
GTH Quad 230
HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70 Configuration X1Y24-X1Y27
G [RN]
GTH Quad 229
PCIe
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 X1Y20-X1Y23
X0Y3
F [RN]
SLR Crossing
GTH Quad 128 GTH Quad 228
PCIe
X0Y16-X0Y19 HP I/O Bank 48 HP I/O Bank 68 X1Y16-X1Y19
X0Y2
N [LS] (RCAL) E [RS]
GTH Quad 127 GTH Quad 227
HP I/O Bank 67 PCIe
X0Y12-X0Y15 HP I/O Bank 47 X1Y12-X1Y15
E (Partial) X0Y1
M [LS] D [RS]
GTH Quad 126 GTH Quad 226
HP I/O Bank 66 SYSMON
X0Y8-X0Y11 HP I/O Bank 46 X1Y8-X1Y11
D Configuration
L [LS] C [RS] (RCAL)
GTH Quad 225
HR I/O Bank 65
HP I/O Bank 25 HP I/O Bank 45 Configuration X1Y4-X1Y7
C
B [RS]
HR I/O Bank PCIe GTH Quad 224
HP I/O Bank 24 HP I/O Bank 44 84/94 X0Y0 X1Y0-X1Y3
B (tandem) A [RS]
X16455-062117

Figure 1-28: XCKU115 Banks in FLVD1517 Package and XQKU115 in the RLD1517 Package

TIP: Bank 64 is labeled as 84/94 in some packages.

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X-Ref Target - Figure 1-29

GTH Quad 133 GTH Quad 233


HP I/O Bank 53 PCIe
X0Y36-X0Y39 HP I/O Bank 73 X1Y36-X1Y39
O (Partial) X0Y5
M [L] (RCAL) I [RN]
GTH Quad 132 GTH Quad 232
HP I/O Bank 52 PCIe
X0Y32-X0Y35 HP I/O Bank 72 X1Y32-X1Y35
N X0Y4
L [L] H [RN]
GTH Quad 131 GTH Quad 231
HP I/O Bank 51 SYSMON
X0Y28-X0Y31 HP I/O Bank 71 X1Y28-X1Y31
M Configuration
K [L] G [RN] (RCAL)
GTH Quad 230
HP I/O Bank 50
HP I/O Bank 30 HR I/O Bank 70 Configuration X1Y24-X1Y27
L
F [RN]

HP I/O Bank 49 PCIe GTH Quad 229


HP I/O Bank 29 HR I/O Bank 69
K X0Y3 X1Y20-X1Y23

SLR Crossing
GTH Quad 128 GTH Quad 228
HP I/O Bank 48 PCIe
X0Y16-X0Y19 HP I/O Bank 68 X1Y16-X1Y19
J X0Y2
J [L] (RCAL) E [RS]
GTH Quad 227
GTH Quad 127 HP I/O Bank 47 HP I/O Bank 67 PCIe
X1Y12-X1Y15
X0Y12-X0Y15 I E X0Y1
D [RS]
GTH Quad 226
GTH Quad 126 HP I/O Bank 46 HP I/O Bank 66 SYSMON
X1Y8-X1Y11
X0Y8-X0Y11 H D Configuration
C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
HP I/O Bank 25 Configuration X1Y4-X1Y7
G C
B [RS]
HR I/O Bank PCIe GTH Quad 224
HP I/O Bank 44
HP I/O Bank 24 84/94 X0Y0 X1Y0-X1Y3
F
B (tandem) A [RS]
X16456-012917

Figure 1-29: XCKU115 Banks in FLVB1760 Package

TIP: Bank 64 is labeled as 84/94 in some packages.

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X-Ref Target - Figure 1-30

GTH Quad 133 GTH Quad 233


HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y36-X0Y39 X1Y36-X1Y39
M Q X0Y5
M [LN] (RCAL) G [RN]
GTH Quad 132 GTH Quad 232
HP I/O Bank 52 HP I/O Bank 72 PCIe
X0Y32-X0Y35 X1Y32-X1Y35
L P X0Y4
L [LN] F [RN]
GTH Quad 131 GTH Quad 231
HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y28-X0Y31 X1Y28-X1Y31
K O Configuration
K [LN] E [RN] (RCAL)

HP I/O Bank 50 HR I/O Bank 70 GTH Quad 230


HP I/O Bank 30 Configuration
J N X1Y24-X1Y27

PCIe GTH Quad 229


HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69
X0Y3 X1Y20-X1Y23

SLR Crossing
GTH Quad 128
PCIe GTH Quad 228
X0Y16-X0Y19 HP I/O Bank 48 HP I/O Bank 68
X0Y2 X1Y16-X1Y19
J [LS] (RCAL)
GTH Quad 127 GTH Quad 227
HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y12-X0Y15 X1Y12-X1Y15
I E X0Y1
I [LS] D [RS]
GTH Quad 126 GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
H D Configuration
H [LS] C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
HP I/O Bank 25 Configuration X1Y4-X1Y7
G C
B [RS]
HR I/O Bank PCIe GTH Quad 224
HP I/O Bank 44
HP I/O Bank 24 84/94 X0Y0 X1Y0-X1Y3
F
B (tandem) A [RS]
X16457-012917

Figure 1-30: XCKU115 Banks in FLVD1924 Package

TIP: Bank 64 is labeled as 84/94 in some packages.

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X-Ref Target - Figure 1-31

GTH Quad 133 GTH Quad 233


HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y36-X0Y39 X1Y36-X1Y39
L P X0Y5
P [LN] (RCAL) J [RN]
GTH Quad 132 GTH Quad 232
HP I/O Bank 52 HP I/O Bank 72 PCIe
X0Y32-X0Y35 X1Y32-X1Y35
K O X0Y4
O [LN] I [RN]
GTH Quad 131 GTH Quad 231
HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y28-X0Y31 X1Y28-X1Y31
J N Configuration
N [LN] H [RN] (RCAL)
GTH Quad 230
HR I/O Bank 70
HP I/O Bank 30 HP I/O Bank 50 Configuration X1Y24-X1Y27
M
G [RN]
GTH Quad 229
PCIe
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 X1Y20-X1Y23
X0Y3
F [RN]
SLR Crossing
GTH Quad 128 GTH Quad 228
HP I/O Bank 68 PCIe
X0Y16-X0Y19 HP I/O Bank 48 X1Y16-X1Y19
F X0Y2
M [LS] (RCAL) E [RS]
GTH Quad 127 GTH Quad 227
HP I/O Bank 67 PCIe
X0Y12-X0Y15 HP I/O Bank 47 X1Y12-X1Y15
E X0Y1
L [LS] D [RS]
GTH Quad 126 GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
I D Configuration
K [LS] C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
HP I/O Bank 25 Configuration X1Y4-X1Y7
H C
B [RS]
PCIe GTH Quad 224
HP I/O Bank 44 HR I/O Bank
HP I/O Bank 24 X0Y0 X1Y0-X1Y3
G 84/94
(tandem) A [RS]
X16458-012917

Figure 1-31: XCKU115 Banks in FLVF1924 Package and XQKU115 Banks in RLF1924 Package

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X-Ref Target - Figure 1-32

GTH Quad 133 GTH Quad 233


HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y36-X0Y39 X1Y36-X1Y39
M Q X0Y5
M [LN] (RCAL) G [RN]
GTH Quad 132 GTH Quad 232
HP I/O Bank 52 HP I/O Bank 72 PCIe
X0Y32-X0Y35 X1Y32-X1Y35
L P X0Y4
L [LN] F [RN]
GTH Quad 131 GTH Quad 231
HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y28-X0Y31 X1Y28-X1Y31
K O Configuration
K [LN] E [RN] (RCAL)

HP I/O Bank 50 HR I/O Bank 70 GTH Quad 230


HP I/O Bank 30 Configuration
J N X1Y24-X1Y27

PCIe GTH Quad 229


HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69
X0Y3 X1Y20-X1Y23

SLR Crossing
GTH Quad 128
PCIe GTH Quad 228
X0Y16-X0Y19 HP I/O Bank 48 HP I/O Bank 68
X0Y2 X1Y16-X1Y19
J [LS] (RCAL)
GTH Quad 127 GTH Quad 227
HP I/O Bank 47 HP I/O Bank 67 PCIe
X0Y12-X0Y15 X1Y12-X1Y15
I E X0Y1
I [LS] D [RS]
GTH Quad 126 GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
H D Configuration
H [LS] C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
HP I/O Bank 25 Configuration X1Y4-X1Y7
G C
B [RS]
HR I/O Bank PCIe GTH Quad 224
HP I/O Bank 44
HP I/O Bank 24 84/94 X0Y0 X1Y0-X1Y3
F
B (tandem) A [RS]
X16459-062117

Figure 1-32: XCKU115 Banks in FLVA2104 Package

TIP: Bank 64 is labeled as 84/94 in some packages.

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X-Ref Target - Figure 1-33

GTH Quad 133 GTH Quad 233


HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y36-X0Y39 X1Y36-X1Y39
L O X0Y5
R [LN] (RCAL) J [RN]
GTH Quad 132 GTH Quad 232
HP I/O Bank 52 HP I/O Bank 72 PCIe
X0Y32-X0Y35 X1Y32-X1Y35
K N X0Y4
Q [LN] I [RN]
GTH Quad 131 GTH Quad 231
HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y28-X0Y31 X1Y28-X1Y31
J M Configuration
P [LN] H [RN] (RCAL)
GTH Quad 230
HP I/O Bank 30 HP I/O Bank 50 HR I/O Bank 70 Configuration X1Y24-X1Y27
G [RN]
GTH Quad 229
PCIe
HP I/O Bank 29 HP I/O Bank 49 HR I/O Bank 69 X1Y20-X1Y23
X0Y3
F [RN]
SLR Crossing
GTH Quad 128 GTH Quad 228
HP I/O Bank 68 PCIe
X0Y16-X0Y19 HP I/O Bank 48 X1Y16-X1Y19
F (Partial) X0Y2
M [LS] (RCAL) E [RS]
GTH Quad 127 GTH Quad 227
HP I/O Bank 67 PCIe
X0Y12-X0Y15 HP I/O Bank 47 X1Y12-X1Y15
E X0Y1
L [LS] D [RS]
GTH Quad 126 GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
I D Configuration
K [LS] C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 45 HR I/O Bank 65
HP I/O Bank 25 Configuration X1Y4-X1Y7
H C
B [RS]
HR I/O Bank PCIe GTH Quad 224
HP I/O Bank 44
HP I/O Bank 24 84/94 X0Y0 X1Y0-X1Y3
G
B (tandem) A [RS]
X16460-012917

Figure 1-33: XCKU115 Banks in FLVB2104 Package

TIP: Bank 64 is labeled as 84/94 in some packages.

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XCVU065 Bank Diagrams


X-Ref Target - Figure 1-34

GTY Quad 128 CMAC PCIe GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y16-X0Y19 X0Y2 X0Y1 X0Y16-X0Y19

GTY Quad 127 CMAC ILKN GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y12-X0Y15 X0Y1 X1Y2 X0Y12-X0Y15

GTH Quad 226


GTY Quad 126 ILKN SYSMON
HP I/O Bank 46 HP I/O Bank 66 X0Y8-X0Y11
X0Y8-X0Y11 X0Y1 Configuration
(RCAL)
GTY Quad 125
CMAC GTH Quad 225
X0Y4-X0Y7 HP I/O Bank 45 HP I/O Bank 65 Configuration
X0Y0 X0Y4-X0Y7
(RCAL)
PCIe
GTY Quad 124 ILKN HR I/O Bank GTH Quad 224
HP I/O Bank 44 X0Y0
X0Y0-X0Y3 X0Y0 84/94 X0Y0-X0Y3
(tandem)
X16466-012917

Figure 1-34: XCVU065 Banks


X-Ref Target - Figure 1-35

GTY Quad 128 GTH Quad 228


CMAC HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y16-X0Y19 X0Y16-X0Y19
X0Y2 K F X0Y1
J [L] E [R]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15 X0Y12-X0Y15
X0Y1 J E X1Y2
I [L] D [R]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X0Y8-X0Y11
X0Y1 I D Configuration
H [L] C [R] (RCAL)
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X0Y4-X0Y7
X0Y0 H C
G [L] (RCAL) B [R]
GTY Quad 124 HR I/O Bank PCIe GTH Quad 224
ILKN HP I/O Bank 44
X0Y0-X0Y3 84/94 X0Y0 X0Y0-X0Y3
X0Y0 G
F [L] B (tandem) A [R]
X16467-062117

Figure 1-35: XCVU065 Banks in FFVC1517 Package

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XCVU080 Bank Diagrams


X-Ref Target - Figure 1-36

GTY Quad 131 CMAC PCIe GTH Quad 231


HP I/O Bank 51 HP I/O Bank 71
X0Y28-X0Y31 X0Y3 X0Y3 X0Y28-X0Y31

GTY Quad 130 ILKN ILKN GTH Quad 230


HP I/O Bank 50 HP I/O Bank 70
X0Y24-X0Y27 X0Y4 X1Y4 X0Y24-X0Y27

GTY Quad 129


CMAC PCIe GTH Quad 229
X0Y20-X0Y23 HP I/O Bank 49 HP I/O Bank 69
X0Y2 X0Y2 X0Y20-X0Y23
(RCAL)

GTY Quad 128 ILKN PCIe GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y16-X0Y19 X0Y3 X0Y1 X0Y16-X0Y19

GTY Quad 127 CMAC ILKN GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y12-X0Y15 X0Y1 X1Y2 X0Y12-X0Y15

GTY Quad 126 ILKN SYSMON GTH Quad 226


HP I/O Bank 46 HP I/O Bank 66
X0Y8-X0Y11 X0Y1 Configuration X0Y8-X0Y11

GTH Quad 225


GTY Quad 125 CMAC
HP I/O Bank 45 HP I/O Bank 65 Configuration X0Y4-X0Y7
X0Y4-X0Y7 X0Y0
(RCAL)
PCIe
GTY Quad 124 ILKN HR I/O Bank GTH Quad 224
HP I/O Bank 44 X0Y0
X0Y0-X0Y3 X0Y0 84/94 X0Y0-X0Y3
(tandem)
X16468-062117

Figure 1-36: XCVU080 Banks

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X-Ref Target - Figure 1-37

GTY Quad 131 CMAC PCIe GTH Quad 231


HP I/O Bank 51 HP I/O Bank 71
X0Y28-X0Y31 X0Y3 X0Y3 X0Y28-X0Y31

GTY Quad 130 ILKN ILKN GTH Quad 230


HP I/O Bank 50 HP I/O Bank 70
X0Y24-X0Y27 X0Y4 X1Y4 X0Y24-X0Y27

GTY Quad 129


CMAC PCIe GTH Quad 229
X0Y20-X0Y23 HP I/O Bank 49 HP I/O Bank 69
X0Y2 X0Y2 X0Y20-X0Y23
J [L] (RCAL)
GTY Quad 128 GTH Quad 228
ILKN HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y16-X0Y19 X0Y16-X0Y19
X0Y3 K F X0Y1
I [L] E [R]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15 X0Y12-X0Y15
X0Y1 J E X1Y2
H [L] D [R]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X0Y8-X0Y11
X0Y1 I D Configuration
G [L] C [R]
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X0Y4-X0Y7
X0Y0 H C
F [L] B [R] (RCAL)
HR I/O Bank PCIe GTH Quad 224
GTY Quad 124 ILKN HP I/O Bank 44
84/94 X0Y0 X0Y0-X0Y3
X0Y0-X0Y3 X0Y0 G
B (tandem) A [R]
X16469-062117

Figure 1-37: XCVU080 Banks in FFVC1517 Package

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X-Ref Target - Figure 1-38

GTY Quad 131 GTH Quad 231


CMAC HP I/O Bank 71 PCIe
X0Y28-X0Y31 HP I/O Bank 51 X0Y28-X0Y31
X0Y3 H X0Y3
R [LN] H [RN]
GTY Quad 130 GTH Quad 230
ILKN HP I/O Bank 70 ILKN
X0Y24-X0Y27 HP I/O Bank 50 X0Y24-X0Y27
X0Y4 G X1Y4
Q [LN] G [RN]
GTY Quad 129 GTH Quad 229
CMAC HP I/O Bank 69 PCIe
X0Y20-X0Y23 HP I/O Bank 49 X0Y20-X0Y23
X0Y2 F X0Y2
P [LN] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
ILKN PCIe
X0Y16-X0Y19 HP I/O Bank 48 HP I/O Bank 68 X0Y16-X0Y19
X0Y3 X0Y1
O [LN] E [RS]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y12-X0Y15 HP I/O Bank 47 X0Y12-X0Y15
X0Y1 E (Partial) X1Y2
N [LS] D [RS]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 66 SYSMON
X0Y8-X0Y11 HP I/O Bank 46 X0Y8-X0Y11
X0Y1 D Configuration
M [LS] C [RS]
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 65
X0Y4-X0Y7 HP I/O Bank 45 Configuration X0Y4-X0Y7
X0Y0 C
L [LS] B [RS] (RCAL)
GTY Quad 124 HR I/O Bank PCIe GTH Quad 224
ILKN
X0Y0-X0Y3 HP I/O Bank 44 84/94 X0Y0 X0Y0-X0Y3
X0Y0
K [LS] B (tandem) A [RS]
X16470-062117

Figure 1-38: XCVU080 Banks in FFVD1517 Package

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X-Ref Target - Figure 1-39

GTY Quad 131 GTH Quad 231


CMAC HP I/O Bank 51 HP I/O Bank 71 PCIe
X0Y28-X0Y31 X0Y28-X0Y31
X0Y3 O (Partial) L X0Y3
M [L] H [RN]
GTY Quad 130 GTH Quad 230
ILKN HP I/O Bank 50 HP I/O Bank 70 ILKN
X0Y24-X0Y27 X0Y24-X0Y27
X0Y4 N K X1Y4
L [L] G [RN]
GTY Quad 129 GTH Quad 229
CMAC HP I/O Bank 49 PCIe
X0Y20-X0Y23 HP I/O Bank 69 X0Y20-X0Y23
X0Y2 M X0Y2
K [L] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
ILKN HP I/O Bank 48 PCIe
X0Y16-X0Y19 HP I/O Bank 68 X0Y16-X0Y19
X0Y3 J X0Y1
J [L] E [RS]
GTH Quad 227
GTY Quad 127 CMAC HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15
X0Y12-X0Y15 X0Y1 I E X1Y2
D [RS]
GTH Quad 226
GTY Quad 126 ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11
X0Y8-X0Y11 X0Y1 H D Configuration
C [RS]
GTH Quad 225
GTY Quad 125 CMAC HP I/O Bank 45 HP I/O Bank 65
Configuration X0Y4-X0Y7
X0Y4-X0Y7 X0Y0 G C
B [RS] (RCAL)
HR I/O Bank PCIe GTH Quad 224
GTY Quad 124 ILKN HP I/O Bank 44
84/94 X0Y0 X0Y0-X0Y3
X0Y0-X0Y3 X0Y0 F
B (tandem) A [RS]
X16471-062117

Figure 1-39: XCVU080 Banks in FFVB1760 Package

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X-Ref Target - Figure 1-40

GTY Quad 131 CMAC HP I/O Bank 51 HP I/O Bank 71 PCIe GTH Quad 231
X0Y28-X0Y31 X0Y3 M Q X0Y3 X0Y28-X0Y31
GTY Quad 130 GTH Quad 230
ILKN HP I/O Bank 50 HP I/O Bank 70 ILKN
X0Y24-X0Y27 X0Y24-X0Y27
X0Y4 L P X1Y4
M [LN] G [RN]
GTY Quad 129 GTH Quad 229
CMAC HP I/O Bank 49 HP I/O Bank 69 PCIe
X0Y20-X0Y23 X0Y20-X0Y23
X0Y2 K O X0Y2
L [LN] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
ILKN HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y16-X0Y19 X0Y16-X0Y19
X0Y3 J N X0Y1
K [LN] E [RN]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15 X0Y12-X0Y15
X0Y1 I E X1Y2
J [LS] D [RS]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X0Y8-X0Y11
X0Y1 H D Configuration
I [LS] C [RS]
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X0Y4-X0Y7
X0Y0 G C
H [LS] B [RS] (RCAL)
HR I/O Bank PCIe GTH Quad 224
GTY Quad 124 ILKN HP I/O Bank 44
84/94 X0Y0 X0Y0-X0Y3
X0Y0-X0Y3 X0Y0 F
B (tandem) A [RS]
X16472-062117

Figure 1-40: XCVU080 Banks in FFVA2104 Package

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X-Ref Target - Figure 1-41

GTY Quad 131 GTH Quad 231


CMAC HP I/O Bank 51 HP I/O Bank 71 PCIe
X0Y28-X0Y31 X0Y28-X0Y31
X0Y3 L O X0Y3
R [LN] H [RN]
GTY Quad 130 GTH Quad 230
ILKN HP I/O Bank 50 HP I/O Bank 70 ILKN
X0Y24-X0Y27 X0Y24-X0Y27
X0Y4 K N X1Y4
Q [LN] G [RN]
GTY Quad 129 GTH Quad 229
CMAC HP I/O Bank 49 HP I/O Bank 69 PCIe
X0Y20-X0Y23 X0Y20-X0Y23
X0Y2 J M X0Y2
P [LN] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
ILKN HP I/O Bank 68 PCIe
X0Y16-X0Y19 HP I/O Bank 48 X0Y16-X0Y19
X0Y3 F (Partial) X0Y1
O [LN] E [RS]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y12-X0Y15 HP I/O Bank 47 X0Y12-X0Y15
X0Y1 E X1Y2
N [LS] D [RS]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X0Y8-X0Y11
X0Y1 I D Configuration
M [LS] C [RS]
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X0Y4-X0Y7
X0Y0 H C
L [LS] B [RS] (RCAL)
GTY Quad 124 HR I/O Bank PCIe GTH Quad 224
ILKN HP I/O Bank 44
X0Y0-X0Y3 84/94 X0Y0 X0Y0-X0Y3
X0Y0 G
K [LS] B (tandem) A [RS]
X16473-062117

Figure 1-41: XCVU080 Banks in FFVB2104 Package

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XCVU095 Bank Diagrams


X-Ref Target - Figure 1-42

GTY Quad 131 CMAC PCIe GTH Quad 231


HP I/O Bank 51 HP I/O Bank 71
X0Y28-X0Y31 X0Y3 X0Y3 X0Y28-X0Y31

GTY Quad 130 ILKN ILKN GTH Quad 230


HP I/O Bank 50 HP I/O Bank 70
X0Y24-X0Y27 X0Y4 X1Y4 X0Y24-X0Y27

GTY Quad 129


CMAC PCIe GTH Quad 229
X0Y20-X0Y23 HP I/O Bank 49 HP I/O Bank 69
X0Y2 X0Y2 X0Y20-X0Y23
(RCAL)

GTY Quad 128 ILKN PCIe GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y16-X0Y19 X0Y3 X0Y1 X0Y16-X0Y19

GTY Quad 127 CMAC ILKN GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y12-X0Y15 X0Y1 X1Y2 X0Y12-X0Y15

GTY Quad 126 ILKN SYSMON GTH Quad 226


HP I/O Bank 46 HP I/O Bank 66
X0Y8-X0Y11 X0Y1 Configuration X0Y8-X0Y11

GTH Quad 225


GTY Quad 125 CMAC
HP I/O Bank 45 HP I/O Bank 65 Configuration X0Y4-X0Y7
X0Y4-X0Y7 X0Y0
(RCAL)
PCIe
GTY Quad 124 ILKN HR I/O Bank GTH Quad 224
HP I/O Bank 44 X0Y0
X0Y0-X0Y3 X0Y0 84/94 X0Y0-X0Y3
(tandem)
X16474-062117

Figure 1-42: XCVU095 Banks

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X-Ref Target - Figure 1-43

GTY Quad 131 CMAC PCIe GTH Quad 231


HP I/O Bank 51 HP I/O Bank 71
X0Y28-X0Y31 X0Y3 X0Y3 X0Y28-X0Y31

GTY Quad 130 ILKN ILKN GTH Quad 230


HP I/O Bank 50 HP I/O Bank 70
X0Y24-X0Y27 X0Y4 X1Y4 X0Y24-X0Y27

GTY Quad 129


CMAC PCIe GTH Quad 229
X0Y20-X0Y23 HP I/O Bank 49 HP I/O Bank 69
X0Y2 X0Y2 X0Y20-X0Y23
J [L] (RCAL)
GTY Quad 128 GTH Quad 228
ILKN HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y16-X0Y19 X0Y16-X0Y19
X0Y3 K F X0Y1
I [L] E [R]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15 X0Y12-X0Y15
X0Y1 J E X1Y2
H [L] D [R]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X0Y8-X0Y11
X0Y1 I D Configuration
G [L] C [R]
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X0Y4-X0Y7
X0Y0 H C
F [L] B [R] (RCAL)
HR I/O Bank PCIe GTH Quad 224
GTY Quad 124 ILKN HP I/O Bank 44
84/94 X0Y0 X0Y0-X0Y3
X0Y0-X0Y3 X0Y0 G
B (tandem) A [R]
X16475-062117

Figure 1-43: XCVU095 Banks in FFVC1517 Package

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X-Ref Target - Figure 1-44

GTY Quad 131 GTH Quad 231


CMAC HP I/O Bank 71 PCIe
X0Y28-X0Y31 HP I/O Bank 51 X0Y28-X0Y31
X0Y3 H X0Y3
R [LN] H [RN]
GTY Quad 130 GTH Quad 230
ILKN HP I/O Bank 70 ILKN
X0Y24-X0Y27 HP I/O Bank 50 X0Y24-X0Y27
X0Y4 G X1Y4
Q [LN] G [RN]
GTY Quad 129 GTH Quad 229
CMAC HP I/O Bank 69 PCIe
X0Y20-X0Y23 HP I/O Bank 49 X0Y20-X0Y23
X0Y2 F X0Y2
P [LN] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
ILKN PCIe
X0Y16-X0Y19 HP I/O Bank 48 HP I/O Bank 68 X0Y16-X0Y19
X0Y3 X0Y1
O [LN] E [RS]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y12-X0Y15 HP I/O Bank 47 X0Y12-X0Y15
X0Y1 E (Partial) X1Y2
N [LS] D [RS]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 66 SYSMON
X0Y8-X0Y11 HP I/O Bank 46 X0Y8-X0Y11
X0Y1 D Configuration
M [LS] C [RS]
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 65
X0Y4-X0Y7 HP I/O Bank 45 Configuration X0Y4-X0Y7
X0Y0 C
L [LS] B [RS] (RCAL)
GTY Quad 124 HR I/O Bank PCIe GTH Quad 224
ILKN
X0Y0-X0Y3 HP I/O Bank 44 84/94 X0Y0 X0Y0-X0Y3
X0Y0
K [LS] B (tandem) A [RS]
X16476-062117

Figure 1-44: XCVU095 Banks in FFVD1517 Package

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X-Ref Target - Figure 1-45

GTY Quad 131 GTH Quad 231


CMAC HP I/O Bank 51 HP I/O Bank 71 PCIe
X0Y28-X0Y31 X0Y28-X0Y31
X0Y3 O (Partial) L X0Y3
M [L] H [RN]
GTY Quad 130 GTH Quad 230
ILKN HP I/O Bank 50 HP I/O Bank 70 ILKN
X0Y24-X0Y27 X0Y24-X0Y27
X0Y4 N K X1Y4
L [L] G [RN]
GTY Quad 129 GTH Quad 229
CMAC HP I/O Bank 49 PCIe
X0Y20-X0Y23 HP I/O Bank 69 X0Y20-X0Y23
X0Y2 M X0Y2
K [L] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
ILKN HP I/O Bank 48 PCIe
X0Y16-X0Y19 HP I/O Bank 68 X0Y16-X0Y19
X0Y3 J X0Y1
J [L] E [RS]
GTH Quad 227
GTY Quad 127 CMAC HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15
X0Y12-X0Y15 X0Y1 I E X1Y2
D [RS]
GTH Quad 226
GTY Quad 126 ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11
X0Y8-X0Y11 X0Y1 H D Configuration
C [RS]
GTH Quad 225
GTY Quad 125 CMAC HP I/O Bank 45 HP I/O Bank 65
Configuration X0Y4-X0Y7
X0Y4-X0Y7 X0Y0 G C
B [RS] (RCAL)
HR I/O Bank PCIe GTH Quad 224
GTY Quad 124 ILKN HP I/O Bank 44
84/94 X0Y0 X0Y0-X0Y3
X0Y0-X0Y3 X0Y0 F
B (tandem) A [RS]
X16477-062117

Figure 1-45: XCVU095 Banks in FFVB1760 Package

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X-Ref Target - Figure 1-46

GTY Quad 131 CMAC HP I/O Bank 51 HP I/O Bank 71 PCIe GTH Quad 231
X0Y28-X0Y31 X0Y3 M Q X0Y3 X0Y28-X0Y31

GTY Quad 130 GTH Quad 230


ILKN HP I/O Bank 50 HP I/O Bank 70 ILKN
X0Y24-X0Y27 X0Y24-X0Y27
X0Y4 L P X1Y4
M [LN] G [RN]
GTY Quad 129 GTH Quad 229
CMAC HP I/O Bank 49 HP I/O Bank 69 PCIe
X0Y20-X0Y23 X0Y20-X0Y23
X0Y2 K O X0Y2
L [LN] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
ILKN HP I/O Bank 48 HP I/O Bank 68 PCIe
X0Y16-X0Y19 X0Y16-X0Y19
X0Y3 J N X0Y1
K [LN] E [RN]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15 X0Y12-X0Y15
X0Y1 I E X1Y2
J [LS] D [RS]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X0Y8-X0Y11
X0Y1 H D Configuration
I [LS] C [RS]
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X0Y4-X0Y7
X0Y0 G C
H [LS] B [RS] (RCAL)
HR I/O Bank PCIe GTH Quad 224
GTY Quad 124 ILKN HP I/O Bank 44
84/94 X0Y0 X0Y0-X0Y3
X0Y0-X0Y3 X0Y0 F
B (tandem) A [RS]
X16478-062117

Figure 1-46: XCVU095 Banks in FFVA2104 Package

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X-Ref Target - Figure 1-47

GTY Quad 131 GTH Quad 231


CMAC HP I/O Bank 51 HP I/O Bank 71 PCIe
X0Y28-X0Y31 X0Y28-X0Y31
X0Y3 L O X0Y3
R [LN] H [RN]
GTY Quad 130 GTH Quad 230
ILKN HP I/O Bank 50 HP I/O Bank 70 ILKN
X0Y24-X0Y27 X0Y24-X0Y27
X0Y4 K N X1Y4
Q [LN] G [RN]
GTY Quad 129 GTH Quad 229
CMAC HP I/O Bank 49 HP I/O Bank 69 PCIe
X0Y20-X0Y23 X0Y20-X0Y23
X0Y2 J M X0Y2
P [LN] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
ILKN HP I/O Bank 68 PCIe
X0Y16-X0Y19 HP I/O Bank 48 X0Y16-X0Y19
X0Y3 F (Partial) X0Y1
O [LN] E [RS]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y12-X0Y15 HP I/O Bank 47 X0Y12-X0Y15
X0Y1 E X1Y2
N [LS] D [RS]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X0Y8-X0Y11
X0Y1 I D Configuration
M [LS] C [RS]
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X0Y4-X0Y7
X0Y0 H C
L [LS] B [RS] (RCAL)
GTY Quad 124 HR I/O Bank PCIe GTH Quad 224
ILKN HP I/O Bank 44
X0Y0-X0Y3 84/94 X0Y0 X0Y0-X0Y3
X0Y0 G
K [LS] B (tandem) A [RS]
X16479-062117

Figure 1-47: XCVU095 Banks in FFVB2104 Package

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X-Ref Target - Figure 1-48

GTY Quad 131 GTH Quad 231


CMAC HP I/O Bank 71 PCIe
X0Y28-X0Y31 HP I/O Bank 51 X0Y28-X0Y31
X0Y3 I X0Y3
U [LN] H [RN]
GTY Quad 130 GTH Quad 230
ILKN HP I/O Bank 70 ILKN
X0Y24-X0Y27 HP I/O Bank 50 X0Y24-X0Y27
X0Y4 H X1Y4
T [LN] G [RN]
GTY Quad 129 GTH Quad 229
CMAC HP I/O Bank 69 PCIe
X0Y20-X0Y23 HP I/O Bank 49 X0Y20-X0Y23
X0Y2 G X0Y2
S [LN] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
ILKN HP I/O Bank 68 PCIe
X0Y16-X0Y19 HP I/O Bank 48 X0Y16-X0Y19
X0Y3 F X0Y1
R [LC] E [RC]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y12-X0Y15 HP I/O Bank 47 X0Y12-X0Y15
X0Y1 E X1Y2
Q [LC] D [RC]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 66 SYSMON
X0Y8-X0Y11 HP I/O Bank 46 X0Y8-X0Y11
X0Y1 D Configuration
P [LC] C [RC]
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 65
X0Y4-X0Y7 HP I/O Bank 45 Configuration X0Y4-X0Y7
X0Y0 C
O [LC] B [RC] (RCAL)
GTY Quad 124 HR I/O Bank PCIe GTH Quad 224
ILKN
X0Y0-X0Y3 HP I/O Bank 44 84/94 X0Y0 X0Y0-X0Y3
X0Y0
N [LC] B (tandem) A [RC]
X16480-062117

Figure 1-48: XCVU095 Banks in FFVC2104 Package

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XCVU125 Bank Diagrams


X-Ref Target - Figure 1-49

GTY Quad 133 CMAC PCIe GTH Quad 233


HP I/O Bank 53 HP I/O Bank 73
X0Y36-X0Y39 X0Y5 X0Y3 X0Y36-X0Y39

GTY Quad 132 CMAC ILKN GTH Quad 232


HP I/O Bank 52 HP I/O Bank 72
X0Y32-X0Y35 X0Y4 X1Y5 X0Y32-X0Y35

GTH Quad 231


GTY Quad 131 ILKN SYSMON
HP I/O Bank 51 HP I/O Bank 71 X0Y28-X0Y31
X0Y28-X0Y31 X0Y4 Configuration
(RCAL)
GTY Quad 130
CMAC GTH Quad 230
X0Y24-X0Y27 HP I/O Bank 50 HP I/O Bank 70 Configuration
X0Y3 X0Y24-X0Y27
(RCAL)

GTY Quad 129 ILKN PCIe GTH Quad 229


HP I/O Bank 49 HR I/O Bank 69
X0Y20-X0Y23 X0Y3 X0Y2 X0Y20-X0Y23

SLR Crossing

GTY Quad 128 CMAC PCIe GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y16-X0Y19 X0Y2 X0Y1 X0Y16-X0Y19

GTY Quad 127 CMAC ILKN GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y12-X0Y15 X0Y1 X1Y2 X0Y12-X0Y15

GTH Quad 226


GTY Quad 126 ILKN SYSMON
HP I/O Bank 46 HP I/O Bank 66 X0Y8-X0Y11
X0Y8-X0Y11 X0Y1 Configuration
(RCAL)
GTY Quad 125
CMAC GTH Quad 225
X0Y4-X0Y7 HP I/O Bank 45 HP I/O Bank 65 Configuration
X0Y0 X0Y4-X0Y7
(RCAL)
PCIe
GTY Quad 124 ILKN HR I/O Bank GTH Quad 224
HP I/O Bank 44 X0Y0
X0Y0-X0Y3 X0Y0 84/94 X0Y0-X0Y3
(tandem)
X16481-012917

Figure 1-49: XCVU125 Banks

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X-Ref Target - Figure 1-50

GTH Quad 233


GTY Quad 133 CMAC HP I/O Bank 73 PCIe
HP I/O Bank 53 X0Y36-X0Y39
X0Y36-X0Y39 X0Y5 H X0Y3
J [RN]
GTY Quad 132 GTH Quad 232
CMAC HP I/O Bank 72 ILKN
X0Y32-X0Y35 HP I/O Bank 52 X0Y32-X0Y35
X0Y4 G X1Y5
R [LN] I [RN]
GTY Quad 131 GTH Quad 231
ILKN HP I/O Bank 71 SYSMON
X0Y28-X0Y31 HP I/O Bank 51 X0Y28-X0Y31
X0Y4 F Configuration
Q [LN] H [RN] (RCAL)
GTY Quad 130 GTH Quad 230
CMAC
X0Y24-X0Y27 HP I/O Bank 50 HP I/O Bank 70 Configuration X0Y24-X0Y27
X0Y3
P [LN] (RCAL) G [RN]
GTY Quad 129 GTH Quad 229
ILKN PCIe
X0Y20-X0Y23 HP I/O Bank 49 HR I/O Bank 69 X0Y20-X0Y23
X0Y3 X0Y2
O [LN] F [RN]
SLR Crossing
GTH Quad 228
GTY Quad 128 CMAC PCIe
HP I/O Bank 48 HP I/O Bank 68 X0Y16-X0Y19
X0Y16-X0Y19 X0Y2 X0Y1
E [RS]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y12-X0Y15 HP I/O Bank 47 X0Y12-X0Y15
X0Y1 E (Partial) X1Y2
N [LS] D [RS]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 66 SYSMON
X0Y8-X0Y11 HP I/O Bank 46 X0Y8-X0Y11
X0Y1 D Configuration
M [LS] C [RS] (RCAL)
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 65
X0Y4-X0Y7 HP I/O Bank 45 Configuration X0Y4-X0Y7
X0Y0 C
L [LS] (RCAL) B [RS]
GTY Quad 124 HR I/O Bank PCIe GTH Quad 224
ILKN
X0Y0-X0Y3 HP I/O Bank 44 84/94 X0Y0 X0Y0-X0Y3
X0Y0
K [LS] B (tandem) A [RS]
X16482-031820

Figure 1-50: XCVU125 Banks in FLVD1517 Package

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X-Ref Target - Figure 1-51

GTH Quad 233


GTY Quad 133 CMAC HP I/O Bank 53 PCIe
HP I/O Bank 73 X0Y36-X0Y39
X0Y36-X0Y39 X0Y5 O (Partial) X0Y3
I [RN]
GTY Quad 132 GTH Quad 232
CMAC HP I/O Bank 52 ILKN
X0Y32-X0Y35 HP I/O Bank 72 X0Y32-X0Y35
X0Y4 N X1Y5
M [L] H [RN]
GTY Quad 131 GTH Quad 231
ILKN HP I/O Bank 51 SYSMON
X0Y28-X0Y31 HP I/O Bank 71 X0Y28-X0Y31
X0Y4 M Configuration
L [L] G [RN] (RCAL)
GTY Quad 130 GTH Quad 230
CMAC HP I/O Bank 50
X0Y24-X0Y27 HP I/O Bank 70 Configuration X0Y24-X0Y27
X0Y3 L
K [L] (RCAL) F [RN]
GTY Quad 129
ILKN HP I/O Bank 49 PCIe GTH Quad 229
X0Y20-X0Y23 HR I/O Bank 69
X0Y3 K X0Y2 X0Y20-X0Y23
J [L]
SLR Crossing
GTH Quad 228
GTY Quad 128 CMAC HP I/O Bank 48 PCIe
HP I/O Bank 68 X0Y16-X0Y19
X0Y16-X0Y19 X0Y2 J X0Y1
E [RS]
GTH Quad 227
GTY Quad 127 CMAC HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15
X0Y12-X0Y15 X0Y1 I E X1Y2
D [RS]
GTH Quad 226
GTY Quad 126 ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11
X0Y8-X0Y11 X0Y1 H D Configuration
C [RS] (RCAL)
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X0Y4-X0Y7
X0Y0 G C
(RCAL) B [RS]
HR I/O Bank PCIe GTH Quad 224
GTY Quad 124 ILKN HP I/O Bank 44
84/94 X0Y0 X0Y0-X0Y3
X0Y0-X0Y3 X0Y0 F
B (tandem) A [RS]
X16483-031820

Figure 1-51: XCVU125 Banks in FLVB1760 Package

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X-Ref Target - Figure 1-52

GTH Quad 233


GTY Quad 133 CMAC HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y36-X0Y39
X0Y36-X0Y39 X0Y5 M Q X0Y3
G [RN]
GTY Quad 132 GTH Quad 232
CMAC HP I/O Bank 52 HP I/O Bank 72 ILKN
X0Y32-X0Y35 X0Y32-X0Y35
X0Y4 L P X1Y5
M [LN] F [RN]
GTY Quad 131 GTH Quad 231
ILKN HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y28-X0Y31 X0Y28-X0Y31
X0Y4 K O Configuration
L [LN] E [RN] (RCAL)
GTY Quad 130
CMAC HP I/O Bank 50 HP I/O Bank 70 GTH Quad 230
X0Y24-X0Y27 Configuration
X0Y3 J N X0Y24-X0Y27
K [LN] (RCAL)

GTY Quad 129 ILKN PCIe GTH Quad 229


HP I/O Bank 49 HR I/O Bank 69
X0Y20-X0Y23 X0Y3 X0Y2 X0Y20-X0Y23

SLR Crossing

GTY Quad 128 CMAC PCIe GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y16-X0Y19 X0Y2 X0Y1 X0Y16-X0Y19

GTY Quad 127 GTH Quad 227


CMAC HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15 X0Y12-X0Y15
X0Y1 I E X1Y2
J [LS] D [RS]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X0Y8-X0Y11
X0Y1 H D Configuration
I [LS] C [RS] (RCAL)
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X0Y4-X0Y7
X0Y0 G C
H [LS] (RCAL) B [RS]
HR I/O Bank PCIe GTH Quad 224
GTY Quad 124 ILKN HP I/O Bank 44
84/94 X0Y0 X0Y0-X0Y3
X0Y0-X0Y3 X0Y0 F
B (tandem) A [RS]
X16484-031820

Figure 1-52: XCVU125 Banks in FLVA2104 Package

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X-Ref Target - Figure 1-53

GTY Quad 133 GTH Quad 233


CMAC PCIe
X0Y36-X0Y39 HP I/O Bank 53 HP I/O Bank 73 X0Y36-X0Y39
X0Y5 X0Y3
S [LN] J [RN]
GTY Quad 132 GTH Quad 232
CMAC HP I/O Bank 52 HP I/O Bank 72 ILKN
X0Y32-X0Y35 X0Y32-X0Y35
X0Y4 L O X1Y5
R [LN] I [RN]
GTY Quad 131 GTH Quad 231
ILKN HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y28-X0Y31 X0Y28-X0Y31
X0Y4 K N Configuration
Q [LN] H [RN] (RCAL)
GTY Quad 130 GTH Quad 230
CMAC HP I/O Bank 50 HP I/O Bank 70
X0Y24-X0Y27 Configuration X0Y24-X0Y27
X0Y3 J M
P [LN] (RCAL) G [RN]
GTY Quad 129 GTH Quad 229
ILKN PCIe
X0Y20-X0Y23 HP I/O Bank 49 HR I/O Bank 69 X0Y20-X0Y23
X0Y3 X0Y2
O [LN] F [RN]
SLR Crossing
GTY Quad 128 GTH Quad 228
CMAC HP I/O Bank 68 PCIe
X0Y16-X0Y19 HP I/O Bank 48 X0Y16-X0Y19
X0Y2 F (Partial) X0Y1
N [LS] E [RS]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y12-X0Y15 HP I/O Bank 47 X0Y12-X0Y15
X0Y1 E X1Y2
M [LS] D [RS]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X0Y8-X0Y11
X0Y1 I D Configuration
L [LS] C [RS] (RCAL)
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X0Y4-X0Y7
X0Y0 H C
K [LS] (RCAL) B [RS]
GTY Quad 124 HR I/O Bank PCIe GTH Quad 224
ILKN HP I/O Bank 44
X0Y0-X0Y3 84/94 X0Y0 X0Y0-X0Y3
X0Y0 G
N [LC] B (tandem) A [RS]
X16485-031820

Figure 1-53: XCVU125 Banks in FLVB2104 Package

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X-Ref Target - Figure 1-54

GTY Quad 133 GTH Quad 233


CMAC PCIe
X0Y36-X0Y39 HP I/O Bank 53 HP I/O Bank 73 X0Y36-X0Y39
X0Y5 X0Y3
W [LN] J [RN]
GTY Quad 132 GTH Quad 232
CMAC HP I/O Bank 72 ILKN
X0Y32-X0Y35 HP I/O Bank 52 X0Y32-X0Y35
X0Y4 I X1Y5
V [LN] I [RN]
GTY Quad 131 GTH Quad 231
ILKN HP I/O Bank 71 SYSMON
X0Y28-X0Y31 HP I/O Bank 51 X0Y28-X0Y31
X0Y4 H Configuration
U [LN] H [RN] (RCAL)
GTY Quad 130 GTH Quad 230
CMAC HP I/O Bank 70
X0Y24-X0Y27 HP I/O Bank 50 Configuration X0Y24-X0Y27
X0Y3 G
T [LN] (RCAL) G [RN]
GTY Quad 129 GTH Quad 229
ILKN PCIe
X0Y20-X0Y23 HP I/O Bank 49 HR I/O Bank 69 X0Y20-X0Y23
X0Y3 X0Y2
S [LN] F [RN]
SLR Crossing
GTY Quad 128 GTH Quad 228
CMAC HP I/O Bank 68 PCIe
X0Y16-X0Y19 HP I/O Bank 48 X0Y16-X0Y19
X0Y2 F X0Y1
R [LC] E [RC]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y12-X0Y15 HP I/O Bank 47 X0Y12-X0Y15
X0Y1 E X1Y2
Q [LC] D [RC]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 66 SYSMON
X0Y8-X0Y11 HP I/O Bank 46 X0Y8-X0Y11
X0Y1 D Configuration
P [LC] C [RC] (RCAL)
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 65
X0Y4-X0Y7 HP I/O Bank 45 Configuration X0Y4-X0Y7
X0Y0 C
O [LC] (RCAL) B [RC]
GTY Quad 124 HR I/O Bank PCIe GTH Quad 224
ILKN
X0Y0-X0Y3 HP I/O Bank 44 84/94 X0Y0 X0Y0-X0Y3
X0Y0
N [LC] B (tandem) A [RC]
X16486-031720

Figure 1-54: XCVU125 Banks in FLVC2104 Package

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XCVU160 Bank Diagrams


X-Ref Target - Figure 1-55

GTY Quad 133 CMAC PCIe GTH Quad 233


HP I/O Bank 53 HP I/O Bank 73
X0Y52-X0Y55 X0Y8 X0Y4 X0Y52-X0Y55

GTY Quad 132 CMAC ILKN GTH Quad 232


HP I/O Bank 52 HP I/O Bank 72
X0Y45-X0Y51 X0Y7 X1Y7 X0Y45-X0Y51

GTH Quad 231


GTY Quad 131 ILKN SYSMON
HP I/O Bank 51 HP I/O Bank 71 X0Y44-X0Y47
X0Y44-X0Y47 X0Y6 Configuration
(RCAL)
GTY Quad 130
CMAC GTH Quad 230
X0Y40-X0Y43 HP I/O Bank 50 HP I/O Bank 70 Configuration
X0Y6 X0Y40-X0Y43
(RCAL)

GTY Quad 129 ILKN PCIe GTH Quad 229


HP I/O Bank 49 HR I/O Bank 69
X0Y36-X0Y39 X0Y5 X0Y3 X0Y36-X0Y39

SLR Crossing

GTY Quad 128 CMAC PCIe GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y32-X0Y35 X0Y5 X0Y2 X0Y32-X0Y35

GTY Quad 127 CMAC ILKN GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y28-X0Y31 X0Y4 X1Y4 X0Y28-X0Y31

GTH Quad 226


GTY Quad 126 ILKN SYSMON
HP I/O Bank 46 HP I/O Bank 66 X0Y24-X0Y27
X0Y24-X0Y27 X0Y2 Configuration
(RCAL)
GTY Quad 125
CMAC GTH Quad 225
X0Y20-X0Y23 HP I/O Bank 45 HP I/O Bank 65 Configuration
X0Y3 X0Y20-X0Y23
(RCAL)
PCIe
GTY Quad 124 ILKN HR I/O Bank GTH Quad 224
HP I/O Bank 44 X0Y1
X0Y16-X0Y19 X0Y2 84/94 X0Y16-X0Y19
(tandem)
SLR Crossing

GTY Quad 123 CMAC PCIe GTH Quad 223


HP I/O Bank 43 HP I/O Bank 63
X0Y12-X0Y15 X0Y2 X0Y0 X0Y12-X0Y15

GTY Quad 122 CMAC ILKN GTH Quad 222


HP I/O Bank 42 HP I/O Bank 62
X0Y8-X0Y11 X0Y1 X1Y1 X0Y8-X0Y11

GTH Quad 221


GTY Quad 121 ILKN SYSMON
HP I/O Bank 41 HP I/O Bank 61 X0Y4-X0Y7
X0Y4-X0Y7 X0Y0 Configuration
(RCAL)
GTY Quad 120
CMAC GTH Quad 220
X0Y0-X0Y3 HP I/O Bank 40 HP I/O Bank 60 Configuration
X0Y0 X0Y0-X0Y3
(RCAL)
X16488-012917

Figure 1-55: XCVU160 Banks

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X-Ref Target - Figure 1-56

GTY Quad 133 GTH Quad 233


CMAC PCIe
X0Y52-X0Y55 HP I/O Bank 53 HP I/O Bank 73 X0Y52-X0Y55
X0Y8 X0Y4
S [LN] J [RN]
GTY Quad 132 GTH Quad 232
CMAC HP I/O Bank 52 HP I/O Bank 72 ILKN
X0Y45-X0Y51 X0Y45-X0Y51
X0Y7 L O X1Y7
R [LN] I [RN]
GTY Quad 131 GTH Quad 231
ILKN HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y44-X0Y47 X0Y44-X0Y47
X0Y6 K N Configuration
Q [LN] H [RN] (RCAL)
GTY Quad 130 GTH Quad 230
CMAC HP I/O Bank 50 HP I/O Bank 70
X0Y40-X0Y43 Configuration X0Y40-X0Y43
X0Y6 J M
P [LN] (RCAL) G [RN]
GTY Quad 129 GTH Quad 229
ILKN PCIe
X0Y36-X0Y39 HP I/O Bank 49 HR I/O Bank 69 X0Y36-X0Y39
X0Y5 X0Y3
O [LN] F [RN]
SLR Crossing
GTY Quad 128 GTH Quad 228
CMAC HP I/O Bank 68 PCIe
X0Y32-X0Y35 HP I/O Bank 48 X0Y32-X0Y35
X0Y5 F (Partial) X0Y2
N [LS] E [RS]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y28-X0Y31 HP I/O Bank 47 X0Y28-X0Y31
X0Y4 E X1Y4
M [LS] D [RS]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y24-X0Y27 X0Y24-X0Y27
X0Y2 I D Configuration
L [LS] C [RS] (RCAL)
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y20-X0Y23 Configuration X0Y20-X0Y23
X0Y3 H C
K [LS] (RCAL) B [RS]
HR I/O Bank PCIe GTH Quad 224
GTY Quad 124 ILKN HP I/O Bank 44
84/94 X0Y1 X0Y16-X0Y19
X0Y16-X0Y19 X0Y2 G
B (tandem) A [RS]
SLR Crossing

GTY Quad 123 CMAC PCIe GTH Quad 223


HP I/O Bank 43 HP I/O Bank 63
X0Y12-X0Y15 X0Y2 X0Y0 X0Y12-X0Y15

GTY Quad 122 CMAC ILKN GTH Quad 222


HP I/O Bank 42 HP I/O Bank 62
X0Y8-X0Y11 X0Y1 X1Y1 X0Y8-X0Y11

GTH Quad 221


GTY Quad 121 ILKN SYSMON
HP I/O Bank 41 HP I/O Bank 61 X0Y4-X0Y7
X0Y4-X0Y7 X0Y0 Configuration
(RCAL)
GTY Quad 120
CMAC GTH Quad 220
X0Y0-X0Y3 HP I/O Bank 40 HP I/O Bank 60 Configuration
X0Y0 X0Y0-X0Y3
(RCAL)
X16489-012917

Figure 1-56: XCVU160 Banks in FLGB2104 Package

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X-Ref Target - Figure 1-57

GTY Quad 133 GTH Quad 233


CMAC PCIe
X0Y52-X0Y55 HP I/O Bank 53 HP I/O Bank 73 X0Y52-X0Y55
X0Y8 X0Y4
W [LN] J [RN]
GTY Quad 132 GTH Quad 232
CMAC HP I/O Bank 52 HP I/O Bank 72 ILKN
X0Y45-X0Y51 X0Y45-X0Y51
X0Y7 L I X1Y7
V [LN] I [RN]
GTY Quad 131 GTH Quad 231
ILKN HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y44-X0Y47 X0Y44-X0Y47
X0Y6 K H Configuration
U [LN] H [RN] (RCAL)
GTY Quad 130 GTH Quad 230
CMAC HP I/O Bank 50 HP I/O Bank 70
X0Y40-X0Y43 Configuration X0Y40-X0Y43
X0Y6 J G
T [LN] (RCAL) G [RN]
GTY Quad 129 GTH Quad 229
ILKN PCIe
X0Y36-X0Y39 HP I/O Bank 49 HR I/O Bank 69 X0Y36-X0Y39
X0Y5 X0Y3
S [LN] F [RN]
SLR Crossing
GTY Quad 128 GTH Quad 228
CMAC HP I/O Bank 68 PCIe
X0Y32-X0Y35 HP I/O Bank 48 X0Y32-X0Y35
X0Y5 F X0Y2
R [LC] E [RC]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y28-X0Y31 HP I/O Bank 47 X0Y28-X0Y31
X0Y4 E X1Y4
Q [LC] D [RC]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y24-X0Y27 X0Y24-X0Y27
X0Y2 I D Configuration
P [LC] C [RC] (RCAL)
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y20-X0Y23 Configuration X0Y20-X0Y23
X0Y3 H C
O [LC] (RCAL) B [RC]
GTY Quad 124 HR I/O Bank PCIe GTH Quad 224
ILKN HP I/O Bank 44
X0Y16-X0Y19 84/94 X0Y1 X0Y16-X0Y19
X0Y2 G
N [LC] B (tandem) A [RC]
SLR Crossing

GTY Quad 123 CMAC PCIe GTH Quad 223


HP I/O Bank 43 HP I/O Bank 63
X0Y12-X0Y15 X0Y2 X0Y0 X0Y12-X0Y15

GTY Quad 122 GTH Quad 222


CMAC ILKN
X0Y8-X0Y11 HP I/O Bank 42 HP I/O Bank 62 X0Y8-X0Y11
X0Y1 X1Y1
Z [LS] M [RS]
GTY Quad 121 GTH Quad 221
ILKN SYSMON
X0Y4-X0Y7 HP I/O Bank 41 HP I/O Bank 61 X0Y4-X0Y7
X0Y0 Configuration
Y [LS] L [RS] (RCAL)
GTY Quad 120 GTH Quad 220
CMAC
X0Y0-X0Y3 HP I/O Bank 40 HP I/O Bank 60 Configuration X0Y0-X0Y3
X0Y0
X [LS] (RCAL) K [RS]
X16490-012917

Figure 1-57: XCVU160 Banks in FLGC2104 Package

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XCVU190 Bank Diagrams


X-Ref Target - Figure 1-58

GTY Quad 133 CMAC PCIe GTH Quad 233


HP I/O Bank 53 HP I/O Bank 73
X0Y56-X0Y59 X0Y8 X0Y5 X0Y56-X0Y59

GTY Quad 132 CMAC ILKN GTH Quad 232


HP I/O Bank 52 HP I/O Bank 72
X0Y52-X0Y55 X0Y7 X1Y8 X0Y52-X0Y55

GTH Quad 231


GTY Quad 131 ILKN SYSMON
HP I/O Bank 51 HP I/O Bank 71 X0Y48-X0Y51
X0Y48-X0Y51 X0Y7 Configuration
(RCAL)
GTY Quad 130
CMAC GTH Quad 230
X0Y44-X0Y47 HP I/O Bank 50 HP I/O Bank 70 Configuration
X0Y6 X0Y44-X0Y47
(RCAL)

GTY Quad 129 ILKN PCIe GTH Quad 229


HP I/O Bank 49 HR I/O Bank 69
X0Y40-X0Y43 X0Y6 X0Y4 X0Y40-X0Y43

SLR Crossing

GTY Quad 128 CMAC PCIe GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y36-X0Y39 X0Y5 X0Y3 X0Y36-X0Y39

GTY Quad 127 CMAC ILKN GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y32-X0Y35 X0Y4 X1Y5 X0Y32-X0Y35

GTH Quad 226


GTY Quad 126 ILKN SYSMON
HP I/O Bank 46 HP I/O Bank 66 X0Y28-X0Y31
X0Y28-X0Y31 X0Y4 Configuration
(RCAL)
GTY Quad 125
CMAC GTH Quad 225
X0Y24-X0Y27 HP I/O Bank 45 HP I/O Bank 65 Configuration
X0Y3 X0Y24-X0Y27
(RCAL)
PCIe
GTY Quad 124 ILKN HR I/O Bank GTH Quad 224
HP I/O Bank 44 X0Y2
X0Y20-X0Y23 X0Y3 84/94 X0Y20-X0Y23
(tandem)
SLR Crossing

GTY Quad 123 CMAC PCIe GTH Quad 223


HP I/O Bank 43 HP I/O Bank 63
X0Y16-X0Y19 X0Y2 X0Y1 X0Y16-X0Y19

GTY Quad 122 CMAC ILKN GTH Quad 222


HP I/O Bank 42 HP I/O Bank 62
X0Y12-X0Y15 X0Y1 X1Y2 X0Y12-X0Y15

GTH Quad 221


GTY Quad 121 ILKN SYSMON
HP I/O Bank 41 HP I/O Bank 61 X0Y8-X0Y11
X0Y8-X0Y11 X0Y1 Configuration
(RCAL)
GTY Quad 120
CMAC GTH Quad 220
X0Y4-X0Y7 HP I/O Bank 40 HP I/O Bank 60 Configuration
X0Y0 X0Y4-X0Y7
(RCAL)

GTY Quad 119 ILKN PCIe GTH Quad 219


HP I/O Bank 39 HR I/O Bank 59
X0Y0-X0Y3 X0Y0 X0Y0 X0Y0-X0Y3

X16491-012917

Figure 1-58: XCVU190 Banks

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X-Ref Target - Figure 1-59

GTY Quad 133 GTH Quad 233


CMAC PCIe
X0Y56-X0Y59 HP I/O Bank 53 HP I/O Bank 73 X0Y56-X0Y59
X0Y8 X0Y5
S [LN] J [RN]
GTY Quad 132 GTH Quad 232
CMAC HP I/O Bank 52 HP I/O Bank 72 ILKN
X0Y52-X0Y55 X0Y52-X0Y55
X0Y7 L O X1Y8
R [LN] I [RN]
GTY Quad 131 GTH Quad 231
ILKN HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y48-X0Y51 X0Y48-X0Y51
X0Y7 K N Configuration
Q [LN] H [RN] (RCAL)
GTY Quad 130 GTH Quad 230
CMAC HP I/O Bank 50 HP I/O Bank 70
X0Y44-X0Y47 Configuration X0Y44-X0Y47
X0Y6 J M
P [LN] (RCAL) G [RN]
GTY Quad 129 GTH Quad 229
ILKN PCIe
X0Y40-X0Y43 HP I/O Bank 49 HR I/O Bank 69 X0Y40-X0Y43
X0Y6 X0Y4
O [LN] F [RN]
SLR Crossing
GTY Quad 128 GTH Quad 228
CMAC HP I/O Bank 68 PCIe
X0Y36-X0Y39 HP I/O Bank 48 X0Y36-X0Y39
X0Y5 F (Partial) X0Y3
N [LS] E [RS]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y32-X0Y35 HP I/O Bank 47 X0Y32-X0Y35
X0Y4 E X1Y5
M [LS] D [RS]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y28-X0Y31 X0Y28-X0Y31
X0Y4 I D Configuration
L [LS] C [RS] (RCAL)
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y24-X0Y27 Configuration X0Y24-X0Y27
X0Y3 H C
K [LS] (RCAL) B [RS]
HR I/O Bank PCIe GTH Quad 224
GTY Quad 124 ILKN HP I/O Bank 44
84/94 X0Y2 X0Y20-X0Y23
X0Y20-X0Y23 X0Y3 G
B (tandem) A [RS]
SLR Crossing

GTY Quad 123 CMAC PCIe GTH Quad 223


HP I/O Bank 43 HP I/O Bank 63
X0Y16-X0Y19 X0Y2 X0Y1 X0Y16-X0Y19

GTY Quad 122 CMAC ILKN GTH Quad 222


HP I/O Bank 42 HP I/O Bank 62
X0Y12-X0Y15 X0Y1 X1Y2 X0Y12-X0Y15

GTH Quad 221


GTY Quad 121 ILKN SYSMON
HP I/O Bank 41 HP I/O Bank 61 X0Y8-X0Y11
X0Y8-X0Y11 X0Y1 Configuration
(RCAL)
GTY Quad 120
CMAC GTH Quad 220
X0Y4-X0Y7 HP I/O Bank 40 HP I/O Bank 60 Configuration
X0Y0 X0Y4-X0Y7
(RCAL)

GTY Quad 119 ILKN PCIe GTH Quad 219


HP I/O Bank 39 HR I/O Bank 59
X0Y0-X0Y3 X0Y0 X0Y0 X0Y0-X0Y3

X16492-012917

Figure 1-59: XCVU190 Banks in FLGB2104 Package

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X-Ref Target - Figure 1-60

GTY Quad 133 GTH Quad 233


CMAC PCIe
X0Y56-X0Y59 HP I/O Bank 53 HP I/O Bank 73 X0Y56-X0Y59
X0Y8 X0Y5
W [LN] J [RN]
GTY Quad 132 GTH Quad 232
CMAC HP I/O Bank 52 HP I/O Bank 72 ILKN
X0Y52-X0Y55 X0Y52-X0Y55
X0Y7 L I X1Y8
V [LN] I [RN]
GTY Quad 131 GTH Quad 231
ILKN HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y48-X0Y51 X0Y48-X0Y51
X0Y7 K H Configuration
U [LN] H [RN] (RCAL)
GTY Quad 130 GTH Quad 230
CMAC HP I/O Bank 50 HP I/O Bank 70
X0Y44-X0Y47 Configuration X0Y44-X0Y47
X0Y6 J G
T [LN] (RCAL) G [RN]
GTY Quad 129 GTH Quad 229
ILKN PCIe
X0Y40-X0Y43 HP I/O Bank 49 HR I/O Bank 69 X0Y40-X0Y43
X0Y6 X0Y4
S [LN] F [RN]
SLR Crossing
GTY Quad 128 GTH Quad 228
CMAC HP I/O Bank 68 PCIe
X0Y36-X0Y39 HP I/O Bank 48 X0Y36-X0Y39
X0Y5 F X0Y3
R [LC] E [RC]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y32-X0Y35 HP I/O Bank 47 X0Y32-X0Y35
X0Y4 E X1Y5
Q [LC] D [RC]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y28-X0Y31 X0Y28-X0Y31
X0Y4 I D Configuration
P [LC] C [RC] (RCAL)
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 45 HP I/O Bank 65
X0Y24-X0Y27 Configuration X0Y24-X0Y27
X0Y3 H C
O [LC] (RCAL) B [RC]
GTY Quad 124 HR I/O Bank PCIe GTH Quad 224
ILKN HP I/O Bank 44
X0Y20-X0Y23 84/94 X0Y2 X0Y20-X0Y23
X0Y3 G
N [LC] B (tandem) A [RC]
SLR Crossing

GTY Quad 123 CMAC PCIe GTH Quad 223


HP I/O Bank 43 HP I/O Bank 63
X0Y16-X0Y19 X0Y2 X0Y1 X0Y16-X0Y19

GTY Quad 122 GTH Quad 222


CMAC ILKN
X0Y12-X0Y15 HP I/O Bank 42 HP I/O Bank 62 X0Y12-X0Y15
X0Y1 X1Y2
Z [LS] M [RS]
GTY Quad 121 GTH Quad 221
ILKN SYSMON
X0Y8-X0Y11 HP I/O Bank 41 HP I/O Bank 61 X0Y8-X0Y11
X0Y1 Configuration
Y [LS] L [RS] (RCAL)
GTY Quad 120 GTH Quad 220
CMAC
X0Y4-X0Y7 HP I/O Bank 40 HP I/O Bank 60 Configuration X0Y4-X0Y7
X0Y0
X [LS] (RCAL) K [RS]

GTY Quad 119 ILKN PCIe GTH Quad 219


HP I/O Bank 39 HR I/O Bank 59
X0Y0-X0Y3 X0Y0 X0Y0 X0Y0-X0Y3

X16493-012917

Figure 1-60: XCVU190 Banks in FLGC2104 Package

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X-Ref Target - Figure 1-61

GTY Quad 133 GTH Quad 233


CMAC PCIe
X0Y56-X0Y59 HP I/O Bank 53 HP I/O Bank 73 X0Y56-X0Y59
X0Y8 X0Y5
Z [LN] J [RN]
GTY Quad 132 GTH Quad 232
CMAC HP I/O Bank 72 ILKN
X0Y52-X0Y55 HP I/O Bank 52 X0Y52-X0Y55
X0Y7 K X1Y8
Y [LN] I [RN]
GTY Quad 131 GTH Quad 231
ILKN HP I/O Bank 71 SYSMON
X0Y48-X0Y51 HP I/O Bank 51 X0Y48-X0Y51
X0Y7 J Configuration
X [LN] H [RN] (RCAL)
GTY Quad 130 GTH Quad 230
CMAC HP I/O Bank 70
X0Y44-X0Y47 HP I/O Bank 50 Configuration X0Y44-X0Y47
X0Y6 I
W [LUC] (RCAL) G [RUC]
GTY Quad 129 GTH Quad 229
ILKN PCIe
X0Y40-X0Y43 HP I/O Bank 49 HR I/O Bank 69 X0Y40-X0Y43
X0Y6 X0Y4
V [LUC] F [RUC]
SLR Crossing
GTY Quad 128 GTH Quad 228
CMAC HP I/O Bank 68 PCIe
X0Y36-X0Y39 HP I/O Bank 48 X0Y36-X0Y39
X0Y5 H (Partial) X0Y3
U [LUC] E [RUC]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y32-X0Y35 HP I/O Bank 47 X0Y32-X0Y35
X0Y4 G X1Y5
T [LUC] D [RUC]
GTY Quad 126 GTH Quad 226
ILKN HP I/O Bank 66 SYSMON
X0Y28-X0Y31 HP I/O Bank 46 X0Y28-X0Y31
X0Y4 B (Partial) Configuration
S [LLC] C [RLC] (RCAL)
GTY Quad 125 GTH Quad 225
CMAC HP I/O Bank 65
X0Y24-X0Y27 HP I/O Bank 45 Configuration X0Y24-X0Y27
X0Y3 C
R [LLC] (RCAL) B [RLC]
GTY Quad 124 PCIe GTH Quad 224
ILKN HR I/O Bank
X0Y20-X0Y23 HP I/O Bank 44 X0Y2 X0Y20-X0Y23
X0Y3 84/94
Q [LLC] (tandem) A [RLC]
SLR Crossing
GTY Quad 123 GTH Quad 223
CMAC HP I/O Bank 63 PCIe
X0Y16-X0Y19 HP I/O Bank 43 X0Y16-X0Y19
X0Y2 F X0Y1
AF [LLC] P [RLC]
GTY Quad 122 GTH Quad 222
CMAC HP I/O Bank 62 ILKN
X0Y12-X0Y15 HP I/O Bank 42 X0Y12-X0Y15
X0Y1 E X1Y2
AE [LS] O [RS]
GTY Quad 121 GTH Quad 221
ILKN HP I/O Bank 61 SYSMON
X0Y8-X0Y11 HP I/O Bank 41 X0Y8-X0Y11
X0Y1 D Configuration
AD [LS] N [RS] (RCAL)
GTY Quad 120 GTH Quad 220
CMAC
X0Y4-X0Y7 HP I/O Bank 40 HP I/O Bank 60 Configuration X0Y4-X0Y7
X0Y0
AC [LS] (RCAL) M [RS]
GTY Quad 119 GTH Quad 219
ILKN PCIe
X0Y0-X0Y3 HP I/O Bank 39 HR I/O Bank 59 X0Y0-X0Y3
X0Y0 X0Y0
AB [LS] L [RS]
X16494-012917

Figure 1-61: XCVU190 Banks in FLGA2577 Package

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XCVU440 Bank Diagrams


X-Ref Target - Figure 1-62

PCIe GTH Quad 233


HP I/O Bank 53 HP I/O Bank 73
X0Y5 X0Y56-X0Y59

CMAC GTH Quad 232


HP I/O Bank 52 HP I/O Bank 72
X0Y2 X0Y52-X0Y55

GTH Quad 231


SYSMON
HP I/O Bank 51 HP I/O Bank 71 X0Y48-X0Y51
Configuration
(RCAL)

GTH Quad 230


HP I/O Bank 50 HP I/O Bank 70 Configuration
X0Y44-X0Y47

PCIe GTH Quad 229


HP I/O Bank 49 HR I/O Bank 69
X0Y4 X0Y40-X0Y43

SLR Crossing

PCIe GTH Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y3 X0Y36-X0Y39

CMAC GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y1 X0Y32-X0Y35

GTH Quad 226


SYSMON
HP I/O Bank 46 HP I/O Bank 66 X0Y28-X0Y31
Configuration
(RCAL)

GTH Quad 225


HP I/O Bank 45 HP I/O Bank 65 Configuration
X0Y24-X0Y27

PCIe
HR I/O Bank GTH Quad 224
HP I/O Bank 44 X0Y2
84/94 X0Y20-X0Y23
(tandem)
SLR Crossing

PCIe GTH Quad 223


HP I/O Bank 43 HP I/O Bank 63
X0Y1 X0Y16-X0Y19

CMAC GTH Quad 222


HP I/O Bank 42 HP I/O Bank 62
X0Y0 X0Y12-X0Y15

GTH Quad 221


SYSMON
HP I/O Bank 41 HP I/O Bank 61 X0Y8-X0Y11
Configuration
(RCAL)

GTH Quad 220


HP I/O Bank 40 HP I/O Bank 60 Configuration
X0Y4-X0Y7

PCIe GTH Quad 219


HP I/O Bank 39 HR I/O Bank 59
X0Y0 X0Y0-X0Y3
X16497-012917

Figure 1-62: XCVU440 Banks

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X-Ref Target - Figure 1-63

GTH Quad 233


HP I/O Bank 53 HP I/O Bank 73 PCIe
X0Y56-X0Y59
V Z X0Y5
F [RN]
GTH Quad 232
HP I/O Bank 52 HP I/O Bank 72 CMAC
X0Y52-X0Y55
U Y X0Y2
E [RN]
GTH Quad 231
HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y48-X0Y51
T X Configuration
D [RN] (RCAL)

HP I/O Bank 50 HP I/O Bank 70 GTH Quad 230


Configuration
S W X0Y44-X0Y47

PCIe GTH Quad 229


HP I/O Bank 49 HR I/O Bank 69
X0Y4 X0Y40-X0Y43

SLR Crossing

HP I/O Bank 48 HP I/O Bank 68 PCIe GTH Quad 228


R F X0Y3 X0Y36-X0Y39

HP I/O Bank 47 HP I/O Bank 67 CMAC GTH Quad 227


Q E X0Y1 X0Y32-X0Y35

GTH Quad 226


HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y28-X0Y31
P D Configuration
C [RC] (RCAL)
GTH Quad 225
HP I/O Bank 45 HP I/O Bank 65
Configuration X0Y24-X0Y27
O C
B [RC]
HR I/O Bank PCIe GTH Quad 224
HP I/O Bank 44 84/94 X0Y2 X0Y20-X0Y23
B (tandem) A [RC]
SLR Crossing
GTH Quad 223
HP I/O Bank 43 HP I/O Bank 63 PCIe
X0Y16-X0Y19
N J X0Y1
I [RS]
GTH Quad 222
HP I/O Bank 42 HP I/O Bank 62 CMAC
X0Y12-X0Y15
M I X0Y0
H [RS]
GTH Quad 221
HP I/O Bank 41 HP I/O Bank 61 SYSMON
X0Y8-X0Y11
L H Configuration
G [RS] (RCAL)

HP I/O Bank 40 HP I/O Bank 60 GTH Quad 220


Configuration
K G X0Y4-X0Y7

PCIe GTH Quad 219


HP I/O Bank 39 HR I/O Bank 59
X0Y0 X0Y0-X0Y3
X16498-012917

Figure 1-63: XCVU440 Banks in FLGB2377 Package

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X-Ref Target - Figure 1-64

HP I/O Bank 53 HP I/O Bank 73 PCIe GTH Quad 233


Y AC X0Y5 X0Y56-X0Y59

GTH Quad 232


HP I/O Bank 52 HP I/O Bank 72 CMAC
X0Y52-X0Y55
X AB X0Y2
H [RN]
GTH Quad 231
HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y48-X0Y51
W AA Configuration
G [RN] (RCAL)
GTH Quad 230
HP I/O Bank 50 HP I/O Bank 70
Configuration X0Y44-X0Y47
V Z
F [RN]
GTH Quad 229
HP I/O Bank 49 PCIe
HR I/O Bank 69 X0Y40-X0Y43
U X0Y4
E [RN]
SLR Crossing

HP I/O Bank 48 HP I/O Bank 68 PCIe GTH Quad 228


T F X0Y3 X0Y36-X0Y39

GTH Quad 227


HP I/O Bank 47 HP I/O Bank 67 CMAC
X0Y32-X0Y35
S E X0Y1
D [RC]
GTH Quad 226
HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y28-X0Y31
R D Configuration
C [RC] (RCAL)
GTH Quad 225
HP I/O Bank 45 HP I/O Bank 65
Configuration X0Y24-X0Y27
Q C
B [RC]
HR I/O Bank PCIe GTH Quad 224
HP I/O Bank 44
84/94 X0Y2 X0Y20-X0Y23
P
B (tandem) A [RC]
SLR Crossing

HP I/O Bank 43 HP I/O Bank 63 PCIe GTH Quad 223


O J X0Y1 X0Y16-X0Y19

GTH Quad 222


HP I/O Bank 42 HP I/O Bank 62 CMAC
X0Y12-X0Y15
N I X0Y0
L [RS]
GTH Quad 221
HP I/O Bank 41 HP I/O Bank 61 SYSMON
X0Y8-X0Y11
M H Configuration
K [RS] (RCAL)
GTH Quad 220
HP I/O Bank 40 HP I/O Bank 60
Configuration X0Y4-X0Y7
L G
J [RS]
GTH Quad 219
HP I/O Bank 39 PCIe
HR I/O Bank 59 X0Y0-X0Y3
K X0Y0
I [RS]
X16496-012917

Figure 1-64: XCVU440 Banks in FLGA2892 Package

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XCAU7P and XAAU7P Bank Diagrams


X-Ref Target - Figure 1-65

SYSMON
HP I/O Bank 66 HD I/O Bank 86 HD I/O Bank 106
Configuration

HP I/O Bank 65 Configuration HD I/O Bank 85 HD I/O Bank 105

GTH Quad 124 PCIE4C


X0Y0-X0Y3 X0Y0 HD I/O Bank 84 HD I/O Bank 104
(RCAL) (tandem)

X27962-050223

Figure 1-65: XCAU7P and XAAU7P Banks


\
X-Ref Target - Figure 1-66

SYSMON HD I/O Bank 86 HD I/O Bank 106


HP I/O Bank 66
D Configuration G J

HP I/O Bank 65 Configuration HD I/O Bank 85 HD I/O Bank 105


C F I
GTH Quad 124 PCIE4C
X0Y0-X0Y3 X0Y0 HD I/O Bank 84 HD I/O Bank 104
E H
(RCAL) (tandem)

X27964-050223

Figure 1-66: XCAU7P and XAAU7P Banks in SBVC484 Package

XCAU10P and XAAU10P Bank Diagrams


X-Ref Target - Figure 1-67

SYSMON GTH Quad 226


HP I/O Bank 66 HD I/O Bank 86
Configuration X0Y8-X0Y11

GTH Quad 225


HP I/O Bank 65 HD I/O Bank 85 Configuration
X0Y4-X0Y7

PCIE4C GTH Quad 224


HP I/O Bank 64 HD I/O Bank 84 X0Y0 X0Y0-X0Y3
(tandem) (RCAL)
X26542-041222

Figure 1-67: XCAU10P Banks

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X-Ref Target - Figure 1-68

HP I/O Bank 66 SYSMON GTH Quad 226


HD I/O Bank 86
D Configuration X0Y8-X0Y11

GTH Quad 225


HP I/O Bank 65
HD I/O Bank 85 Configuration X0Y4-X0Y7
C
B [R]
PCIE4C GTH Quad 224
HD I/O Bank 84
HP I/O Bank 64 X0Y0 X0Y0-X0Y3
A
(tandem) A [R] (RCAL)
X26545-041222

Figure 1-68: XCAU10P Banks in UBVA368 Package


X-Ref Target - Figure 1-69

GTH Quad 226


HP I/O Bank 66 SYSMON
HD I/O Bank 86 X0Y8-X0Y11
D Configuration
C [R]
GTH Quad 225
HP I/O Bank 65 HD I/O Bank 85
Configuration X0Y4-X0Y7
C F
B [R]
PCIE4C GTH Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
B E
(tandem) A [R] (RCAL)
X26543-041222

Figure 1-69: XCAU10P and XAAU10P Banks in SBVB484 Package


X-Ref Target - Figure 1-70

GTH Quad 226


HP I/O Bank 66 HD I/O Bank 86 SYSMON
X0Y8-X0Y11
D G Configuration
C [R]
GTH Quad 225
HP I/O Bank 65 HD I/O Bank 85
Configuration X0Y4-X0Y7
C F
B [R]
PCIE4C GTH Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
B A
(tandem) A [R] (RCAL)
X26544-041222

Figure 1-70: XCAU10P and XAAU10P Banks in FFVB676 Package

XCAU15P and XAAU15P Bank Diagrams


X-Ref Target - Figure 1-71

SYSMON GTH Quad 226


HP I/O Bank 66 HD I/O Bank 86
Configuration X0Y8-X0Y11

GTH Quad 225


HP I/O Bank 65 HD I/O Bank 85 Configuration
X0Y4-X0Y7

PCIE4C GTH Quad 224


HP I/O Bank 64 HD I/O Bank 84 X0Y0 X0Y0-X0Y3
(tandem) (RCAL)
X26538-041222

Figure 1-71: XCAU15P and XAAU15P Banks

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X-Ref Target - Figure 1-72

HP I/O Bank 66 SYSMON GTH Quad 226


HD I/O Bank 86
D Configuration X0Y8-X0Y11

GTH Quad 225


HP I/O Bank 65
HD I/O Bank 85 Configuration X0Y4-X0Y7
C
B [R]
PCIE4C GTH Quad 224
HD I/O Bank 84
HP I/O Bank 64 X0Y0 X0Y0-X0Y3
A
(tandem) A [R] (RCAL)
X26541-041222

Figure 1-72: XCAU15P Banks in UBVA368 Package


X-Ref Target - Figure 1-73

GTH Quad 226


HP I/O Bank 66 SYSMON
HD I/O Bank 86 X0Y8-X0Y11
D Configuration
C [R]
GTH Quad 225
HP I/O Bank 65 HD I/O Bank 85
Configuration X0Y4-X0Y7
C F
B [R]
PCIE4C GTH Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
B E
(tandem) A [R] (RCAL)
X26539-041222

Figure 1-73: XCAU15P and XAAU15P Banks in SBVB484 Package


X-Ref Target - Figure 1-74

GTH Quad 226


HP I/O Bank 66 HD I/O Bank 86 SYSMON
X0Y8-X0Y11
D G Configuration
C [R]
GTH Quad 225
HP I/O Bank 65 HD I/O Bank 85
Configuration X0Y4-X0Y7
C F
B [R]
PCIE4C GTH Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
B A
(tandem) A [R] (RCAL)
X26540-041222

Figure 1-74: XCAU15P and XAAU15P Banks in FFVB676 Package

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XCAU20P Bank Diagrams


X-Ref Target - Figure 1-75

HP I/O Bank 67 HD I/O Bank 87

SYSMON GTY Quad 226


HP I/O Bank 66 HD I/O Bank 86
Configuration X0Y8-X0Y11

GTY Quad 225


HP I/O Bank 65 HD I/O Bank 85 Configuration X0Y4-X0Y7
(RCAL)
PCIE4
GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84 X0Y0
X0Y0-X0Y3
(tandem)
X25582-081921

Figure 1-75: XCAU20P Banks


X-Ref Target - Figure 1-76

HD I/O Bank 87
HP I/O Bank 67
G

GTY Quad 226


HP I/O Bank 66 HD I/O Bank 86 SYSMON
X0Y8-X0Y11
D F Configuration
C [R]
GTY Quad 225
HP I/O Bank 65
HD I/O Bank 85 Configuration X0Y4-X0Y7
C
B [R] (RCAL)
PCIE4 GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
B A
(tandem) A [R]
X25584-041222

Figure 1-76: XCAU20P Banks in FFVB676 Package

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X-Ref Target - Figure 1-77

HP I/O Bank 67 HD I/O Bank 87

GTY Quad 226


HP I/O Bank 66 HD I/O Bank 86 SYSMON
X0Y8-X0Y11
D G Configuration
C [R]
GTY Quad 225
HP I/O Bank 65 HD I/O Bank 85
Configuration X0Y4-X0Y7
C I
B [R] (RCAL)
PCIE4 GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
B H
(tandem) A [R]
X25583-081921

Figure 1-77: XCAU20P Banks in SFVB784 Package

XCAU25P Bank Diagrams


X-Ref Target - Figure 1-78

HP I/O Bank 67 HD I/O Bank 87

SYSMON GTY Quad 226


HP I/O Bank 66 HD I/O Bank 86
Configuration X0Y8-X0Y11

GTY Quad 225


HP I/O Bank 65 HD I/O Bank 85 Configuration X0Y4-X0Y7
(RCAL)
PCIE4
GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84 X0Y0
X0Y0-X0Y3
(tandem)
X25579-072021

Figure 1-78: XCAU25P Banks

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X-Ref Target - Figure 1-79

HP I/O Bank 67 HD I/O Bank 87


E G

GTY Quad 226


HP I/O Bank 66 HD I/O Bank 86 SYSMON
X0Y8-X0Y11
D F Configuration
C [R]
GTY Quad 225
HP I/O Bank 65
HD I/O Bank 85 Configuration X0Y4-X0Y7
C
B [R] (RCAL)
PCIE4 GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
B A
(tandem) A [R]
X25580-072021

Figure 1-79: XCAU25P Banks in FFVB676 Package


X-Ref Target - Figure 1-80

HP I/O Bank 67 HD I/O Bank 87


E F

GTY Quad 226


HP I/O Bank 66 HD I/O Bank 86 SYSMON
X0Y8-X0Y11
D G Configuration
C [R]
HP I/O Bank 65 GTY Quad 225
HD I/O Bank 85 Configuration
C X0Y4-X0Y7
I PCIE4
B [R] (RCAL)
HP I/O Bank 64 GTY Quad 224
HD I/O Bank 84 X0Y0
B X0Y0-X0Y3
H (tandem)
A [R]
X25581-072021

Figure 1-80: XCAU25P Banks in SFVB784 Package

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XCKU3P Bank Diagrams


X-Ref Target - Figure 1-81

CMAC GTY Quad 227


HP I/O Bank 67 HD I/O Bank 87
X0Y0 X0Y12-X0Y15

SYSMON GTY Quad 226


HP I/O Bank 66 HD I/O Bank 86
Configuration X0Y8-X0Y11

GTY Quad 225


HP I/O Bank 65 HD I/O Bank 85 Configuration X0Y4-X0Y7
(RCAL)
PCIE4
GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84 X0Y0
X0Y0-X0Y3
(tandem)
X15536-020817

Figure 1-81: XCKU3P Banks


X-Ref Target - Figure 1-82

GTY Quad 227


HP I/O Bank 67 CMAC
HD I/O Bank 87 X0Y12-X0Y15
G X0Y0
D [R]
GTY Quad 226
HP I/O Bank 66 SYSMON
HD I/O Bank 86 X0Y8-X0Y11
D Configuration
C [R]
GTY Quad 225
HP I/O Bank 65 HD I/O Bank 85
Configuration X0Y4-X0Y7
C R
B [R] (RCAL)
PCIE4 GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
E R
(tandem) A [R]
X15538-020817

Figure 1-82: XCKU3P Banks in FFVA676 Package


X-Ref Target - Figure 1-83

GTY Quad 227


HP I/O Bank 67 HD I/O Bank 87 CMAC
X0Y12-X0Y15
E G X0Y0
D [R]
GTY Quad 226
HP I/O Bank 66 HD I/O Bank 86 SYSMON
X0Y8-X0Y11
D F Configuration
C [R]
GTY Quad 225
HP I/O Bank 65
HD I/O Bank 85 Configuration X0Y4-X0Y7
C
B [R] (RCAL)
PCIE4 GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
B A
(tandem) A [R]
X16502-020817

Figure 1-83: XCKU3P Banks in FFVB676 Package

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X-Ref Target - Figure 1-84

GTY Quad 227


HP I/O Bank 67 HD I/O Bank 87 CMAC
X0Y12-X0Y15
E F X0Y0
D [R]
GTY Quad 226
HP I/O Bank 66 HD I/O Bank 86 SYSMON
X0Y8-X0Y11
D G Configuration
C [R]
GTY Quad 225
HP I/O Bank 65 HD I/O Bank 85
Configuration X0Y4-X0Y7
C I
B [R] (RCAL)
PCIE4 GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
B H
(tandem) A [R]
X15537-020817

Figure 1-84: XCKU3P Banks in SFVB784 Package


X-Ref Target - Figure 1-85

GTY Quad 227


HP I/O Bank 67 HD I/O Bank 87 CMAC
X0Y12-X0Y15
F K X0Y0
D [R]
GTY Quad 226
HP I/O Bank 66 HD I/O Bank 86 SYSMON
X0Y8-X0Y11
D L Configuration
C [R]
GTY Quad 225
HP I/O Bank 65 HD I/O Bank 85
Configuration X0Y4-X0Y7
C J
B [R] (RCAL)
PCIE4 GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
E I
(tandem) A [R]
X16503-020817

Figure 1-85: XCKU3P Banks in FFVD900 Package

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XCKU5P and XQKU5P Bank Diagrams


X-Ref Target - Figure 1-86

CMAC GTY Quad 227


HP I/O Bank 67 HD I/O Bank 87
X0Y0 X0Y12-X0Y15

SYSMON GTY Quad 226


HP I/O Bank 66 HD I/O Bank 86
Configuration X0Y8-X0Y11

GTY Quad 225


HP I/O Bank 65 HD I/O Bank 85 Configuration X0Y4-X0Y7
(RCAL)
PCIE4
GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84 X0Y0
X0Y0-X0Y3
(tandem)
X15539-020817

Figure 1-86: XCKU5P and XQKU5P Banks


X-Ref Target - Figure 1-87

GTY Quad 227


HP I/O Bank 67 CMAC
HD I/O Bank 87 X0Y12-X0Y15
G X0Y0
D [R]
GTY Quad 226
HP I/O Bank 66 SYSMON
HD I/O Bank 86 X0Y8-X0Y11
D Configuration
C [R]
GTY Quad 225
HP I/O Bank 65 HD I/O Bank 85
Configuration X0Y4-X0Y7
C R
B [R] (RCAL)
PCIE4 GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
E R
(tandem) A [R]
X15588-020817

Figure 1-87: XCKU5P Banks in FFVA676 Package


X-Ref Target - Figure 1-88

GTY Quad 227


HP I/O Bank 67 HD I/O Bank 87 CMAC
X0Y12-X0Y15
E G X0Y0
D [R]
GTY Quad 226
HP I/O Bank 66 HD I/O Bank 86 SYSMON
X0Y8-X0Y11
D F Configuration
C [R]
GTY Quad 225
HP I/O Bank 65
HD I/O Bank 85 Configuration X0Y4-X0Y7
C
B [R] (RCAL)
PCIE4 GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
B A
(tandem) A [R]
X15586-020817

Figure 1-88: XCKU5P Banks in FFVB676 Package and XQKU5P Banks in FFRB676 Package

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X-Ref Target - Figure 1-89

GTY Quad 227


HP I/O Bank 67 HD I/O Bank 87 CMAC
X0Y12-X0Y15
E F X0Y0
D [R]
GTY Quad 226
HP I/O Bank 66 HD I/O Bank 86 SYSMON
X0Y8-X0Y11
D G Configuration
C [R]
GTY Quad 225
HP I/O Bank 65 HD I/O Bank 85
Configuration X0Y4-X0Y7
C I
B [R] (RCAL)
PCIE4 GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
B H
(tandem) A [R]
X15587-020817

Figure 1-89: XCKU5P Banks in SFVB784 Package and XQKU5P Banks in SFRB784 Package
X-Ref Target - Figure 1-90

GTY Quad 227


HP I/O Bank 67 HD I/O Bank 87 CMAC
X0Y12-X0Y15
F K X0Y0
D [R]
GTY Quad 226
HP I/O Bank 66 HD I/O Bank 86 SYSMON
X0Y8-X0Y11
D L Configuration
C [R]
GTY Quad 225
HP I/O Bank 65 HD I/O Bank 85
Configuration X0Y4-X0Y7
C J
B [R] (RCAL)
PCIE4 GTY Quad 224
HP I/O Bank 64 HD I/O Bank 84
X0Y0 X0Y0-X0Y3
E I
(tandem) A [R]
X15589-020817

Figure 1-90: XCKU5P Banks in FFVD900 Package

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XCKU9P Bank Diagrams


X-Ref Target - Figure 1-91

GTH Quad 130 GTH Quad 230


HD I/O Bank 50
X0Y12-X0Y15 X1Y12-X1Y15

GTH Quad 129 GTH Quad 229


HD I/O Bank 49
X0Y8-X0Y11 X1Y8-X1Y11

GTH Quad 128 GTH Quad 228


X0Y4-X0Y7 HD I/O Bank 48 X1Y4-X1Y7
(RCAL) (RCAL)

GTH Quad 127


HD I/O Bank47 HP I/O Bank 67
X0Y0-X0Y3

SYSMON
HP I/O Bank 66
Configuration

Configuration HP I/O Bank 65

HD I/O Bank 44 HP I/O Bank 64

X15591-062217

Figure 1-91: XCKU9P Banks

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X-Ref Target - Figure 1-92

GTH Quad 130 GTH Quad 230


X0Y12-X0Y15 HD I/O Bank 50 X1Y12-X1Y15
G [L] C [R]
GTH Quad 129 GTH Quad 229
HD I/O Bank 49
X0Y8-X0Y11 X1Y8-X1Y11
O
F [L] B [R]
GTH Quad 128 GTH Quad 228
HD I/O Bank 48
X0Y4-X0Y7 X1Y4-X1Y7
N
E [L] (RCAL) A [R] (RCAL)
GTH Quad 127
HD I/O Bank47 HP I/O Bank 67
X0Y0-X0Y3
G E
D [L]

SYSMON HP I/O Bank 66


Configuration D

HP I/O Bank 65
Configuration
C

HD I/O Bank 44 HP I/O Bank 64


F B

X15592-062217

Figure 1-92: XCKU9P Banks in FFVE900 Package

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XCKU11P Bank Diagrams


X-Ref Target - Figure 1-93

GTY Quad 131 PCIE4 GTH Quad 231


HP I/O Bank 71 HD I/O Bank 91
X0Y16-X0Y19 X0Y3 X0Y28-X0Y31

GTY Quad 130 CMAC GTH Quad 230


HP I/O Bank 70 HD I/O Bank 90
X0Y12-X0Y15 X0Y1 X0Y24-X0Y27

GTY Quad 129


ILKN GTH Quad 229
X0Y8-X0Y11 HP I/O Bank 69 HD I/O Bank 89
X0Y0 X0Y20-X0Y23
(RCAL)

GTY Quad 128 PCIE4 GTH Quad 228


HP I/O Bank 68 HD I/O Bank 88
X0Y4-X0Y7 X0Y2 X0Y16-X0Y19

GTY Quad 127 CMAC PCIE4 GTH Quad 227


HP I/O Bank 67
X0Y0-X0Y3 X0Y0 X1Y1 X0Y12-X0Y15

GTH Quad 226


SYSMON
HP I/O Bank 66 X0Y8-X0Y11
Configuration
(RCAL)

GTH Quad 225


HP I/O Bank 65 Configuration
X0Y4-X0Y7

PCIE4
GTH Quad 224
HP I/O Bank 64 X1Y0
X0Y0-X0Y3
(tandem)
X15593-020817

Figure 1-93: XCKU11P Banks

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X-Ref Target - Figure 1-94

GTY Quad 131 PCIE4 HD I/O Bank 91 GTH Quad 231


HP I/O Bank 71
X0Y16-X0Y19 X0Y3 K X0Y28-X0Y31

GTY Quad 130 CMAC HP I/O Bank 70 HD I/O Bank 90 GTH Quad 230
X0Y12-X0Y15 X0Y1 H L X0Y24-X0Y27

GTY Quad 129


ILKN HP I/O Bank 69 HD I/O Bank 89 GTH Quad 229
X0Y8-X0Y11
X0Y0 G J X0Y20-X0Y23
(RCAL)

GTY Quad 128 PCIE4 HP I/O Bank 68 HD I/O Bank 88 GTH Quad 228
X0Y4-X0Y7 X0Y2 F I X0Y16-X0Y19

GTH Quad 227


GTY Quad 127 CMAC HP I/O Bank 67 PCIE4
X0Y12-X0Y15
X0Y0-X0Y3 X0Y0 E X1Y1
D [R]
GTH Quad 226
HP I/O Bank 66 SYSMON
X0Y8-X0Y11
D Configuration
C [R] (RCAL)
GTH Quad 225
HP I/O Bank 65
Configuration X0Y4-X0Y7
C
B [R]
PCIE4 GTH Quad 224
HP I/O Bank 64 X1Y0 X0Y0-X0Y3
(tandem) A [R]
X15594-020817

Figure 1-94: XCKU11P Banks in FFVD900 Package

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X-Ref Target - Figure 1-95

GTY Quad 131 PCIE4 HP I/O Bank 71 GTH Quad 231


HD I/O Bank 91
X0Y16-X0Y19 X0Y3 F X0Y28-X0Y31

GTY Quad 130


CMAC HP I/O Bank 70 GTH Quad 230
X0Y12-X0Y15 HD I/O Bank 90
X0Y1 E X0Y24-X0Y27
G[L]
GTY Quad 129
ILKN HP I/O Bank 69 HD I/O Bank 89 GTH Quad 229
X0Y8-X0Y11
X0Y0 K R X0Y20-X0Y23
F [L] (RCAL)
GTH Quad 228
GTY Quad 128 PCIE4 HP I/O Bank 68 HD I/O Bank 88
X0Y16-X0Y19
X0Y4-X0Y7 X0Y2 J R
E [R]
GTH Quad 227
GTY Quad 127 CMAC HP I/O Bank 67 PCIE4
X0Y12-X0Y15
X0Y0-X0Y3 X0Y0 G X1Y1
D [R]
GTH Quad 226
HP I/O Bank 66 SYSMON
X0Y8-X0Y11
D Configuration
C [R] (RCAL)
GTH Quad 225
HP I/O Bank 65
Configuration X0Y4-X0Y7
C
B [R]
PCIE4 GTH Quad 224
HP I/O Bank 64
X1Y0 X0Y0-X0Y3
H
(tandem) A [R]
X15595-062217

Figure 1-95: XCKU11P Banks in FFVA1156 Package

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X-Ref Target - Figure 1-96

GTY Quad 131 GTH Quad 231


PCIE4 HP I/O Bank 71 HD I/O Bank 91
X0Y16-X0Y19 X0Y28-X0Y31
X0Y3 R N
M [L] H [RN]
GTY Quad 130 GTH Quad 230
CMAC HP I/O Bank 70 HD I/O Bank 90
X0Y12-X0Y15 X0Y24-X0Y27
X0Y1 S O
L [L] G [RN]
GTY Quad 129 GTH Quad 229
ILKN HP I/O Bank 69 HD I/O Bank 89
X0Y8-X0Y11 X0Y20-X0Y23
X0Y0 T P
K [L] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
PCIE4 HP I/O Bank 68 HD I/O Bank 88
X0Y4-X0Y7 X0Y16-X0Y19
X0Y2 G Q
J [L] E [RN]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 PCIE4
X0Y0-X0Y3 X0Y12-X0Y15
X0Y0 F X1Y1
I [L] D [RS]
GTH Quad 226
HP I/O Bank 66 SYSMON
X0Y8-X0Y11
E Configuration
C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 65
Configuration X0Y4-X0Y7
C
B [RS]
PCIE4 GTH Quad 224
HP I/O Bank 64
X1Y0 X0Y0-X0Y3
D
(tandem) A [RS]
X15597-020817

Figure 1-96: XCKU11P Banks in FFVE1517 Package

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XCKU13P Bank Diagrams


X-Ref Target - Figure 1-97

GTH Quad 130 GTH Quad 230


HD I/O Bank 50
X0Y12-X0Y15 X1Y12-X1Y15

GTH Quad 129 GTH Quad 229


HD I/O Bank 49
X0Y8-X0Y11 X1Y8-X1Y11

GTH Quad 128 GTH Quad 228


X0Y4-X0Y7 HD I/O Bank 48 X1Y4-X1Y7
(RCAL) (RCAL)

GTH Quad 127


HD I/O Bank47 HP I/O Bank 67
X0Y0-X0Y3

SYSMON
HP I/O Bank 66
Configuration

Configuration HP I/O Bank 65

HD I/O Bank 44 HP I/O Bank 64

X15598-062217

Figure 1-97: XCKU13P Banks

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X-Ref Target - Figure 1-98

GTH Quad 130 GTH Quad 230


X0Y12-X0Y15 HD I/O Bank 50 X1Y12-X1Y15
G [L] C [R]
GTH Quad 129 GTH Quad 229
HD I/O Bank 49
X0Y8-X0Y11 X1Y8-X1Y11
O
F [L] B [R]
GTH Quad 128 GTH Quad 228
HD I/O Bank 48
X0Y4-X0Y7 X1Y4-X1Y7
N
E [L] (RCAL) A [R] (RCAL)
GTH Quad 127
HD I/O Bank47 HP I/O Bank 67
X0Y0-X0Y3
G E
D [L]

SYSMON HP I/O Bank 66


Configuration D

HP I/O Bank 65
Configuration
C

HD I/O Bank 44 HP I/O Bank 64


F B

X15599-062217

Figure 1-98: XCKU13P Banks in FFVE900 Package

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XCKU15P and XQKU15P Bank Diagrams


X-Ref Target - Figure 1-99

GTY Quad 134 CMAC GTH Quad 234


HP I/O Bank 74 HD I/O Bank 94
X0Y28-X0Y31 X0Y3 X0Y40-X0Y43

GTY Quad 133 ILKN GTH Quad 233


HP I/O Bank 73 HD I/O Bank 93
X0Y24-X0Y27 X0Y2 X0Y36-X0Y39

GTY Quad 132 CMAC ILKN GTH Quad 232


HP I/O Bank 72
X0Y20-X0Y23 X0Y2 X1Y1 X0Y32-X0Y35

GTY Quad 131 PCIE4 GTH Quad 231


HP I/O Bank 71 HD I/O Bank 91
X0Y16-X0Y19 X0Y3 X0Y28-X0Y31

GTY Quad 130 CMAC GTH Quad 230


HP I/O Bank 70 HD I/O Bank 90
X0Y12-X0Y15 X0Y1 X0Y24-X0Y27

GTY Quad 129


ILKN ILKN GTH Quad 229
X0Y8-X0Y11 HP I/O Bank 69
X0Y0 X1Y0 X0Y20-X0Y23
(RCAL)

GTY Quad 128 PCIE4 PCIE4 GTH Quad 228


HP I/O Bank 68
X0Y4-X0Y7 X0Y2 X1Y2 X0Y16-X0Y19

GTY Quad 127 CMAC PCIE4 GTH Quad 227


HP I/O Bank 67
X0Y0-X0Y3 X0Y0 X1Y1 X0Y12-X0Y15

GTH Quad 226


SYSMON
HP I/O Bank 66 X0Y8-X0Y11
Configuration
(RCAL)

GTH Quad 225


HP I/O Bank 65 Configuration
X0Y4-X0Y7

PCIE4
GTH Quad 224
HP I/O Bank 64 X1Y0
X0Y0-X0Y3
(tandem)
X15600-062217

Figure 1-99: XCKU15P and XQKU15P Banks

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X-Ref Target - Figure 1-100

GTY Quad 134 CMAC GTH Quad 234


HP I/O Bank 74 HD I/O Bank 94
X0Y28-X0Y31 X0Y3 X0Y40-X0Y43

GTY Quad 133 ILKN GTH Quad 233


HP I/O Bank 73 HD I/O Bank 93
X0Y24-X0Y27 X0Y2 X0Y36-X0Y39

GTY Quad 132 CMAC HP I/O Bank 72 ILKN GTH Quad 232
X0Y20-X0Y23 X0Y2 F X1Y1 X0Y32-X0Y35

GTY Quad 131 PCIE4 HP I/O Bank 71 HD I/O Bank 91 GTH Quad 231
X0Y16-X0Y19 X0Y3 E R X0Y28-X0Y31

GTY Quad 130


CMAC HP I/O Bank 70 HD I/O Bank 90 GTH Quad 230
X0Y12-X0Y15
X0Y1 K R X0Y24-X0Y27
G[L]
GTY Quad 129
ILKN HP I/O Bank 69 ILKN GTH Quad 229
X0Y8-X0Y11
X0Y0 J X1Y0 X0Y20-X0Y23
F[L] (RCAL)
GTH Quad 228
GTY Quad 128 PCIE4 HP I/O Bank 68 PCIE4
X0Y16-X0Y19
X0Y4-X0Y7 X0Y2 I X1Y2
E [R]
GTH Quad 227
GTY Quad 127 CMAC HP I/O Bank 67 PCIE4
X0Y12-X0Y15
X0Y0-X0Y3 X0Y0 G X1Y1
D [R]
GTH Quad 226
HP I/O Bank 66 SYSMON
X0Y8-X0Y11
D Configuration
C [R] (RCAL)
GTH Quad 225
HP I/O Bank 65
Configuration X0Y4-X0Y7
C
B [R]
PCIE4 GTH Quad 224
HP I/O Bank 64
X1Y0 X0Y0-X0Y3
H
(tandem) A [R]
X15601-062217

Figure 1-100: XCKU15P Banks in FFVA1156 Package and XQKU15P in FFRA1156 Package

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X-Ref Target - Figure 1-101

GTY Quad 134 CMAC HD I/O Bank 94 GTH Quad 234


HP I/O Bank 74
X0Y28-X0Y31 X0Y3 N X0Y40-X0Y43

GTY Quad 133 ILKN HD I/O Bank 93 GTH Quad 233


HP I/O Bank 73
X0Y24-X0Y27 X0Y2 O X0Y36-X0Y39

GTY Quad 132


CMAC ILKN GTH Quad 232
X0Y20-X0Y23 HP I/O Bank 72
X0Y2 X1Y1 X0Y32-X0Y35
N [L]
GTY Quad 131 GTH Quad 231
PCIE4 HP I/O Bank 71 HD I/O Bank 91
X0Y16-X0Y19 X0Y28-X0Y31
X0Y3 R P
M [L] H [RN]
GTY Quad 130 GTH Quad 230
CMAC HP I/O Bank 70 HD I/O Bank 90
X0Y12-X0Y15 X0Y24-X0Y27
X0Y1 S Q
L [L] G [RN]
GTY Quad 129 GTH Quad 229
ILKN HP I/O Bank 69 ILKN
X0Y8-X0Y11 X0Y20-X0Y23
X0Y0 T X1Y0
K [L] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
PCIE4 HP I/O Bank 68 PCIE4
X0Y4-X0Y7 X0Y16-X0Y19
X0Y2 G X1Y2
J [L] E [RN]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 PCIE4
X0Y0-X0Y3 X0Y12-X0Y15
X0Y0 F X1Y1
I [L] D [RS]
GTH Quad 226
HP I/O Bank 66 SYSMON
X0Y8-X0Y11
E Configuration
C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 65
Configuration X0Y4-X0Y7
C
B [RS]
PCIE4 GTH Quad 224
HP I/O Bank 64
X1Y0 X0Y0-X0Y3
D
(tandem) A [RS]
X15602-062217

Figure 1-101: XCKU15P Banks in FFVE1517 Package and XQKU15P Banks in FFRE1517 Package

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X-Ref Target - Figure 1-102

GTY Quad 134 GTH Quad 234


CMAC HD I/O Bank 94
X0Y28-X0Y31 HP I/O Bank 74 X0Y40-X0Y43
X0Y3 N
S [LN] K [RN]
GTY Quad 133 GTH Quad 233
ILKN HD I/O Bank 93
X0Y24-X0Y27 HP I/O Bank 73 X0Y36-X0Y39
X0Y2 O
R [LN] J [RN]
GTY Quad 132 GTH Quad 232
CMAC HP I/O Bank 72 ILKN
X0Y20-X0Y23 X0Y32-X0Y35
X0Y2 R X1Y1
Q [LN] I [RN]
GTY Quad 131 GTH Quad 231
PCIE4 HP I/O Bank 71 HD I/O Bank 91
X0Y16-X0Y19 X0Y28-X0Y31
X0Y3 S P
P [LN] H [RN]
GTY Quad 130 GTH Quad 230
CMAC HP I/O Bank 70 HD I/O Bank 90
X0Y12-X0Y15 X0Y24-X0Y27
X0Y1 T Q
O [LS] G [RN]
GTY Quad 129 GTH Quad 229
ILKN ILKN
X0Y8-X0Y11 HP I/O Bank 69 X0Y20-X0Y23
X0Y0 X1Y0
N [LS] (RCAL) F [RS]
GTY Quad 128 GTH Quad 228
PCIE4 HP I/O Bank 68 PCIE4
X0Y4-X0Y7 X0Y16-X0Y19
X0Y2 G X1Y2
M [LS] E [RS]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 PCIE4
X0Y0-X0Y3 X0Y12-X0Y15
X0Y0 F X1Y1
L [LS] D [RS]
GTH Quad 226
HP I/O Bank 66 SYSMON
X0Y8-X0Y11
E Configuration
C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 65
Configuration X0Y4-X0Y7
C
B [RS]
PCIE4 GTH Quad 224
HP I/O Bank 64
X1Y0 X0Y0-X0Y3
D
(tandem) A [RS]
X15604-062217

Figure 1-102: XCKU15P Banks in FFVA1760 Package

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X-Ref Target - Figure 1-103

GTY Quad 134 CMAC HP I/O Bank 74 HD I/O Bank 94 GTH Quad 234
X0Y28-X0Y31 X0Y3 R N X0Y40-X0Y43

GTY Quad 133 ILKN HP I/O Bank 73 HD I/O Bank 93 GTH Quad 233
X0Y24-X0Y27 X0Y2 S O X0Y36-X0Y39

GTY Quad 132


CMAC HP I/O Bank 72 ILKN GTH Quad 232
X0Y20-X0Y23
X0Y2 T X1Y1 X0Y32-X0Y35
N [L]
GTY Quad 131 GTH Quad 231
PCIE4 HP I/O Bank 71 HD I/O Bank 91
X0Y16-X0Y19 X0Y28-X0Y31
X0Y3 U P
M [L] H [RN]
GTY Quad 130 GTH Quad 230
CMAC HP I/O Bank 70 HD I/O Bank 90
X0Y12-X0Y15 X0Y24-X0Y27
X0Y1 V Q
L [L] G [RN]
GTY Quad 129 GTH Quad 229
ILKN HP I/O Bank 69 ILKN
X0Y8-X0Y11 X0Y20-X0Y23
X0Y0 H X1Y0
K [L] (RCAL) F [RN]
GTY Quad 128 GTH Quad 228
PCIE4 HP I/O Bank 68 PCIE4
X0Y4-X0Y7 X0Y16-X0Y19
X0Y2 G X1Y2
J [L] E [RN]
GTY Quad 127 GTH Quad 227
CMAC HP I/O Bank 67 PCIE4
X0Y0-X0Y3 X0Y12-X0Y15
X0Y0 F X1Y1
I [L] D [RS]
GTH Quad 226
HP I/O Bank 66 SYSMON
X0Y8-X0Y11
E Configuration
C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 65
Configuration X0Y4-X0Y7
C
B [RS]
PCIE4 GTH Quad 224
HP I/O Bank 64
X1Y0 X0Y0-X0Y3
D
(tandem) A [RS]
X15603-062217

Figure 1-103: XCKU15P Banks in FFVE1760 Package

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XCKU19P Bank Diagrams


X-Ref Target - Figure 1-104

CMAC
HP I/O Bank 73
X0Y0

GTY Quad 232


HP I/O Bank 72 HD I/O Bank 92
X0Y28-X0Y31

PCIE4C GTY Quad 231


HP I/O Bank 71
X0Y2 X0Y24-X0Y27

GTY Quad 230


HP I/O Bank 70 HD I/O Bank 90
X0Y20-X0Y23

PCIE4C GTY Quad 229


HP I/O Bank 69
X0Y1 X0Y16-X0Y19

GTY Quad 228


HP I/O Bank 68 HD I/O Bank 88
X0Y12-X0Y15

PCIE4C GTY Quad 227


HP I/O Bank 67
X0Y0 X0Y8-X0Y11

SYSMON GTY Quad 226


HP I/O Bank 66
Configuration X0Y4-X0Y7
GTY Quad 225
HP I/O Bank 65 Configuration X0Y0-X0Y3
(RCAL)

X24987-010821

Figure 1-104: XCKU19P Banks

IMPORTANT: Tandem configuration is not supported for any PCIE4C instance in XCKU19P banks.

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X-Ref Target - Figure 1-105

HP I/O Bank 73 CMAC


U X0Y0
GTY Quad 232
HP I/O Bank 72 HD I/O Bank 92
X0Y28-X0Y31
T P I [RC]
GTY Quad 231
HP I/O Bank 71 PCIE4C
X0Y24-X0Y27
S X0Y2 H [RC]
GTY Quad 230
HP I/O Bank 70 HD I/O Bank 90
X0Y20-X0Y23
R O G [RC]
GTY Quad 229
HP I/O Bank 69 PCIE4C
X0Y16-X0Y19
G X0Y1 F [RC]
GTY Quad 228
HP I/O Bank 68 HD I/O Bank 88
X0Y12-X0Y15
F N E [RC]
GTY Quad 227
HP I/O Bank 67 PCIE4C
X0Y8-X0Y11
E X0Y0 D [RS]
GTY Quad 226
HP I/O Bank 66 SYSMON
X0Y4-X0Y7
D Configuration C [RS]
GTY Quad 225
HP I/O Bank 65
Configuration X0Y0-X0Y3
C B [RS] (RCAL)

X24989-010821

Figure 1-105: XCKU19P Banks in FFVJ1760 Package

IMPORTANT: Tandem configuration is not supported for any PCIE4C instance in XCKU19P banks.

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X-Ref Target - Figure 1-106

HP I/O Bank 73 CMAC


J X0Y0

HP I/O Bank 72 HD I/O Bank 92 GTY Quad 232


X0Y28-X0Y31
K B I [RN]

HP I/O Bank 71 PCIE4C GTY Quad 231


X0Y24-X0Y27
L X0Y2 H [RN]

HP I/O Bank 70 HD I/O Bank 90 GTY Quad 230


X0Y20-X0Y23
O B G [RN]
GTY Quad 229
HP I/O Bank 69 PCIE4C
N X0Y1 X0Y16-X0Y19
F [RN]

HP I/O Bank 68 HD I/O Bank 88 GTY Quad 228


X0Y12-X0Y15
M F D [RS]

HP I/O Bank 67 PCIE4C GTY Quad 227


X0Y8-X0Y11
E X0Y0 C [RS]

HP I/O Bank 66 SYSMON GTY Quad 226


X0Y4-X0Y7
D Configuration B [RS]

HP I/O Bank 65 GTY Quad 225


Configuration X0Y0-X0Y3
C A [RS] (RCAL)

X24988-031822

Figure 1-106: XCKU19P Banks in FFVB2104 Package

IMPORTANT: Tandem configuration is not supported for any PCIE4C instance in XCKU19P banks.

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XCVU3P and XQVU3P Bank Diagrams


X-Ref Target - Figure 1-107

GTY Quad 128 CMAC ILKN GTY Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y16-X0Y19 X0Y2 X1Y2 X1Y16-X1Y19

GTY Quad 127 PCIE4 ILKN GTY Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y12-X0Y15 X0Y1 X1Y1 X1Y12-X1Y15

GTY Quad 126 GTY Quad 226


CMAC SYSMON
X0Y8-X0Y11 HP I/O Bank 46 HP I/O Bank 66 X1Y8-X1Y11
X0Y1 Configuration
(RCAL) (RCAL)

GTY Quad 125 ILKN GTY Quad 225


HP I/O Bank 45 HP I/O Bank 65 Configuration
X0Y4-X0Y7 X0Y0 X1Y4-X1Y7

PCIE4
GTY Quad 124 CMAC GTY Quad 224
HP I/O Bank 44 HP I/O Bank 64 X1Y0
X0Y0-X0Y3 X0Y0 X1Y0-X1Y3
(tandem)
X15605-020817

Figure 1-107: XCVU3P and XQVU3P Banks


X-Ref Target - Figure 1-108

GTY Quad 128 GTY Quad 228


CMAC HP I/O Bank 48 HP I/O Bank 68 ILKN
X0Y16-X0Y19 X1Y16-X1Y19
X0Y2 K F X1Y2
J [L] E [R]
GTY Quad 127 GTY Quad 227
PCIE4 HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15 X1Y12-X1Y15
X0Y1 J E X1Y1
I [L] D [R]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
X0Y1 I D Configuration
H [L] (RCAL) C [R] (RCAL)
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 H C
G [L] B [R]
GTY Quad 124 PCIE4 GTY Quad 224
CMAC HP I/O Bank 44 HP I/O Bank 64
X0Y0-X0Y3 X1Y0 X1Y0-X1Y3
X0Y0 G B
F [L] (tandem) A [R]
X15606-020817

Figure 1-108: XCVU3P Banks in FFVC1517 Package and XQVU3P Banks in FFRC1517 Package

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XCVU5P Bank Diagrams


X-Ref Target - Figure 1-109

GTY Quad 133 CMAC ILKN GTY Quad 233


HP I/O Bank 53 HP I/O Bank 73
X0Y36-X0Y39 X0Y5 X1Y5 X1Y36-X1Y39

GTY Quad 132 PCIE4 ILKN GTY Quad 232


HP I/O Bank 52 HP I/O Bank 72
X0Y32-X0Y35 X0Y3 X1Y4 X1Y32-X1Y35

GTY Quad 131 GTY Quad 231


CMAC SYSMON
X0Y28-X0Y31 HP I/O Bank 51 HP I/O Bank 71 X1Y28-X1Y31
X0Y4 Configuration
(RCAL) (RCAL)

GTY Quad 130 ILKN GTY Quad 230


HP I/O Bank 50 HP I/O Bank 70 Configuration
X0Y24-X0Y27 X0Y3 X1Y24-X1Y27

GTY Quad 129 CMAC PCIE4 GTY Quad 229


HP I/O Bank 49 HP I/O Bank 69
X0Y20-X0Y23 X0Y3 X1Y2 X1Y20-X1Y23

SLR Crossing

GTY Quad 128 CMAC ILKN GTY Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y16-X0Y19 X0Y2 X1Y2 X1Y16-X1Y19

GTY Quad 127 PCIE4 ILKN GTY Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y12-X0Y15 X0Y1 X1Y1 X1Y12-X1Y15

GTY Quad 126 GTY Quad 226


CMAC SYSMON
X0Y8-X0Y11 HP I/O Bank 46 HP I/O Bank 66 X1Y8-X1Y1
X0Y1 Configuration
(RCAL) (RCAL)

GTY Quad 125 ILKN GTY Quad 225


HP I/O Bank 45 HP I/O Bank 65 Configuration
X0Y4-X0Y7 X0Y0 X1Y4-X1Y7

PCIE4
GTY Quad 124 CMAC GTY Quad 224
HP I/O Bank 44 HP I/O Bank 64 X1Y0
X0Y0-X0Y3 X0Y0 X1Y0-X1Y3
(tandem)
X18708-020817

Figure 1-109: XCVU5P Banks

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X-Ref Target - Figure 1-110

GTY Quad 233


GTY Quad 133 CMAC HP I/O Bank 53 HP I/O Bank 73 ILKN
X1Y36-X1Y39
X0Y36-X0Y39 X0Y5 M Q X1Y5
G [RN]
GTY Quad 132 GTY Quad 232
PCIE4 HP I/O Bank 52 HP I/O Bank 72 ILKN
X0Y32-X0Y35 X1Y32-X1Y35
X0Y3 L P X1Y4
M [LN] F [RN]
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y28-X0Y31 X1Y28-X1Y31
X0Y4 K O Configuration
L [LN] (RCAL) E [RN] (RCAL)
GTY Quad 130
ILKN HP I/O Bank 50 HP I/O Bank 70 GTY Quad 230
X0Y24-X0Y27 Configuration
X0Y3 J N X1Y24-X1Y27
K [LN]

GTY Quad 129 CMAC PCIE4 GTY Quad 229


HP I/O Bank 49 HP I/O Bank 69
X0Y20-X0Y23 X0Y3 X1Y2 X1Y20-X1Y23

SLR Crossing

GTY Quad 128 CMAC ILKN GTY Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y16-X0Y19 X0Y2 X1Y2 X1Y16-X1Y19

GTY Quad 127 GTY Quad 227


PCIE4 HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15 X1Y12-X1Y15
X0Y1 I E X1Y1
J [LS] D [RS]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
X0Y1 H D Configuration
I [LS] (RCAL) C [RS] (RCAL)
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 G C
H [LS] B [RS]
PCIE4 GTY Quad 224
GTY Quad 124 CMAC HP I/O Bank 44 HP I/O Bank 64
X1Y0 X1Y0-X1Y3
X0Y0-X0Y3 X0Y0 F B
(tandem) A [RS]

X18709-020817

Figure 1-110: XCVU5P Banks in FLVA2104 Package

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X-Ref Target - Figure 1-111

GTY Quad 133 GTY Quad 233


CMAC ILKN
X0Y36-X0Y39 HP I/O Bank 53 HP I/O Bank 73 X1Y36-X1Y39
X0Y5 X1Y5
S [LN] J [RN]
GTY Quad 132 GTY Quad 232
PCIE4 HP I/O Bank 52 HP I/O Bank 72 ILKN
X0Y32-X0Y35 X1Y32-X1Y35
X0Y3 L O X1Y4
R [LN] I [RN]
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y28-X0Y31 X1Y28-X1Y31
X0Y4 K N Configuration
Q [LN] (RCAL) H [RN] (RCAL)
GTY Quad 130 GTY Quad 230
ILKN HP I/O Bank 50 HP I/O Bank 70
X0Y24-X0Y27 Configuration X1Y24-X1Y27
X0Y3 J M
P [LN] G [RN]
GTY Quad 129 GTY Quad 229
CMAC PCIE4
X0Y20-X0Y23 HP I/O Bank 49 HP I/O Bank 69 X1Y20-X1Y23
X0Y3 X1Y2
O [LN] F [RN]
SLR Crossing
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 68 ILKN
X0Y16-X0Y19 HP I/O Bank 48 X1Y16-X1Y19
X0Y2 F (Partial) X1Y2
N [LS] E [RS]
GTY Quad 127 GTY Quad 227
PCIE4 HP I/O Bank 67 ILKN
X0Y12-X0Y15 HP I/O Bank 47 X1Y12-X1Y15
X0Y1 E X1Y1
M [LS] D [RS]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
X0Y1 I D Configuration
L [LS] (RCAL) C [RS] (RCAL)
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 H C
K [LS] B [RS]
PCIE4 GTY Quad 224
GTY Quad 124 CMAC HP I/O Bank 44 HP I/O Bank 64
X1Y0 X1Y0-X1Y3
X0Y0-X0Y3 X0Y0 G B
(tandem) A [RS]
X16504-020817

Figure 1-111: XCVU5P Banks in FLVB2104 Package

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X-Ref Target - Figure 1-112

GTY Quad 133 GTY Quad 233


CMAC ILKN
X0Y36-X0Y39 HP I/O Bank 53 HP I/O Bank 73 X1Y36-X1Y39
X0Y5 X1Y5
W [LN] J [RN]
GTY Quad 132 GTY Quad 232
PCIE4 HP I/O Bank 72 ILKN
X0Y32-X0Y35 HP I/O Bank 52 X1Y32-X1Y35
X0Y3 I X1Y4
V [LN] I [RN]
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 SYSMON
X0Y28-X0Y31 HP I/O Bank 51 X1Y28-X1Y31
X0Y4 H Configuration
U [LN] (RCAL) H [RN] (RCAL)
GTY Quad 130 GTY Quad 230
ILKN HP I/O Bank 70
X0Y24-X0Y27 HP I/O Bank 50 Configuration X1Y24-X1Y27
X0Y3 G
T [LN] G [RN]
GTY Quad 129 GTY Quad 229
CMAC PCIE4
X0Y20-X0Y23 HP I/O Bank 49 HP I/O Bank 69 X1Y20-X1Y23
X0Y3 X1Y2
S [LN] F [RN]
SLR Crossing
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 68 ILKN
X0Y16-X0Y19 HP I/O Bank 48 X1Y16-X1Y19
X0Y2 F X1Y2
R [LC] E [RC]
GTY Quad 127 GTY Quad 227
PCIE4 HP I/O Bank 67 ILKN
X0Y12-X0Y15 HP I/O Bank 47 X1Y12-X1Y15
X0Y1 E X1Y1
Q [LC] D [RC]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y8-X0Y11 HP I/O Bank 46 X1Y8-X1Y11
X0Y1 D Configuration
P [LC] (RCAL) C [RC] (RCAL)
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y4-X0Y7 HP I/O Bank 45 Configuration X1Y4-X1Y7
X0Y0 C
O [LC] B [RC]
GTY Quad 124 PCIE4 GTY Quad 224
CMAC HP I/O Bank 64
X0Y0-X0Y3 HP I/O Bank 44 X1Y0 X1Y0-X1Y3
X0Y0 B
N [LC] (tandem) A [RC]
X16505-020817

Figure 1-112: XCVU5P Banks in FLVC2104 Package

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XCVU7P and XQVU7P Bank Diagrams


X-Ref Target - Figure 1-113

GTY Quad 133 CMAC ILKN GTY Quad 233


HP I/O Bank 53 HP I/O Bank 73
X0Y36-X0Y39 X0Y5 X1Y5 X1Y36-X1Y39

GTY Quad 132 PCIE4 ILKN GTY Quad 232


HP I/O Bank 52 HP I/O Bank 72
X0Y32-X0Y35 X0Y3 X1Y4 X1Y32-X1Y35

GTY Quad 131 GTY Quad 231


CMAC SYSMON
X0Y28-X0Y31 HP I/O Bank 51 HP I/O Bank 71 X1Y28-X1Y31
X0Y4 Configuration
(RCAL) (RCAL)

GTY Quad 130 ILKN GTY Quad 230


HP I/O Bank 50 HP I/O Bank 70 Configuration
X0Y24-X0Y27 X0Y3 X1Y24-X1Y27

GTY Quad 129 CMAC PCIE4 GTY Quad 229


HP I/O Bank 49 HP I/O Bank 69
X0Y20-X0Y23 X0Y3 X1Y2 X1Y20-X1Y23

SLR Crossing

GTY Quad 128 CMAC ILKN GTY Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y16-X0Y19 X0Y2 X1Y2 X1Y16-X1Y19

GTY Quad 127 PCIE4 ILKN GTY Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y12-X0Y15 X0Y1 X1Y1 X1Y12-X1Y15

GTY Quad 126 GTY Quad 226


CMAC SYSMON
X0Y8-X0Y11 HP I/O Bank 46 HP I/O Bank 66 X1Y8-X1Y11
X0Y1 Configuration
(RCAL) (RCAL)

GTY Quad 125 ILKN GTY Quad 225


HP I/O Bank 45 HP I/O Bank 65 Configuration
X0Y4-X0Y7 X0Y0 X1Y4-X1Y7

PCIE4
GTY Quad 124 CMAC GTY Quad 224
HP I/O Bank 44 HP I/O Bank 64 X1Y0
X0Y0-X0Y3 X0Y0 X1Y0-X1Y3
(tandem)
X15607-020817

Figure 1-113: XCVU7P and XQVU7P Banks

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X-Ref Target - Figure 1-114

GTY Quad 233


GTY Quad 133 CMAC HP I/O Bank 53 HP I/O Bank 73 ILKN
X1Y36-X1Y39
X0Y36-X0Y39 X0Y5 M Q X1Y5
G [RN]
GTY Quad 132 GTY Quad 232
PCIE4 HP I/O Bank 52 HP I/O Bank 72 ILKN
X0Y32-X0Y35 X1Y32-X1Y35
X0Y3 L P X1Y4
M [LN] F [RN]
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y28-X0Y31 X1Y28-X1Y31
X0Y4 K O Configuration
L [LN] (RCAL) E [RN] (RCAL)
GTY Quad 130
ILKN HP I/O Bank 50 HP I/O Bank 70 GTY Quad 230
X0Y24-X0Y27 Configuration
X0Y3 J N X1Y24-X1Y27
K [LN]

GTY Quad 129 CMAC PCIE4 GTY Quad 229


HP I/O Bank 49 HP I/O Bank 69
X0Y20-X0Y23 X0Y3 X1Y2 X1Y20-X1Y23

SLR Crossing

GTY Quad 128 CMAC ILKN GTY Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y16-X0Y19 X0Y2 X1Y2 X1Y16-X1Y19

GTY Quad 127 GTY Quad 227


PCIE4 HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y12-X0Y15 X1Y12-X1Y15
X0Y1 I E X1Y1
J [LS] D [RS]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
X0Y1 H D Configuration
I [LS] (RCAL) C [RS] (RCAL)
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 G C
H [LS] B [RS]
PCIE4 GTY Quad 224
GTY Quad 124 CMAC HP I/O Bank 44 HP I/O Bank 64
X1Y0 X1Y0-X1Y3
X0Y0-X0Y3 X0Y0 F B
(tandem) A [RS]
X15608-020817

Figure 1-114: XCVU7P Banks in FLVA2104 Package and XQVU7P in FLRA2104 Package

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X-Ref Target - Figure 1-115

GTY Quad 133 GTY Quad 233


CMAC ILKN
X0Y36-X0Y39 HP I/O Bank 53 HP I/O Bank 73 X1Y36-X1Y39
X0Y5 X1Y5
S [LN] J [RN]
GTY Quad 132 GTY Quad 232
PCIE4 HP I/O Bank 52 HP I/O Bank 72 ILKN
X0Y32-X0Y35 X1Y32-X1Y35
X0Y3 L O X1Y4
R [LN] I [RN]
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 51 HP I/O Bank 71 SYSMON
X0Y28-X0Y31 X1Y28-X1Y31
X0Y4 K N Configuration
Q [LN] (RCAL) H [RN] (RCAL)
GTY Quad 130 GTY Quad 230
ILKN HP I/O Bank 50 HP I/O Bank 70
X0Y24-X0Y27 Configuration X1Y24-X1Y27
X0Y3 J M
P [LN] G [RN]
GTY Quad 129 GTY Quad 229
CMAC PCIE4
X0Y20-X0Y23 HP I/O Bank 49 HP I/O Bank 69 X1Y20-X1Y23
X0Y3 X1Y2
O [LN] F [RN]
SLR Crossing
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 68 ILKN
X0Y16-X0Y19 HP I/O Bank 48 X1Y16-X1Y19
X0Y2 F (Partial) X1Y2
N [LS] E [RS]
GTY Quad 127 GTY Quad 227
PCIE4 HP I/O Bank 67 ILKN
X0Y12-X0Y15 HP I/O Bank 47 X1Y12-X1Y15
X0Y1 E X1Y1
M [LS] D [RS]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y08-X0Y11 X1Y8-X1Y11
X0Y1 I D Configuration
L [LS] (RCAL) C [RS] (RCAL)
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 45 HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 H C
K [LS] B [RS]
PCIE4 GTY Quad 224
GTY Quad 124 CMAC HP I/O Bank 44 HP I/O Bank 64
X1Y0 X1Y0-X1Y3
X0Y0-X0Y3 X0Y0 G B
(tandem) A [RS]
X15609-020817

Figure 1-115: XCVU7P Banks in FLVB2104 Package and XQVU7P in FLRB2104 Package

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X-Ref Target - Figure 1-116

GTY Quad 133 GTY Quad 233


CMAC ILKN
X0Y36-X0Y39 HP I/O Bank 53 HP I/O Bank 73 X1Y36-X1Y39
X0Y5 X1Y5
W [LN] J [RN]
GTY Quad 132 GTY Quad 232
PCIE4 HP I/O Bank 72 ILKN
X0Y32-X0Y35 HP I/O Bank 52 X1Y32-X1Y35
X0Y3 I X1Y4
V [LN] I [RN]
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 SYSMON
X0Y28-X0Y31 HP I/O Bank 51 X1Y28-X1Y31
X0Y4 H Configuration
U [LN] (RCAL) H [RN] (RCAL)
GTY Quad 130 GTY Quad 230
ILKN HP I/O Bank 70
X0Y24-X0Y27 HP I/O Bank 50 Configuration X1Y24-X1Y27
X0Y3 G
T [LN] G [RN]
GTY Quad 129 GTY Quad 229
CMAC PCIE4
X0Y20-X0Y23 HP I/O Bank 49 HP I/O Bank 69 X1Y20-X1Y23
X0Y3 X1Y2
S [LN] F [RN]
SLR Crossing
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 68 ILKN
X0Y16-X0Y19 HP I/O Bank 48 X1Y16-X1Y19
X0Y2 F X1Y2
R [LC] E [RC]
GTY Quad 127 GTY Quad 227
PCIE4 HP I/O Bank 67 ILKN
X0Y12-X0Y15 HP I/O Bank 47 X1Y12-X1Y15
X0Y1 E X1Y1
Q [LC] D [RC]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y8-X0Y11 HP I/O Bank 46 X1Y8-X1Y11
X0Y1 D Configuration
P [LC] (RCAL) C [RC] (RCAL)
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y4-X0Y7 HP I/O Bank 45 Configuration X1Y4-X1Y7
X0Y0 C
O [LC] B [RC]
GTY Quad 124 PCIE4 GTY Quad 224
CMAC HP I/O Bank 64
X0Y0-X0Y3 HP I/O Bank 44 X1Y0 X1Y0-X1Y3
X0Y0 B
N [LC] (tandem) A [RC]
X15610-020817

Figure 1-116: XCVU7P Banks in FLVC2104 Package

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XCVU9P Bank Diagrams


X-Ref Target - Figure 1-117

GTY Quad 133 CMAC ILKN GTY Quad 233


HP I/O Bank 53 HP I/O Bank 73
X0Y56-X0Y59 X0Y8 X1Y8 X1Y56-X1Y59

GTY Quad 132 PCIE4 ILKN GTY Quad 232


HP I/O Bank 52 HP I/O Bank 72
X0Y52-X0Y55 X0Y5 X1Y7 X1Y52-X1Y55

GTY Quad 131 GTY Quad 231


CMAC SYSMON
X0Y48-X0Y51 HP I/O Bank 51 HP I/O Bank 71 X1Y48-X1Y51
X0Y7 Configuration
(RCAL) (RCAL)

GTY Quad 130 ILKN GTY Quad 230


HP I/O Bank 50 HP I/O Bank 70 Configuration
X0Y44-X0Y47 X0Y6 X1Y44-X1Y47

GTY Quad 129 CMAC PCIE4 GTY Quad 229


HP I/O Bank 49 HP I/O Bank 69
X0Y40-X0Y43 X0Y6 X1Y4 X1Y40-X1Y43

SLR Crossing

GTY Quad 128 CMAC ILKN GTY Quad 228


HP I/O Bank 48 HP I/O Bank 68
X0Y36-X0Y39 X0Y5 X1Y5 X1Y36-X1Y39

GTY Quad 127 PCIE4 ILKN GTY Quad 227


HP I/O Bank 47 HP I/O Bank 67
X0Y32-X0Y35 X0Y3 X1Y4 X1Y32-X1Y35

GTY Quad 126 GTY Quad 226


CMAC SYSMON
X0Y28-X0Y31 HP I/O Bank 46 HP I/O Bank 66 X1Y28-X1Y31
X0Y4 Configuration
(RCAL) (RCAL)

GTY Quad 125 ILKN GTY Quad 225


HP I/O Bank 45 HP I/O Bank 65 Configuration
X0Y24-X0Y27 X0Y3 X1Y24-X1Y27

PCIE4
GTY Quad 124 CMAC GTY Quad 224
HP I/O Bank 44 HP I/O Bank 64 X1Y2
X0Y20-X0Y23 X0Y3 X1Y20-X1Y23
(tandem)
SLR Crossing

GTY Quad 123 CMAC ILKN GTY Quad 223


HP I/O Bank 43 HP I/O Bank 63
X0Y16-X0Y19 X0Y2 X1Y2 X1Y16-X1Y19

GTY Quad 122 PCIE4 ILKN GTY Quad 222


HP I/O Bank 42 HP I/O Bank 62
X0Y12-X0Y15 X0Y1 X1Y1 X1Y12-X1Y15

GTY Quad 121 GTY Quad 221


CMAC SYSMON
X0Y8-X0Y11 HP I/O Bank 41 HP I/O Bank 61 X1Y8-X1Y11
X0Y1 Configuration
(RCAL) (RCAL)

GTY Quad 120 ILKN GTY Quad 220


HP I/O Bank 40 HP I/O Bank 60 Configuration
X0Y4-X0Y7 X0Y0 X1Y4-X1Y7

GTY Quad 119 CMAC PCIE4 GTY Quad 219


HP I/O Bank 39 HP I/O Bank 59
X0Y0-X0Y3 X0Y0 X1Y0 X1Y0-X1Y3
X15611-020817

Figure 1-117: XCVU9P Banks

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X-Ref Target - Figure 1-118

GTY Quad 233


GTY Quad 133 CMAC HP I/O Bank 73 ILKN
HP I/O Bank 53 X1Y56-X1Y59
X0Y56-X0Y59 X0Y8 Q X1Y8
G [RN]
GTY Quad 232
GTY Quad 132 PCIE4 HP I/O Bank 72 ILKN
HP I/O Bank 52 X1Y52-X1Y55
X0Y52-X0Y55 X0Y5 P X1Y7
F [RN]
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 SYSMON
X0Y48-X0Y51 HP I/O Bank 51 X1Y48-X1Y51
X0Y7 O Configuration
(RCAL) E [RN] (RCAL)

GTY Quad 130 ILKN HP I/O Bank 70 GTY Quad 230


HP I/O Bank 50 Configuration
X0Y44-X0Y47 X0Y6 N X1Y44-X1Y47

GTY Quad 129 CMAC PCIE4 GTY Quad 229


HP I/O Bank 49 HP I/O Bank 69
X0Y40-X0Y43 X0Y6 X1Y4 X1Y40-X1Y43

SLR Crossing

GTY Quad 128 CMAC HP I/O Bank 48 ILKN GTY Quad 228
HP I/O Bank 68
X0Y36-X0Y39 X0Y5 M X1Y5 X1Y36-X1Y39

GTY Quad 127 GTY Quad 227


PCIE4 HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y32-X0Y35 X1Y32-X1Y35
X0Y3 L E X1Y4
M [LN] D [RS]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y28-X0Y31 X1Y28-X1Y31
X0Y4 K D Configuration
L [LN] (RCAL) C [RS] (RCAL)
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 45 HP I/O Bank 65
X0Y24-X0Y27 Configuration X1Y24-X1Y27
X0Y3 J C
K [LN] B [RS]
PCIE4 GTY Quad 224
GTY Quad 124 CMAC HP I/O Bank 64
HP I/O Bank 44 X1Y2 X1Y20-X1Y23
X0Y20-X0Y23 X0Y3 B
(tandem) A [RS]
SLR Crossing

GTY Quad 123 CMAC HP I/O Bank 43 ILKN GTY Quad 223
HP I/O Bank 63
X0Y16-X0Y19 X0Y2 I X1Y2 X1Y16-X1Y19

GTY Quad 122


PCIE4 HP I/O Bank 42 ILKN GTY Quad 222
X0Y12-X0Y15 HP I/O Bank 62
X0Y1 H X1Y1 X1Y12-X1Y15
J [LS]
GTY Quad 121 GTY Quad 221
CMAC HP I/O Bank 41 SYSMON
X0Y8-X0Y11 HP I/O Bank 61 X1Y8-X1Y11
X0Y1 G Configuration
I [LS] (RCAL) (RCAL)
GTY Quad 120
ILKN HP I/O Bank 40 GTY Quad 220
X0Y4-X0Y7 HP I/O Bank 60 Configuration
X0Y0 F X1Y4-X1Y7
H [LS]

GTY Quad 119 CMAC PCIE4 GTY Quad 219


HP I/O Bank 39 HP I/O Bank 59
X0Y0-X0Y3 X0Y0 X1Y0 X1Y0-X1Y3

X15612-020817

Figure 1-118: XCVU9P Banks in FLGA2104 Package

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X-Ref Target - Figure 1-119

GTY Quad 233


GTY Quad 133 CMAC ILKN
HP I/O Bank 53 HP I/O Bank 73 X1Y56-X1Y59
X0Y56-X0Y59 X0Y8 X1Y8
J [RN]
GTY Quad 232
GTY Quad 132 PCIE4 HP I/O Bank 72 ILKN
HP I/O Bank 52 X1Y52-X1Y55
X0Y52-X0Y55 X0Y5 O X1Y7
I [RN]
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 SYSMON
X0Y48-X0Y51 HP I/O Bank 51 X1Y48-X1Y51
X0Y7 N Configuration
(RCAL) H [RN] (RCAL)
GTY Quad 230
GTY Quad 130 ILKN HP I/O Bank 70
HP I/O Bank 50 Configuration X1Y44-X1Y47
X0Y44-X0Y47 X0Y6 M
G [RN]
GTY Quad 229
GTY Quad 129 CMAC PCIE4
HP I/O Bank 49 HP I/O Bank 69 X1Y40-X1Y43
X0Y40-X0Y43 X0Y6 X1Y4
F [RN]
SLR Crossing
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 48 HP I/O Bank 68 ILKN
X0Y36-X0Y39 X1Y36-X1Y39
X0Y5 L F (Partial) X1Y5
S [LN] E [RS]
GTY Quad 127 GTY Quad 227
PCIE4 HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y32-X0Y35 X1Y32-X1Y35
X0Y3 K E X1Y4
R [LN] D [RS]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y28-X0Y31 X1Y28-X1Y31
X0Y4 J D Configuration
Q [LN] (RCAL) C [RS] (RCAL)
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y24-X0Y27 HP I/O Bank 45 Configuration X1Y24-X1Y27
X0Y3 C
P [LN] B [RS]
GTY Quad 124 PCIE4 GTY Quad 224
CMAC HP I/O Bank 64
X0Y20-X0Y23 HP I/O Bank 44 X1Y2 X1Y20-X1Y23
X0Y3 B
O [LN] (tandem) A [RS]
SLR Crossing
GTY Quad 123
CMAC ILKN GTY Quad 223
X0Y16-X0Y19 HP I/O Bank 43 HP I/O Bank 63
X0Y2 X1Y2 X1Y16-X1Y19
N [LS]
GTY Quad 122
PCIE4 HP I/O Bank 42 ILKN GTY Quad 222
X0Y12-X0Y15 HP I/O Bank 62
X0Y1 I X1Y1 X1Y12-X1Y15
M [LS]
GTY Quad 121 GTY Quad 221
CMAC HP I/O Bank 41 SYSMON
X0Y8-X0Y11 HP I/O Bank 61 X1Y8-X1Y11
X0Y1 H Configuration
L [LS] (RCAL) (RCAL)
GTY Quad 120
ILKN HP I/O Bank 40 GTY Quad 220
X0Y4-X0Y7 HP I/O Bank 60 Configuration
X0Y0 G X1Y4-X1Y7
K [LS]

GTY Quad 119 CMAC PCIE4 GTY Quad 219


HP I/O Bank 39 HP I/O Bank 59
X0Y0-X0Y3 X0Y0 X1Y0 X1Y0-X1Y3

X15613-020817

Figure 1-119: XCVU9P Banks in FLGB2104 Package

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X-Ref Target - Figure 1-120

GTY Quad 133 GTY Quad 233


CMAC ILKN
X0Y56-X0Y59 HP I/O Bank 53 HP I/O Bank 73 X1Y56-X1Y59
X0Y8 X1Y8
W [LN] J [RN]
GTY Quad 132 GTY Quad 232
PCIE4 HP I/O Bank 72 ILKN
X0Y52-X0Y55 HP I/O Bank 52 X1Y52-X1Y55
X0Y5 I X1Y7
V [LN] I [RN]
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 SYSMON
X0Y48-X0Y51 HP I/O Bank 51 X1Y48-X1Y51
X0Y7 H Configuration
U [LN] (RCAL) H [RN] (RCAL)
GTY Quad 130 GTY Quad 230
ILKN HP I/O Bank 70
X0Y44-X0Y47 HP I/O Bank 50 Configuration X1Y44-X1Y47
X0Y6 G
T [LN] G [RN]
GTY Quad 129 GTY Quad 229
CMAC PCIE4
X0Y40-X0Y43 HP I/O Bank 49 HP I/O Bank 69 X1Y40-X1Y43
X0Y6 X1Y4
S [LN] F [RN]
SLR Crossing
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 68 ILKN
X0Y36-X0Y39 HP I/O Bank 48 X1Y36-X1Y39
X0Y5 F X1Y5
R [LC] E [RC]
GTY Quad 127 GTY Quad 227
PCIE4 HP I/O Bank 67 ILKN
X0Y32-X0Y35 HP I/O Bank 47 X1Y32-X1Y35
X0Y3 E X1Y4
Q [LC] D [RC]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y28-X0Y31 HP I/O Bank 46 X1Y28-X1Y31
X0Y4 D Configuration
P [LC] (RCAL) C [RC] (RCAL)
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y24-X0Y27 HP I/O Bank 45 Configuration X1Y24-X1Y27
X0Y3 C
O [LC] B [RC]
GTY Quad 124 PCIE4 GTY Quad 224
CMAC HP I/O Bank 64
X0Y20-X0Y23 HP I/O Bank 44 X1Y2 X1Y20-X1Y23
X0Y3 B
N [LC] (tandem) A [RC]
SLR Crossing

GTY Quad 123 CMAC ILKN GTY Quad 223


HP I/O Bank 43 HP I/O Bank 63
X0Y16-X0Y19 X0Y2 X1Y2 X1Y16-X1Y19

GTY Quad 122 GTY Quad 222


PCIE4 ILKN
X0Y12-X0Y15 HP I/O Bank 42 HP I/O Bank 62 X1Y12-X1Y15
X0Y1 X1Y1
Z [LS] M [RS]
GTY Quad 121 GTY Quad 221
CMAC SYSMON
X0Y8-X0Y11 HP I/O Bank 41 HP I/O Bank 61 X1Y8-X1Y11
X0Y1 Configuration
Y [LS] (RCAL) L [RS] (RCAL)
GTY Quad 120 GTY Quad 220
ILKN
X0Y4-X0Y7 HP I/O Bank 40 HP I/O Bank 60 Configuration X1Y4-X1Y7
X0Y0
X [LS] K [RS]

GTY Quad 119 CMAC PCIE4 GTY Quad 219


HP I/O Bank 39 HP I/O Bank 59
X0Y0-X0Y3 X0Y0 X1Y0 X1Y0-X1Y3

X15614-020817

Figure 1-120: XCVU9P Banks in FLGC2104 Package

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X-Ref Target - Figure 1-121

GTY Quad 133 CMAC ILKN GTY Quad 233


HP I/O Bank 53 HP I/O Bank 73 X1Y56-X1Y59
X0Y56-X0Y59 X0Y8 X1Y8
J [RN]
GTY Quad 132 GTY Quad 232
PCIE4 HP I/O Bank 72 ILKN
HP I/O Bank 52 X1Y52-X1Y55
X0Y52-X0Y55 X0Y5 O X1Y7 I [RN]
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 SYSMON
X0Y48-X0Y51 HP I/O Bank 51 X1Y48-X1Y51
X0Y7 N Configuration
S [LN] (RCAL) H [RN] (RCAL)

GTY Quad 130 GTY Quad 230


ILKN HP I/O Bank 70
HP I/O Bank 50 Configuration X1Y44-X1Y47
X0Y44-X0Y47 X0Y6 M
G [RN]

GTY Quad 129 CMAC PCIE4 GTY Quad 229


HP I/O Bank 49 HP I/O Bank 69 X1Y40-X1Y43
X0Y40-X0Y43 X0Y6 X1Y4
F [RN]
SLR Crossing
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 48 ILKN
HP I/O Bank 68 X1Y36-X1Y39
X0Y36-X0Y39 X0Y5 L X1Y5
E [RS]
GTY Quad 127 GTY Quad 227
PCIE4 HP I/O Bank 47 HP I/O Bank 67 ILKN
X0Y32-X0Y35 X1Y32-X1Y35
X0Y3 K E X1Y4
R [LN] D [RS]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 46 HP I/O Bank 66 SYSMON
X0Y28-X0Y31 X1Y28-X1Y31
X0Y4 J D Configuration
Q [LN] (RCAL) C [RS] (RCAL)
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y24-X0Y27 HP I/O Bank 45 Configuration X1Y24-X1Y27
X0Y3 C
P [LN] B [RS]
GTY Quad 124 PCIE4 GTY Quad 224
CMAC HP I/O Bank 64
X0Y20-X0Y23 HP I/O Bank 44 X1Y2 X1Y20-X1Y23
X0Y3 B
O [LN] (tandem) A [RS]
SLR Crossing
GTY Quad 123 CMAC ILKN GTY Quad 223
X0Y16-X0Y19 HP I/O Bank 43 HP I/O Bank 63
X0Y2 X1Y2 X1Y16-X1Y19
N [LS]
GTY Quad 122
PCIE4 HP I/O Bank 42 ILKN GTY Quad 222
X0Y12-X0Y15 HP I/O Bank 62
M [LS] X0Y1 H X1Y1 X1Y12-X1Y15
GTY Quad 121
CMAC HP I/O Bank 41 SYSMON GTY Quad 221
X0Y8-X0Y11 HP I/O Bank 61
X0Y1 G Configuration X1Y8-X1Y11
L [LS](RCAL)
GTY Quad 120
ILKN HP I/O Bank 40 GTY Quad 220
X0Y4-X0Y7 HP I/O Bank 60 Configuration
X0Y0 F X1Y4-X1Y7
K [LS]

GTY Quad 119 CMAC PCIE4 GTY Quad 219


HP I/O Bank 39 HP I/O Bank 59
X0Y0-X0Y3 X0Y0 X1Y0 X1Y0-X1Y3

X18713-020817

Figure 1-121: XCVU9P Banks in FSGD2104 Package

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X-Ref Target - Figure 1-122

GTY Quad 133 GTY Quad 233


CMAC ILKN
X0Y56-X0Y59 HP I/O Bank 53 HP I/O Bank 73 X1Y56-X1Y59
X0Y8 X1Y8
Z [LN] J [RN]
GTY Quad 132 GTY Quad 232
PCIE4 HP I/O Bank 72 ILKN
X0Y52-X0Y55 HP I/O Bank 52 X1Y52-X1Y55
X0Y5 K X1Y7
Y [LN] I [RN]
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 SYSMON
X0Y48-X0Y51 HP I/O Bank 51 X1Y48-X1Y51
X0Y7 J Configuration
X [LN] (RCAL) H [RN] (RCAL)
GTY Quad 130 GTY Quad 230
ILKN HP I/O Bank 70
X0Y44-X0Y47 HP I/O Bank 50 Configuration X1Y44-X1Y47
X0Y6 I
W [LUC] G [RUC]
GTY Quad 129 GTY Quad 229
CMAC PCIE4
X0Y40-X0Y43 HP I/O Bank 49 HP I/O Bank 69 X1Y40-X1Y43
X0Y6 X1Y4
V [LUC] F [RUC]
SLR Crossing
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 68 ILKN
X0Y36-X0Y39 HP I/O Bank 48 X1Y36-X1Y39
X0Y5 H (Partial) X1Y5
U [LUC] E [RUC]
GTY Quad 127 GTY Quad 227
PCIE4 HP I/O Bank 67 ILKN
X0Y32-X0Y35 HP I/O Bank 47 X1Y32-X1Y35
X0Y3 G X1Y4
T [LUC] D [RUC]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y28-X0Y31 HP I/O Bank 46 X1Y28-X1Y31
X0Y4 B (Partial) Configuration
S [LLC] (RCAL) C [RLC] (RCAL)
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y24-X0Y27 HP I/O Bank 45 Configuration X1Y24-X1Y27
X0Y3 C
R [LLC] B [RLC]
GTY Quad 124 PCIE4 GTY Quad 224
CMAC
X0Y20-X0Y23 HP I/O Bank 44 HP I/O Bank 64 X1Y2 X1Y20-X1Y23
X0Y3
Q [LLC] (tandem) A [RLC]
SLR Crossing
GTY Quad 123 GTY Quad 223
CMAC HP I/O Bank 63 ILKN
X0Y16-X0Y19 HP I/O Bank 43 X1Y16-X1Y19
X0Y2 F X1Y2
AF [LLC] P [RLC]
GTY Quad 122 GTY Quad 222
PCIE4 HP I/O Bank 62 ILKN
X0Y12-X0Y15 HP I/O Bank 42 X1Y12-X1Y15
X0Y1 E X1Y1
AE [LS] O [RS]
GTY Quad 121 GTY Quad 221
CMAC HP I/O Bank 61 SYSMON
X0Y8-X0Y11 HP I/O Bank 41 X1Y8-X1Y11
X0Y1 D Configuration
AD [LS] (RCAL) N [RS] (RCAL)
GTY Quad 120 GTY Quad 220
ILKN
X0Y4-X0Y7 HP I/O Bank 40 HP I/O Bank 60 Configuration X1Y4-X1Y7
X0Y0
AC [LS] M [RS]
GTY Quad 119 GTY Quad 219
CMAC PCIE4
X0Y0-X0Y3 HP I/O Bank 39 HP I/O Bank 59 X1Y0-X1Y3
X0Y0 X1Y0
AB [LS] L [RS]
X15615-020817

Figure 1-122: XCVU9P Banks in FLGA2577 Package

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XCVU11P and XQVU11P Bank Diagrams


X-Ref Target - Figure 1-123

GTY Quad 135 CMAC ILKN GTY Quad 235


HP I/O Bank 75
X0Y44-X0Y47 X0Y8 X1Y5 X1Y44-X1Y47

GTY Quad 134 CMAC SYSMON GTY Quad 234


HP I/O Bank 74
X0Y40-X0Y43 X0Y7 Configuration X1Y40-X1Y43

GTY Quad 133 GTY Quad 233


ILKN
X0Y36-X0Y39 HP I/O Bank 73 Configuration X1Y36-X1Y39
X0Y4
(RCAL) (RCAL)

GTY Quad 132 CMAC PCIE4 GTY Quad 232


HP I/O Bank 72
X0Y32-X0Y35 X0Y6 X0Y2 X1Y32-X1Y35

SLR Crossing

GTY Quad 131 CMAC ILKN GTY Quad 231


HP I/O Bank 71
X0Y28-X0Y31 X0Y5 X1Y3 X1Y28-X1Y31

GTY Quad 130 CMAC SYSMON GTY Quad 230


HP I/O Bank 70
X0Y24-X0Y27 X0Y4 Configuration X1Y24-X1Y27

GTY Quad 129 GTY Quad 229


ILKN
X0Y20-X0Y23 HP I/O Bank 69 Configuration X1Y20-X1Y23
X0Y2
(RCAL) (RCAL)

GTY Quad 128 CMAC PCIE4 GTY Quad 228


HP I/O Bank 68
X0Y16-X0Y19 X0Y3 X0Y1 X1Y16-X1Y19

SLR Crossing

GTY Quad 127 CMAC ILKN GTY Quad 227


HP I/O Bank 67
X0Y12-X0Y15 X0Y2 X1Y1 X1Y12-X1Y15

GTY Quad 126 CMAC SYSMON GTY Quad 226


HP I/O Bank 66
X0Y8-X0Y11 X0Y1 Configuration X1Y8-X1Y11

GTY Quad 125 GTY Quad 225


ILKN
X0Y4-X0Y7 HP I/O Bank 65 Configuration X1Y4-X1Y7
X0Y0
(RCAL) (RCAL)
PCIE4
GTY Quad 124 CMAC GTY Quad 224
HP I/O Bank 64 X0Y0
X0Y0-X0Y3 X0Y0 X1Y0-X1Y3
(tandem)
X15616-020817

Figure 1-123: XCVU11P and XQVU11P Banks

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X-Ref Target - Figure 1-124

GTY Quad 135 CMAC HP I/O Bank 75 ILKN GTY Quad 235
X0Y44-X0Y47 X0Y8 P X1Y5 X1Y44-X1Y47

GTY Quad 134 CMAC HP I/O Bank 74 SYSMON GTY Quad 234
X0Y40-X0Y43 X0Y7 O Configuration X1Y40-X1Y43

GTY Quad 133 GTY Quad 233


ILKN HP I/O Bank 73
X0Y36-X0Y39 Configuration X1Y36-X1Y39
X0Y4 N
(RCAL) J [RN] (RCAL)
GTY Quad 232
GTY Quad 132 CMAC HP I/O Bank 72 PCIE4
X1Y32-X1Y35
X0Y32-X0Y35 X0Y6 M X0Y2
I [RN]
SLR Crossing
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 ILKN
X0Y28-X0Y31 X1Y28-X1Y31
X0Y5 L X1Y3
P [LN] H [RN]
GTY Quad 130 GTY Quad 230
CMAC HP I/O Bank 70 SYSMON
X0Y24-X0Y27 X1Y24-X1Y27
X0Y4 K Configuration
Q [LN] G [RN]
GTY Quad 129 GTY Quad 229
ILKN HP I/O Bank 69
X0Y20-X0Y23 Configuration X1Y20-X1Y23
X0Y2 J
N [LN] (RCAL) F [RN] (RCAL)
GTY Quad 228
GTY Quad 128 CMAC HP I/O Bank 68 PCIE4
X1Y16-X1Y19
X0Y16-X0Y19 X0Y3 F X0Y1
E [RS]
SLR Crossing
GTY Quad 127 GTY Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y12-X0Y15 X1Y12-X1Y15
X0Y2 E X1Y1
M [LS] D [RS]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
X0Y1 D Configuration
L [LS] C [RS]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 C
K [LS] (RCAL) B [RS] (RCAL)
PCIE4 GTY Quad 224
GTY Quad 124 CMAC HP I/O Bank 64
X0Y0 X1Y0-X1Y3
X0Y0-X0Y3 X0Y0 G
(tandem) A [RS]
X15620-020817

Figure 1-124: XCVU11P Banks in FLGF1924 Package

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X-Ref Target - Figure 1-125

GTY Quad 135 CMAC ILKN GTY Quad 235


HP I/O Bank 75
X0Y44-X0Y47 X0Y8 X1Y5 X1Y44-X1Y47

GTY Quad 134 CMAC HP I/O Bank 74 SYSMON GTY Quad 234
X0Y40-X0Y43 X0Y7 O Configuration X1Y40-X1Y43

GTY Quad 133 GTY Quad 233


ILKN HP I/O Bank 73
X0Y36-X0Y39 Configuration X1Y36-X1Y39
X0Y4 N
S [LN] (RCAL) J [RN] (RCAL)
GTY Quad 232
GTY Quad 132 CMAC HP I/O Bank 72 PCIE4
X1Y32-X1Y35
X0Y32-X0Y35 X0Y6 M X0Y2
I [RN]
SLR Crossing
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 ILKN
X0Y28-X0Y31 X1Y28-X1Y31
X0Y5 L X1Y3
R [LN] H [RN]
GTY Quad 130 GTY Quad 230
CMAC HP I/O Bank 70 SYSMON
X0Y24-X0Y27 X1Y24-X1Y27
X0Y4 K Configuration
Q [LN] G [RN]
GTY Quad 129 GTY Quad 229
ILKN HP I/O Bank 69
X0Y20-X0Y23 Configuration X1Y20-X1Y23
X0Y2 J
P [LN] (RCAL) F [RN] (RCAL)
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 68 PCIE4
X0Y16-X0Y19 X1Y16-X1Y19
X0Y3 G X0Y1
O [LN] E [RS]
SLR Crossing
GTY Quad 127 GTY Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y12-X0Y15 X1Y12-X1Y15
X0Y2 E X1Y1
N [LS] D [RS]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
X0Y1 D Configuration
M [LS] C [RS]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 C
L [LS] (RCAL) B [RS] (RCAL)
GTY Quad 124 PCIE4 GTY Quad 224
CMAC HP I/O Bank 64
X0Y0-X0Y3 X0Y0 X1Y0-X1Y3
X0Y0 B
K [LS] (tandem) A [RS]
X15617-020817

Figure 1-125: XCVU11P Banks in FLGB2104 Package

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X-Ref Target - Figure 1-126

GTY Quad 135 GTY Quad 235


CMAC ILKN
X0Y44-X0Y47 HP I/O Bank 75 X1Y44-X1Y47
X0Y8 X1Y5
W [LN] J [RN]
GTY Quad 134 GTY Quad 234
CMAC SYSMON
X0Y40-X0Y43 HP I/O Bank 74 X1Y40-X1Y43
X0Y7 Configuration
V [LN] I [RN]
GTY Quad 133 GTY Quad 233
ILKN
X0Y36-X0Y39 HP I/O Bank 73 Configuration X1Y36-X1Y39
X0Y4
U [LN] (RCAL) H [RN] (RCAL)
GTY Quad 132 GTY Quad 232
CMAC PCIE4
X0Y32-X0Y35 HP I/O Bank 72 X1Y32-X1Y35
X0Y6 X0Y2
T [LN] G [RN]
SLR Crossing
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 ILKN
X0Y28-X0Y31 X1Y28-X1Y31
X0Y5 I X1Y3
S [LN] F [RN]
GTY Quad 130 GTY Quad 230
CMAC HP I/O Bank 70 SYSMON
X0Y24-X0Y27 X1Y24-X1Y27
X0Y4 H Configuration
R [LC] E [RC]
GTY Quad 129 GTY Quad 229
ILKN HP I/O Bank 69
X0Y20-X0Y23 Configuration X1Y20-X1Y23
X0Y2 G
Q [LC] (RCAL) D [RC] (RCAL)
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 68 PCIE4
X0Y16-X0Y19 X1Y16-X1Y19
X0Y3 F X0Y1
P [LC] C [RC]
SLR Crossing
GTY Quad 127 GTY Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y12-X0Y15 X1Y12-X1Y15
X0Y2 E X1Y1
O [LC] B [RC]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
X0Y1 D Configuration
N [LC] A [RC]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 C
Z [LS] (RCAL) M [RS] (RCAL)
GTY Quad 124 PCIE4 GTY Quad 224
CMAC HP I/O Bank 64
X0Y0-X0Y3 X0Y0 X1Y0-X1Y3
X0Y0 B
Y [LS] (tandem) L [RS]
X15618-020817

Figure 1-126: XCVU11P Banks in FLGC2104 Package and XQVU11P Banks in FLRC2104 Package

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X-Ref Target - Figure 1-127

GTY Quad 135 CMAC ILKN GTY Quad 235


HP I/O Bank 75
X0Y44-X0Y47 X0Y8 X1Y5 X1Y44-X1Y47

GTY Quad 134 CMAC HP I/O Bank 74 SYSMON GTY Quad 234
X0Y40-X0Y43 X0Y7 O Configuration X1Y40-X1Y43

GTY Quad 133 GTY Quad 233


ILKN HP I/O Bank 73
X0Y36-X0Y39 Configuration X1Y36-X1Y39
X0Y4 N
S [LN] (RCAL) J [RN] (RCAL)
GTY Quad 232
GTY Quad 132 CMAC HP I/O Bank 72 PCIE4
X1Y32-X1Y35
X0Y32-X0Y35 X0Y6 M X0Y2
I [RN]
SLR Crossing
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 ILKN
X0Y28-X0Y31 X1Y28-X1Y31
X0Y5 L X1Y3
R [LN] H [RN]
GTY Quad 130 GTY Quad 230
CMAC HP I/O Bank 70 SYSMON
X0Y24-X0Y27 X1Y24-X1Y27
X0Y4 K Configuration
Q [LN] G [RN]
GTY Quad 129 GTY Quad 229
ILKN HP I/O Bank 69
X0Y20-X0Y23 Configuration X1Y20-X1Y23
X0Y2 J
P [LN] (RCAL) F [RN] (RCAL)
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 68 PCIE4
X0Y16-X0Y19 X1Y16-X1Y19
X0Y3 F X0Y1
O [LN] E [RS]
SLR Crossing
GTY Quad 127 GTY Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y12-X0Y15 X1Y12-X1Y15
X0Y2 E X1Y1
N [LS] D [RS]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
X0Y1 D Configuration
M [LS] C [RS]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 C
L [LS] (RCAL) B [RS] (RCAL)
GTY Quad 124 PCIE4 GTY Quad 224
CMAC HP I/O Bank 64
X0Y0-X0Y3 X0Y0 X1Y0-X1Y3
X0Y0 B
K [LS] (tandem) A [RS]
;

Figure 1-127: XCVU11P Banks in FSGD2104 Package

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X-Ref Target - Figure 1-128

GTY Quad 135 GTY Quad 235


CMAC HP I/O Bank 75 ILKN
X0Y44-X0Y47 X1Y44-X1Y47
X0Y8 K X1Y5
AA [LN] K [RN]
GTY Quad 134 GTY Quad 234
CMAC HP I/O Bank 74 SYSMON
X0Y40-X0Y43 X1Y40-X1Y43
X0Y7 J Configuration
Z [LN] J [RN]
GTY Quad 133 GTY Quad 233
ILKN HP I/O Bank 73
X0Y36-X0Y39 Configuration X1Y36-X1Y39
X0Y4 I
Y [LN] (RCAL) I [RN] (RCAL)
GTY Quad 132 GTY Quad 232
CMAC HP I/O Bank 72 PCIE4
X0Y32-X0Y35 X1Y32-X1Y35
X0Y6 H (Partial) X0Y2
X [LN] H [RN]
SLR Crossing
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 ILKN
X0Y28-X0Y31 X1Y28-X1Y31
X0Y5 G X1Y3
W [LUC] G [RUC]
GTY Quad 130 GTY Quad 230
CMAC HP I/O Bank 70 SYSMON
X0Y24-X0Y27 X1Y24-X1Y27
X0Y4 F Configuration
V [LUC] F [RUC]
GTY Quad 129 GTY Quad 229
ILKN HP I/O Bank 69
X0Y20-X0Y23 Configuration X1Y20-X1Y23
X0Y2 E
U [LUC] (RCAL) E [RUC] (RCAL)
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 68 PCIE4
X0Y16-X0Y19 X1Y16-X1Y19
X0Y3 D X0Y1
T [LUC] D [RUC]
SLR Crossing
GTY Quad 127 GTY Quad 227
CMAC ILKN
X0Y12-X0Y15 HP I/O Bank 67 X1Y12-X1Y15
X0Y2 X1Y1
S [LLC] C [RLC]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
X0Y1 B (Partial) Configuration
R [LLC] B [RLC]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 C
Q [LLC] (RCAL) A [RLC] (RCAL)
GTY Quad 124 PCIE4 GTY Quad 224
CMAC
X0Y0-X0Y3 HP I/O Bank 64 X0Y0 X1Y0-X1Y3
X0Y0
AF [LLC] (tandem) P [RLC]
X15619-020817

Figure 1-128: XCVU11P Banks in FLGA2577 Package

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XCVU13P Bank Diagrams


X-Ref Target - Figure 1-129

GTY Quad 135 CMAC ILKN GTY Quad 235


HP I/O Bank 75
X0Y60-X0Y63 X0Y11 X1Y7 X1Y60-X1Y63

GTY Quad 134 CMAC SYSMON GTY Quad 234


HP I/O Bank 74
X0Y56-X0Y59 X0Y10 Configuration X1Y56-X1Y59
GTY Quad 133 GTY Quad 233
ILKN
X0Y52-X0Y55 HP I/O Bank 73 Configuration X1Y52-X1Y55
X0Y6
(RCAL) (RCAL)
GTY Quad 132 CMAC PCIE4 GTY Quad 232
HP I/O Bank 72
X0Y48-X0Y51 X0Y9 X0Y3 X1Y48-X1Y51
SLR Crossing
GTY Quad 131 CMAC ILKN GTY Quad 231
HP I/O Bank 71
X0Y44-X0Y47 X0Y8 X1Y5 X1Y44-X1Y47

GTY Quad 130 CMAC SYSMON GTY Quad 230


HP I/O Bank 70
X0Y40-X0Y43 X0Y7 Configuration X1Y40-X1Y43
GTY Quad 129 GTY Quad 229
ILKN
X0Y36-X0Y39 HP I/O Bank 69 Configuration X1Y36-X1Y39
X0Y4
(RCAL) (RCAL)
GTY Quad 128 CMAC PCIE4 GTY Quad 228
HP I/O Bank 68
X0Y32-X0Y35 X0Y6 X0Y2 X1Y32-X1Y35
SLR Crossing
GTY Quad 127 CMAC ILKN GTY Quad 227
HP I/O Bank 67
X0Y28-X0Y31 X0Y5 X1Y3 X1Y28-X1Y31

GTY Quad 126 CMAC SYSMON GTY Quad 226


HP I/O Bank 66
X0Y24-X0Y27 X0Y4 Configuration X1Y24-X1Y27
GTY Quad 125 GTY Quad 225
ILKN
X0Y20-X0Y23 HP I/O Bank 65 Configuration X1Y20-X1Y23
X0Y2
(RCAL) (RCAL)
PCIE4
GTY Quad 124 CMAC GTY Quad 224
HP I/O Bank 64 X0Y1
X0Y16-X0Y19 X0Y3 X1Y16-X1Y19
(tandem)
SLR Crossing
GTY Quad 123 CMAC ILKN GTY Quad 223
HP I/O Bank 63
X0Y12-X0Y15 X0Y2 X1Y1 X1Y12-X1Y15

GTY Quad 122 CMAC SYSMON GTY Quad 222


HP I/O Bank 62
X0Y8-X0Y11 X0Y1 Configuration X1Y8-X1Y11
GTY Quad 121 GTY Quad 221
ILKN
X0Y4-X0Y7 HP I/O Bank 61 Configuration X1Y4-X1Y7
X0Y0
(RCAL) (RCAL)
GTY Quad 120 CMAC PCIE4 GTY Quad 220
HP I/O Bank 60
X0Y0-X0Y3 X0Y0 X0Y0 X1Y0-X1Y3
X15621-020817

Figure 1-129: XCVU13P Banks

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X-Ref Target - Figure 1-130

GTY Quad 135 CMAC HP I/O Bank 75 ILKN GTY Quad 235
X0Y60-X0Y63 X0Y11 Q X1Y7 X1Y60-X1Y63

GTY Quad 134 CMAC HP I/O Bank 74 SYSMON GTY Quad 234
X0Y56-X0Y59 X0Y10 P Configuration X1Y56-X1Y59
GTY Quad 133 GTY Quad 233
ILKN HP I/O Bank 73
X0Y52-X0Y55 Configuration X1Y52-X1Y55
X0Y6 O
(RCAL) (RCAL)
GTY Quad 132 CMAC HP I/O Bank 72 PCIE4 GTY Quad 232
X0Y48-X0Y51 X0Y9 N X0Y3 X1Y48-X1Y51
SLR Crossing
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 ILKN
X0Y44-X0Y47 X1Y44-X1Y47
X0Y8 M X1Y5
M [LN] G [RN]
GTY Quad 130 GTY Quad 230
CMAC HP I/O Bank 70 SYSMON
X0Y40-X0Y43 X1Y40-X1Y43
X0Y7 L Configuration
L [LN] F [RN]
GTY Quad 129 GTY Quad 229
ILKN HP I/O Bank 69
X0Y36-X0Y39 Configuration X1Y36-X1Y39
X0Y4 K
K [LN] (RCAL) E [RN] (RCAL)
GTY Quad 128 CMAC HP I/O Bank 68 PCIE4 GTY Quad 228
X0Y32-X0Y35 X0Y6 J X0Y2 X1Y32-X1Y35
SLR Crossing
GTY Quad 127 GTY Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y28-X0Y31 X1Y28-X1Y31
X0Y5 E X1Y3
J [LS] D [RS]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y24-X0Y27 X1Y24-X1Y27
X0Y4 D Configuration
I [LS] C [RS]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y20-X0Y23 Configuration X1Y20-X1Y23
X0Y2 C
H [LS] (RCAL) B [RS] (RCAL)
PCIE4 GTY Quad 224
GTY Quad 124 CMAC HP I/O Bank 64
X0Y1 X1Y16-X1Y19
X0Y16-X0Y19 X0Y3 B
(tandem) A [RS]
SLR Crossing
GTY Quad 123 CMAC HP I/O Bank 63 ILKN GTY Quad 223
X0Y12-X0Y15 X0Y2 I X1Y1 X1Y12-X1Y15

GTY Quad 122 CMAC HP I/O Bank 62 SYSMON GTY Quad 222
X0Y8-X0Y11 X0Y1 H Configuration X1Y8-X1Y11
GTY Quad 121 GTY Quad 221
ILKN HP I/O Bank 61
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 G
(RCAL) (RCAL)
GTY Quad 120 CMAC HP I/O Bank 60 PCIE4 GTY Quad 220
X0Y0-X0Y3 X0Y0 F X0Y0 X1Y0-X1Y3

X15622-020817

Figure 1-130: XCVU13P Banks in FHGA2104 Package

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X-Ref Target - Figure 1-131

GTY Quad 135 CMAC ILKN GTY Quad 235


HP I/O Bank 75
X0Y60-X0Y63 X0Y11 X1Y7 X1Y60-X1Y63

GTY Quad 134 CMAC HP I/O Bank 74 SYSMON GTY Quad 234
X0Y56-X0Y59 X0Y10 O Configuration X1Y56-X1Y59
GTY Quad 133 GTY Quad 233
ILKN HP I/O Bank 73
X0Y52-X0Y55 Configuration X1Y52-X1Y55
X0Y6 N
S [LN] (RCAL) J [RN] (RCAL)
GTY Quad 232
GTY Quad 132 CMAC HP I/O Bank 72 PCIE4 X1Y48-X1Y51
X0Y48-X0Y51 X0Y9 M X0Y3 I [RN]
SLR Crossing
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 ILKN
X0Y44-X0Y47 X1Y44-X1Y47
X0Y8 L X1Y5
R [LN] H [RN]
GTY Quad 130 GTY Quad 230
CMAC HP I/O Bank 70 SYSMON
X0Y40-X0Y43 X1Y40-X1Y43
X0Y7 K Configuration
Q [LN] G [RN]
GTY Quad 129 GTY Quad 229
ILKN HP I/O Bank 69
X0Y36-X0Y39 Configuration X1Y36-X1Y39
X0Y4 J
P [LN] (RCAL) F [RN] (RCAL)
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 68 PCIE4
X0Y32-X0Y35 X1Y32-X1Y35
X0Y6 F (Partial) X0Y2
O [LN] E [RS]
SLR Crossing
GTY Quad 127 GTY Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y28-X0Y31 X1Y28-X1Y31
X0Y5 E X1Y3
N [LS] D [RS]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y24-X0Y27 X1Y24-X1Y27
X0Y4 D Configuration
M [LS] C [RS]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y20-X0Y23 Configuration X1Y20-X1Y23
X0Y2 C
L [LS] (RCAL) B [RS] (RCAL)
GTY Quad 124 PCIE4 GTY Quad 224
CMAC HP I/O Bank 64
X0Y16-X0Y19 X0Y1 X1Y16-X1Y19
X0Y3 B
K [LS] (tandem) A [RS]
SLR Crossing
GTY Quad 123 CMAC HP I/O Bank 63 ILKN GTY Quad 223
X0Y12-X0Y15 X0Y2 I X1Y1 X1Y12-X1Y15

GTY Quad 122 CMAC HP I/O Bank 62 SYSMON GTY Quad 222
X0Y8-X0Y11 X0Y1 H Configuration X1Y8-X1Y11
GTY Quad 121 GTY Quad 221
ILKN HP I/O Bank 61
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 G
(RCAL) (RCAL)
GTY Quad 120 CMAC HP I/O Bank 60 PCIE4 GTY Quad 220
X0Y0-X0Y3 X0Y0 F X0Y0 X1Y0-X1Y3

X15623-020817

Figure 1-131: XCVU13P Banks in FHGB2104 Package

UltraScale Device Packaging and Pinouts Send Feedback


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Chapter 1: Packaging Overview

X-Ref Target - Figure 1-132

GTY Quad 135 CMAC ILKN GTY Quad 235


HP I/O Bank 75
X0Y60-X0Y63 X0Y11 X1Y7 X1Y60-X1Y63

GTY Quad 134 CMAC SYSMON GTY Quad 234


HP I/O Bank 74
X0Y56-X0Y59 X0Y10 Configuration X1Y56-X1Y59
GTY Quad 133 GTY Quad 233
ILKN
X0Y52-X0Y55 HP I/O Bank 73 Configuration X1Y52-X1Y55
X0Y6
W [LN] (RCAL) J [RN] (RCAL)
GTY Quad 132 GTY Quad 232
CMAC PCIE4
X0Y48-X0Y51 HP I/O Bank 72 X1Y48-X1Y51
X0Y9 X0Y3
V [LN] I [RN]
SLR Crossing
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 ILKN
X0Y44-X0Y47 X1Y44-X1Y47
X0Y8 I X1Y5
U [LN] H [RN]
GTY Quad 130 GTY Quad 230
CMAC HP I/O Bank 70 SYSMON
X0Y40-X0Y43 X1Y40-X1Y43
X0Y7 H Configuration
T [LN] G [RN]
GTY Quad 129 GTY Quad 229
ILKN HP I/O Bank 69
X0Y36-X0Y39 Configuration X1Y36-X1Y39
X0Y4 G
S [LN] (RCAL) F [RN] (RCAL)
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 68 PCIE4
X0Y32-X0Y35 X1Y32-X1Y35
X0Y6 F X0Y2
R [LC] E [RC]
SLR Crossing
GTY Quad 127 GTY Quad 227
CMAC HP I/O Bank 67 ILKN
X0Y28-X0Y31 X1Y28-X1Y31
X0Y5 E X1Y3
Q [LC] D [RC]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y24-X0Y27 X1Y24-X1Y27
X0Y4 D Configuration
P [LC] C [RC]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y20-X0Y23 Configuration X1Y20-X1Y23
X0Y2 C
O [LC] (RCAL) B [RC] (RCAL)
GTY Quad 124 PCIE4 GTY Quad 224
CMAC HP I/O Bank 64
X0Y16-X0Y19 X0Y1 X1Y16-X1Y19
X0Y3 B
N [LC] (tandem) A [RC]
SLR Crossing
GTY Quad 123 GTY Quad 223
CMAC ILKN
X0Y12-X0Y15 HP I/O Bank 63 X1Y12-X1Y15
X0Y2 X1Y1
Z [LS] M [RS]
GTY Quad 122 GTY Quad 222
CMAC SYSMON
X0Y8-X0Y11 HP I/O Bank 62 X1Y8-X1Y11
X0Y1 Configuration
Y [LS] L [RS]
GTY Quad 121 GTY Quad 221
ILKN
X0Y4-X0Y7 HP I/O Bank 61 Configuration X1Y4-X1Y7
X0Y0
X [LS] (RCAL) K [RS] (RCAL)
GTY Quad 120 CMAC PCIE4 GTY Quad 220
HP I/O Bank 60
X0Y0-X0Y3 X0Y0 X0Y0 X1Y0-X1Y3

X15624-020817

Figure 1-132: XCVU13P Banks in FHGC2104 Package

UltraScale Device Packaging and Pinouts Send Feedback


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UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

X-Ref Target - Figure 1-133

GTY Quad 135 CMAC ILKN GTY Quad 235


HP I/O Bank 75
X0Y60-X0Y63 X0Y11 X1Y7 X1Y60-X1Y63

GTY Quad 134 CMAC HP I/O Bank 74 SYSMON GTY Quad 234
X0Y56-X0Y59 X0Y10 O Configuration X1Y56-X1Y59
GTY Quad 133 GTY Quad 233
ILKN HP I/O Bank 73
X0Y52-X0Y55 Configuration X1Y52-X1Y55
X0Y6 N
S [LN] (RCAL) J [RN] (RCAL)
GTY Quad 132 GTY Quad 232
CMAC HP I/O Bank 72
PCIE4 X1Y48-X1Y51
X0Y48-X0Y51 X0Y9 M X0Y3 I [RN]
SLR Crossing
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 ILKN
X0Y44-X0Y47 X1Y44-X1Y47
X0Y8 L X1Y5
R [LN] H [RN]
GTY Quad 130 GTY Quad 230
CMAC HP I/O Bank 70 SYSMON
X0Y40-X0Y43 X1Y40-X1Y43
X0Y7 K Configuration
Q [LN] G [RN]
GTY Quad 129 GTY Quad 229
ILKN HP I/O Bank 69
X0Y36-X0Y39 Configuration X1Y36-X1Y39
X0Y4 J
P [LN] (RCAL) F [RN] (RCAL)
GTY Quad 128 GTY Quad 228
CMAC PCIE4
X0Y32-X0Y35 HP I/O Bank 68 X1Y32-X1Y35
X0Y6 X0Y2
O [LC] E [RS]
SLR Crossing
GTY Quad 227
GTY Quad 127 CMAC HP I/O Bank 67 ILKN
X1Y28-X1Y31
X0Y28-X0Y31 X0Y5 E X1Y3
D [RS]
GTY Quad 226
GTY Quad 126 CMAC HP I/O Bank 66 SYSMON
X1Y24-X1Y27
X0Y24-X0Y27 X0Y4 D Configuration
C [RS]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y20-X0Y23 Configuration X1Y20-X1Y23
X0Y2 C
(RCAL) B [RS] (RCAL)
PCIE4 GTY Quad 224
GTY Quad 124 CMAC HP I/O Bank 64
X0Y1 X1Y16-X1Y19
X0Y16-X0Y19 X0Y3 B
(tandem) A [RS]
SLR Crossing
GTY Quad 123
CMAC HP I/O Bank 63 ILKN GTY Quad 223
X0Y12-X0Y15
X0Y2 H X1Y1 X1Y12-X1Y15
N [LS]
GTY Quad 122
CMAC HP I/O Bank 62 SYSMON GTY Quad 222
X0Y8-X0Y11
X0Y1 G Configuration X1Y8-X1Y11
M [LS]
GTY Quad 121 GTY Quad 221
ILKN HP I/O Bank 61
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 F
L [LS] (RCAL) (RCAL)
GTY Quad 120 CMAC GTY Quad 220
X0Y0-X0Y3 HP I/O Bank 60 PCIE4
K [LS] X0Y0 X0Y0 X1Y0-X1Y3

X18715-071119

Figure 1-133: XCVU13P Banks in FIGD2104 Package

UltraScale Device Packaging and Pinouts Send Feedback


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UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

X-Ref Target - Figure 1-134

GTY Quad 135 GTY Quad 235


CMAC HP I/O Bank 75 ILKN
X0Y60-X0Y63 X1Y60-X1Y63
X0Y11 K X1Y7
AA [LN] K [RN]
GTY Quad 134 GTY Quad 234
CMAC HP I/O Bank 74 SYSMON
X0Y56-X0Y59 X1Y56-X1Y59
X0Y10 J Configuration
Z [LN] J [RN]
GTY Quad 133 GTY Quad 233
ILKN HP I/O Bank 73
X0Y52-X0Y55 Configuration X1Y52-X1Y55
X0Y6 I
Y [LN] (RCAL) I [RN] (RCAL)
GTY Quad 132 GTY Quad 232
CMAC PCIE4
X0Y48-X0Y51 HP I/O Bank 72 X1Y48-X1Y51
X0Y9 X0Y3
X [LN] H [RN]
SLR Crossing
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 ILKN
X0Y44-X0Y47 X1Y44-X1Y47
X0Y8 H (Partial) X1Y5
W [LUC] G [RUC]
GTY Quad 130 GTY Quad 230
CMAC HP I/O Bank 70 SYSMON
X0Y40-X0Y43 X1Y40-X1Y43
X0Y7 G Configuration
V [LUC] F [RUC]
GTY Quad 129 GTY Quad 229
ILKN
X0Y36-X0Y39 HP I/O Bank 69 Configuration X1Y36-X1Y39
X0Y4
U [LUC] (RCAL) E [RUC] (RCAL)
GTY Quad 128 GTY Quad 228
CMAC PCIE4
X0Y32-X0Y35 HP I/O Bank 68 X1Y32-X1Y35
X0Y6 X0Y2
T [LUC] D [RUC]
SLR Crossing
GTY Quad 127 GTY Quad 227
CMAC ILKN
X0Y28-X0Y31 HP I/O Bank 67 X1Y28-X1Y31
X0Y5 X1Y3
S [LLC] C [RLC]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y24-X0Y27 X1Y24-X1Y27
X0Y4 B (Partial) Configuration
R [LLC] B [RLC]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y20-X0Y23 Configuration X1Y20-X1Y23
X0Y2 C
Q [LLC] (RCAL) A [RLC] (RCAL)
GTY Quad 124 PCIE4 GTY Quad 224
CMAC
X0Y16-X0Y19 HP I/O Bank 64 X0Y1 X1Y16-X1Y19
X0Y3
AF [LLC] (tandem) P [RLC]
SLR Crossing
GTY Quad 123 GTY Quad 223
CMAC HP I/O Bank 63 ILKN
X0Y12-X0Y15 X1Y12-X1Y15
X0Y2 F X1Y1
AE [LS] O [RS]
GTY Quad 122 GTY Quad 222
CMAC HP I/O Bank 62 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
X0Y1 E Configuration
AD [LS] N [RS]
GTY Quad 121 GTY Quad 221
ILKN HP I/O Bank 61
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 D
AC [LS] (RCAL) M [RS] (RCAL)
GTY Quad 120 GTY Quad 220
CMAC PCIE4
X0Y0-X0Y3 HP I/O Bank 60 X1Y0-X1Y3
X0Y0 X0Y0
AB [LS] L [RS]

X15625-020817

Figure 1-134: XCVU13P Banks in FLGA2577 and FSGA2577 Packages

UltraScale Device Packaging and Pinouts Send Feedback


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UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

XCVU19P Bank Diagrams


X-Ref Target - Figure 1-135

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X23017-071119

Figure 1-135: XCVU19P Banks

UltraScale Device Packaging and Pinouts Send Feedback


169
UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

X-Ref Target - Figure 1-136

+3,2%DQN +3,2%DQN +',2%DQN *7<4XDG


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X23024-071119

Figure 1-136: XCVU19P Banks in FSVA3824 Package

UltraScale Device Packaging and Pinouts Send Feedback


170
UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

X-Ref Target - Figure 1-137

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X23025-071119

Figure 1-137: XCVU19P Banks in FSVB3824 Package

UltraScale Device Packaging and Pinouts Send Feedback


171
UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

XCVU23P Bank Diagrams


X-Ref Target - Figure 1-138

CMAC GTM Dual 234


HP I/O Bank 74
X0Y1 X0Y1
GTM Dual 233
CMAC
HP I/O Bank 73 X0Y0
X0Y0
(RCAL)
GTY Quad 232
HP I/O Bank 72 HD I/O Bank 92
X0Y32-X0Y35

PCIE4C GTY Quad 231


HP I/O Bank 71
X0Y3 X0Y28-X0Y31

GTY Quad 230


HP I/O Bank 70 HD I/O Bank 90
X0Y24-X0Y27

PCIE4C GTY Quad 229


HP I/O Bank 69
X0Y2 X0Y20-X0Y23

GTY Quad 228


HP I/O Bank 68 HD I/O Bank 88
X0Y16-X0Y19

PCIE4C GTY Quad 227


HP I/O Bank 67
X0Y1 X0Y12-X0Y15

SYSMON GTY Quad 226


HP I/O Bank 66
Configuration X0Y8-X0Y11
GTY Quad 225
HP I/O Bank 65 Configuration X0Y4-X0Y7
(RCAL)
PCIE4C
GTY Quad 224
HP I/O Bank 64 X0Y0
X0Y0-X0Y3
(tandem)

X24990-122120

Figure 1-138: XCVU23P Banks

UltraScale Device Packaging and Pinouts Send Feedback


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Chapter 1: Packaging Overview

X-Ref Target - Figure 1-139

GTM Dual 234


HP I/O Bank 74 CMAC
X0Y1
L [VCCO_N] X0Y1
K [RN]
GTM Dual 233
HP I/O Bank 73 CMAC
X0Y0
K [VCCO_N] X0Y0
J [RN] (RCAL)
GTY Quad 232
HP I/O Bank 72
HD I/O Bank 92 X0Y32-X0Y33
J [VCCO_N]
I [RC]
GTY Quad 231
PCIE4C
HP I/O Bank 71 X0Y28-X0Y31
X0Y3
H [RC]
GTY Quad 230
HP I/O Bank 70 HD I/O Bank 90 X0Y24-X0Y27
G [RC]
GTY Quad 229
PCIE4C
HP I/O Bank 69 X0Y20-X0Y23
X0Y2
F [RC]
GTY Quad 228
HP I/O Bank 68
HD I/O Bank 88 X0Y16-X0Y19
F [VCCO_S]
E [RC]
GTY Quad 227
HP I/O Bank 67 PCIE4C
X0Y12-X0Y15
E [VCCO_S] X0Y1
D [RS]
GTY Quad 226
HP I/O Bank 66 SYSMON
X0Y8-X0Y11
D [VCCO_S] Configuration
C [RS]
GTY Quad 225
HP I/O Bank 65
Configuration X0Y4-X0Y7
C
B [RS] (RCAL)
PCIE4C GTY Quad 224
HP I/O Bank 64 X0Y0 X0Y0-X0Y3
(tandem) A [RS]

X24992-122120

Figure 1-139: XCVU23P Banks in VSVA1365 Package


Note: Banks with a common VCCO (such as VCCO_S or VCCO_N) should be tied to a common
on-board power supply voltage.

UltraScale Device Packaging and Pinouts Send Feedback


173
UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

X-Ref Target - Figure 1-140

GTM Dual 234


HP I/O Bank 74 CMAC
X0Y1
V X0Y1
K [RN]
GTM Dual 233
HP I/O Bank 73 CMAC
X0Y0
U X0Y0
J [RN] (RCAL)
GTY Quad 232
HP I/O Bank 72 HD I/O Bank 92
X0Y32-X0Y33
T P
I [RC]
GTY Quad 231
HP I/O Bank 71 PCIE4C
X0Y28-X0Y31
S X0Y3
H [RC]
GTY Quad 230
HP I/O Bank 70 HD I/O Bank 90
X0Y24-X0Y27
R O
G [RC]
GTY Quad 229
HP I/O Bank 69 PCIE4C
X0Y20-X0Y23
G X0Y2
F [RC]
GTY Quad 228
HP I/O Bank 68 HD I/O Bank 88
X0Y16-X0Y19
F N
E [RC]
GTY Quad 227
HP I/O Bank 67 PCIE4C
X0Y12-X0Y15
E X0Y1
D [RS]
GTY Quad 226
HP I/O Bank 66 SYSMON
X0Y8-X0Y11
D Configuration
C [RS]
GTY Quad 225
HP I/O Bank 65
Configuration X0Y4-X0Y7
C
B [RS] (RCAL)
PCIE4C GTY Quad 224
HP I/O Bank 64
X0Y0 X0Y0-X0Y3
B
(tandem) A [RS]

X24991-122120

Figure 1-140: XCVU23P Banks in FSVJ1760 Package

UltraScale Device Packaging and Pinouts Send Feedback


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Chapter 1: Packaging Overview

XCVU27P Bank Diagrams


X-Ref Target - Figure 1-141

GTM Dual 135 CMAC ILKN GTM Dual 235


HP I/O Bank 75
X0Y11 X0Y11 X1Y7 X1Y11

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HP I/O Bank 74
X0Y10 X0Y10 Configuration X1Y10
GTM Dual 133 GTM Dual 233
ILKN
X0Y9 HP I/O Bank 73 Configuration X1Y9
X0Y6
(RCAL) (RCAL)
GTM Dual 132 CMAC CMAC GTM Dual 232
HP I/O Bank 72
X0Y8 X0Y9 X1Y9 X1Y8
SLR Crossing
GTM Dual 131 CMAC ILKN GTM Dual 231
HP I/O Bank 71
X0Y7 X0Y8 X1Y5 X1Y7

GTM Dual 130 CMAC SYSMON GTM Dual 230


HP I/O Bank 70
X0Y6 X0Y7 Configuration X1Y6
GTM Dual 129 GTM Dual 229
ILKN
X0Y5 HP I/O Bank 69 Configuration X1Y5
X0Y4
(RCAL) (RCAL)
GTM Dual 128 CMAC CMAC GTM Dual 228
HP I/O Bank 68
X0Y4 X0Y6 X1Y6 X1Y4
SLR Crossing
GTY Quad 127 CMAC ILKN GTY Quad 227
HP I/O Bank 67
X0Y12-X0Y15 X0Y5 X1Y3 X1Y12-X1Y15

GTY Quad 126 CMAC SYSMON GTY Quad 226


HP I/O Bank 66
X0Y8-X0Y11 X0Y4 Configuration X1Y8-X1Y11
GTY Quad 125 GTY Quad 225
ILKN
X0Y4-X0Y7 HP I/O Bank 65 Configuration X1Y4-X1Y7
X0Y2
(RCAL) (RCAL)
PCIE4
GTY Quad 124 CMAC GTY Quad 224
HP I/O Bank 64 X0Y0
X0Y0-X0Y3 X0Y3 X1Y0-X1Y3
(tandem)
SLR Crossing
GTM Dual 123 CMAC ILKN GTM Dual 223
HP I/O Bank 63
X0Y3 X0Y2 X1Y1 X1Y3

GTM Dual 122 CMAC SYSMON GTM Dual 222


HP I/O Bank 62
X0Y2 X0Y1 Configuration X1Y2
GTM Dual 121 GTM Dual 221
ILKN
X0Y1 HP I/O Bank 61 Configuration X1Y1
X0Y0
(RCAL) (RCAL)
GTM Dual 120 CMAC CMAC GTM Dual 220
HP I/O Bank 60
X0Y0 X0Y0 X1Y0 X1Y0
X20507-072619

Figure 1-141: XCVU27P Banks

UltraScale Device Packaging and Pinouts Send Feedback


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Chapter 1: Packaging Overview

X-Ref Target - Figure 1-142

GTM Dual 135 CMAC ILKN GTM Dual 235


HP I/O Bank 75
X0Y11 X0Y11 X1Y7 X1Y11

GTM Dual 134 CMAC HP I/O Bank 74 SYSMON GTM Dual 234
X0Y10 X0Y10 O Configuration X1Y10
GTM Dual 133 GTM Dual 233
ILKN HP I/O Bank 73
X0Y9 Configuration X1Y9
X0Y6 N
S [LN] (RCAL) J [RN] (RCAL)
GTM Dual 232
GTM Dual 132 CMAC HP I/O Bank 72 CMAC
X1Y8
X0Y8 X0Y9 M X1Y9
I [RN]
SLR Crossing
GTM Dual 131 GTM Dual 231
CMAC HP I/O Bank 71 ILKN
X0Y7 X1Y7
X0Y8 L X1Y5
R [LN] H [RN]
GTM Dual 130 GTM Dual 230
CMAC HP I/O Bank 70 SYSMON
X0Y6 X1Y6
X0Y7 K Configuration
Q [LN] G [RN]
GTM Dual 129 GTM Dual 229
ILKN HP I/O Bank 69
X0Y5 Configuration X1Y5
X0Y4 J
P [LN] (RCAL) F [RN] (RCAL)
GTM Dual 128 GTM Dual 228
CMAC CMAC
X0Y4 HP I/O Bank 68 X1Y4
X0Y6 X1Y6
O [LC] E [RS]
SLR Crossing
GTY Quad 227
GTY Quad 127 CMAC HP I/O Bank 67 ILKN
X1Y12-X1Y15
X0Y12-X0Y15 X0Y5 E X1Y3
D [RS]
GTY Quad 226
GTY Quad 126 CMAC HP I/O Bank 66 SYSMON
X1Y8-X1Y11
X0Y8-X0Y11 X0Y4 D Configuration
C [RS]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y2 C
(RCAL) B [RS] (RCAL)
PCIE4 GTY Quad 224
GTY Quad 124 CMAC HP I/O Bank 64
X0Y0 X1Y0-X1Y3
X0Y0-X0Y3 X0Y3 B
(tandem) A [RS]
SLR Crossing
GTM Dual 123
CMAC HP I/O Bank 63 ILKN GTM Dual 223
X0Y3
X0Y2 H X1Y1 X1Y3
N [LS]
GTM Dual 122
CMAC HP I/O Bank 62 SYSMON GTM Dual 222
X0Y2
X0Y1 G Configuration X1Y2
M [LS]
GTM Dual 121 GTM Dual 221
ILKN HP I/O Bank 61
X0Y1 Configuration X1Y1
X0Y0 F
L [LS] (RCAL) (RCAL)
GTM Dual 120
CMAC CMAC GTM Dual 220
X0Y0 HP I/O Bank 60
X0Y0 X1Y0 X1Y0
K [LS]
X20508-072619

Figure 1-142: XCVU27P Banks in FIGD2104 Package

UltraScale Device Packaging and Pinouts Send Feedback


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Chapter 1: Packaging Overview

X-Ref Target - Figure 1-143

GTM Dual 135 GTM Dual 235


CMAC HP I/O Bank 75 ILKN
X0Y11 X1Y11
X0Y11 K X1Y7
AA [LN] K [RN]
GTM Dual 134 GTM Dual 234
CMAC HP I/O Bank 74 SYSMON
X0Y10 X1Y10
X0Y10 J Configuration
Z [LN] J [RN]
GTM Dual 133 GTM Dual 233
ILKN HP I/O Bank 73
X0Y9 Configuration X1Y9
X0Y6 I
Y [LN] (RCAL) I [RN] (RCAL)
GTM Dual 132 GTM Dual 232
CMAC CMAC
X0Y8 HP I/O Bank 72 X1Y8
X0Y9 X1Y9
X [LN] H [RN]
SLR Crossing
GTM Dual 131 GTM Dual 231
CMAC HP I/O Bank 71 ILKN
X0Y7 X1Y7
X0Y8 H (Partial) X1Y5
W [LUC] G [RUC]
GTM Dual 130 GTM Dual 230
CMAC HP I/O Bank 70 SYSMON
X0Y6 X1Y6
X0Y7 G Configuration
V [LUC] F [RUC]
GTM Dual 129 GTM Dual 229
ILKN
X0Y5 HP I/O Bank 69 Configuration X1Y5
X0Y4
U [LUC] (RCAL) E [RUC] (RCAL)
GTM Dual 128 GTM Dual 228
CMAC CMAC
X0Y4 HP I/O Bank 68 X1Y4
X0Y6 X1Y6
T [LUC] D [RUC]
SLR Crossing
GTY Quad 127 GTY Quad 227
CMAC ILKN
X0Y12-X0Y15 HP I/O Bank 67 X1Y12-X1Y15
X0Y5 X1Y3
S [LLC] C [RLC]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
X0Y4 B (Partial) Configuration
R [LLC] B [RLC]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y2 C
Q [LLC] (RCAL) A [RLC] (RCAL)
GTY Quad 124 PCIE4 GTY Quad 224
CMAC
X0Y0-X0Y3 HP I/O Bank 64 X0Y0 X1Y0-X1Y3
X0Y3
AF [LLC] (tandem) P [RLC]
SLR Crossing
GTM Dual 123 GTM Dual 223
CMAC HP I/O Bank 63 ILKN
X0Y3 X1Y3
X0Y2 F X1Y1
AE [LS] O [RS]
GTM Dual 122 GTM Dual 222
CMAC HP I/O Bank 62 SYSMON
X0Y2 X1Y2
X0Y1 E Configuration
AD [LS] N [RS]
GTM Dual 121 GTM Dual 221
ILKN HP I/O Bank 61
X0Y1 Configuration X1Y1
X0Y0 D
AC [LS] (RCAL) M [RS] (RCAL)
GTM Dual 120 GTM Dual 220
CMAC CMAC
X0Y0 HP I/O Bank 60 X1Y0
X0Y0 X1Y0
AB [LS] L [RS]
X20509-072619

Figure 1-143: XCVU27P Banks in FSGA2577 Package

UltraScale Device Packaging and Pinouts Send Feedback


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Chapter 1: Packaging Overview

XCVU29P Bank Diagrams


X-Ref Target - Figure 1-144

GTM Dual 135 CMAC ILKN GTM Dual 235


HP I/O Bank 75
X0Y11 X0Y11 X1Y7 X1Y11

GTM Dual 134 CMAC SYSMON GTM Dual 234


HP I/O Bank 74
X0Y10 X0Y10 Configuration X1Y10
GTM Dual 133 GTM Dual 233
ILKN
X0Y9 HP I/O Bank 73 Configuration X1Y9
X0Y6
(RCAL) (RCAL)
GTM Dual 132 CMAC CMAC GTM Dual 232
HP I/O Bank 72
X0Y8 X0Y9 X1Y9 X1Y8
SLR Crossing
GTM Dual 131 CMAC ILKN GTM Dual 231
HP I/O Bank 71
X0Y7 X0Y8 X1Y5 X1Y7

GTM Dual 130 CMAC SYSMON GTM Dual 230


HP I/O Bank 70
X0Y6 X0Y7 Configuration X1Y6
GTM Dual 129 GTM Dual 229
ILKN
X0Y5 HP I/O Bank 69 Configuration X1Y5
X0Y4
(RCAL) (RCAL)
GTM Dual 128 CMAC CMAC GTM Dual 228
HP I/O Bank 68
X0Y4 X0Y6 X1Y6 X1Y4
SLR Crossing
GTY Quad 127 CMAC ILKN GTY Quad 227
HP I/O Bank 67
X0Y12-X0Y15 X0Y5 X1Y3 X1Y12-X1Y15

GTY Quad 126 CMAC SYSMON GTY Quad 226


HP I/O Bank 66
X0Y8-X0Y11 X0Y4 Configuration X1Y8-X1Y11
GTY Quad 125 GTY Quad 225
ILKN
X0Y4-X0Y7 HP I/O Bank 65 Configuration X1Y4-X1Y7
X0Y2
(RCAL) (RCAL)
PCIE4
GTY Quad 124 CMAC GTY Quad 224
HP I/O Bank 64 X0Y0
X0Y0-X0Y3 X0Y3 X1Y0-X1Y3
(tandem)
SLR Crossing
GTM Dual 123 CMAC ILKN GTM Dual 223
HP I/O Bank 63
X0Y3 X0Y2 X1Y1 X1Y3

GTM Dual 122 CMAC SYSMON GTM Dual 222


HP I/O Bank 62
X0Y2 X0Y1 Configuration X1Y2
GTM Dual 121 GTM Dual 221
ILKN
X0Y1 HP I/O Bank 61 Configuration X1Y1
X0Y0
(RCAL) (RCAL)
GTM Dual 120 CMAC CMAC GTM Dual 220
HP I/O Bank 60
X0Y0 X0Y0 X1Y0 X1Y0
X20507-072619

Figure 1-144: XCVU29P Banks

UltraScale Device Packaging and Pinouts Send Feedback


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Chapter 1: Packaging Overview

X-Ref Target - Figure 1-145

GTM Dual 135 CMAC ILKN GTM Dual 235


HP I/O Bank 75
X0Y11 X0Y11 X1Y7 X1Y11

GTM Dual 134 CMAC HP I/O Bank 74 SYSMON GTM Dual 234
X0Y10 X0Y10 O Configuration X1Y10
GTM Dual 133 GTM Dual 233
ILKN HP I/O Bank 73
X0Y9 Configuration X1Y9
X0Y6 N
S [LN] (RCAL) J [RN] (RCAL)
GTM Dual 232
GTM Dual 132 CMAC HP I/O Bank 72 CMAC
X1Y8
X0Y8 X0Y9 M X1Y9
I [RN]
SLR Crossing
GTM Dual 131 GTM Dual 231
CMAC HP I/O Bank 71 ILKN
X0Y7 X1Y7
X0Y8 L X1Y5
R [LN] H [RN]
GTM Dual 130 GTM Dual 230
CMAC HP I/O Bank 70 SYSMON
X0Y6 X1Y6
X0Y7 K Configuration
Q [LN] G [RN]
GTM Dual 129 GTM Dual 229
ILKN HP I/O Bank 69
X0Y5 Configuration X1Y5
X0Y4 J
P [LN] (RCAL) F [RN] (RCAL)
GTM Dual 128 GTM Dual 228
CMAC CMAC
X0Y4 HP I/O Bank 68 X1Y4
X0Y6 X1Y6
O [LC] E [RS]
SLR Crossing
GTY Quad 227
GTY Quad 127 CMAC HP I/O Bank 67 ILKN
X1Y12-X1Y15
X0Y12-X0Y15 X0Y5 E X1Y3
D [RS]
GTY Quad 226
GTY Quad 126 CMAC HP I/O Bank 66 SYSMON
X1Y8-X1Y11
X0Y8-X0Y11 X0Y4 D Configuration
C [RS]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y2 C
(RCAL) B [RS] (RCAL)
PCIE4 GTY Quad 224
GTY Quad 124 CMAC HP I/O Bank 64
X0Y0 X1Y0-X1Y3
X0Y0-X0Y3 X0Y3 B
(tandem) A [RS]
SLR Crossing
GTM Dual 123
CMAC HP I/O Bank 63 ILKN GTM Dual 223
X0Y3
X0Y2 H X1Y1 X1Y3
N [LS]
GTM Dual 122
CMAC HP I/O Bank 62 SYSMON GTM Dual 222
X0Y2
X0Y1 G Configuration X1Y2
M [LS]
GTM Dual 121 GTM Dual 221
ILKN HP I/O Bank 61
X0Y1 Configuration X1Y1
X0Y0 F
L [LS] (RCAL) (RCAL)
GTM Dual 120
CMAC CMAC GTM Dual 220
X0Y0 HP I/O Bank 60
X0Y0 X1Y0 X1Y0
K [LS]
X20508-072619

Figure 1-145: XCVU29P Banks in FIGD2104 Package

UltraScale Device Packaging and Pinouts Send Feedback


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UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

X-Ref Target - Figure 1-146

GTM Dual 135 GTM Dual 235


CMAC HP I/O Bank 75 ILKN
X0Y11 X1Y11
X0Y11 K X1Y7
AA [LN] K [RN]
GTM Dual 134 GTM Dual 234
CMAC HP I/O Bank 74 SYSMON
X0Y10 X1Y10
X0Y10 J Configuration
Z [LN] J [RN]
GTM Dual 133 GTM Dual 233
ILKN HP I/O Bank 73
X0Y9 Configuration X1Y9
X0Y6 I
Y [LN] (RCAL) I [RN] (RCAL)
GTM Dual 132 GTM Dual 232
CMAC CMAC
X0Y8 HP I/O Bank 72 X1Y8
X0Y9 X1Y9
X [LN] H [RN]
SLR Crossing
GTM Dual 131 GTM Dual 231
CMAC HP I/O Bank 71 ILKN
X0Y7 X1Y7
X0Y8 H (Partial) X1Y5
W [LUC] G [RUC]
GTM Dual 130 GTM Dual 230
CMAC HP I/O Bank 70 SYSMON
X0Y6 X1Y6
X0Y7 G Configuration
V [LUC] F [RUC]
GTM Dual 129 GTM Dual 229
ILKN
X0Y5 HP I/O Bank 69 Configuration X1Y5
X0Y4
U [LUC] (RCAL) E [RUC] (RCAL)
GTM Dual 128 GTM Dual 228
CMAC CMAC
X0Y4 HP I/O Bank 68 X1Y4
X0Y6 X1Y6
T [LUC] D [RUC]
SLR Crossing
GTY Quad 127 GTY Quad 227
CMAC ILKN
X0Y12-X0Y15 HP I/O Bank 67 X1Y12-X1Y15
X0Y5 X1Y3
S [LLC] C [RLC]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
X0Y4 B (Partial) Configuration
R [LLC] B [RLC]
GTY Quad 125 GTY Quad 225
ILKN HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y2 C
Q [LLC] (RCAL) A [RLC] (RCAL)
GTY Quad 124 PCIE4 GTY Quad 224
CMAC
X0Y0-X0Y3 HP I/O Bank 64 X0Y0 X1Y0-X1Y3
X0Y3
AF [LLC] (tandem) P [RLC]
SLR Crossing
GTM Dual 123 GTM Dual 223
CMAC HP I/O Bank 63 ILKN
X0Y3 X1Y3
X0Y2 F X1Y1
AE [LS] O [RS]
GTM Dual 122 GTM Dual 222
CMAC HP I/O Bank 62 SYSMON
X0Y2 X1Y2
X0Y1 E Configuration
AD [LS] N [RS]
GTM Dual 121 GTM Dual 221
ILKN HP I/O Bank 61
X0Y1 Configuration X1Y1
X0Y0 D
AC [LS] (RCAL) M [RS] (RCAL)
GTM Dual 120 GTM Dual 220
CMAC CMAC
X0Y0 HP I/O Bank 60 X1Y0
X0Y0 X1Y0
AB [LS] L [RS]
X20509-072619

Figure 1-146: XCVU29P Banks in FSGA2577 Package

UltraScale Device Packaging and Pinouts Send Feedback


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Chapter 1: Packaging Overview

XCVU31P Bank Diagrams


X-Ref Target - Figure 1-147

*7<4XDG 3&,(& 3&,(& *7<4XDG


+3,2%DQN
;<;< ;< ;< ;<;<

*7<4XDG &0$& 6<6021 *7<4XDG


+3,2%DQN
;<;< ;< &RQILJXUDWLRQ ;<;<

*7<4XDG *7<4XDG
&0$&
;<;< +3,2%DQN &RQILJXUDWLRQ ;<;<
;<
5&$/ 5&$/

*7<4XDG 3&,(& 3&,(& *7<4XDG


+3,2%DQN ;<
;<;< ;< ;<;<
WDQGHP

+%0%DQN

X19796-072619

Figure 1-147: XCVU31P Banks


X-Ref Target - Figure 1-148

*7<4XDG *7<4XDG
3&,(& +3,2%DQN 3&,(&
;<;< ;<;<
;< ( ;<
+>/@ '>5@
*7<4XDG *7<4XDG
&0$& +3,2%DQN 6<6021
;<;< ;<;<
;< ' &RQILJXUDWLRQ
*>/@ &>5@
*7<4XDG *7<4XDG
&0$& +3,2%DQN
;<;< &RQILJXUDWLRQ ;<;<
;< &
)>/@ 5&$/ %>5@ 5&$/
*7<4XDG 3&,(& *7<4XDG
3&,(& +3,2%DQN
;<;< ;< ;<;<
;< % WDQGHP
(>/@ $>5@

+%0%DQN

X19797-072619

Figure 1-148: XCVU31P Banks in FSVH1924 Package

UltraScale Device Packaging and Pinouts Send Feedback


181
UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

XCVU33P Bank Diagrams


X-Ref Target - Figure 1-149

*7<4XDG 3&,(& 3&,(& *7<4XDG


+3,2%DQN
;<;< ;< ;< ;<;<

*7<4XDG &0$& 6<6021 *7<4XDG


+3,2%DQN
;<;< ;< &RQILJXUDWLRQ ;<;<

*7<4XDG *7<4XDG
&0$&
;<;< +3,2%DQN &RQILJXUDWLRQ ;<;<
;<
5&$/ 5&$/

*7<4XDG 3&,(& 3&,(& *7<4XDG


+3,2%DQN ;<
;<;< ;< ;<;<
WDQGHP

+%0%DQN +%0%DQN

X19798-072619

Figure 1-149: XCVU33P Banks


X-Ref Target - Figure 1-150

*7<4XDG *7<4XDG
3&,(& +3,2%DQN 3&,(&
;<;< ;<;<
;< * ;<
/>/6@ '>56@
*7<4XDG *7<4XDG
&0$& +3,2%DQN 6<6021
;<;< ;<;<
;< ' &RQILJXUDWLRQ
.>/6@ &>56@
*7<4XDG *7<4XDG
&0$& +3,2%DQN
;<;< &RQILJXUDWLRQ ;<;<
;< &
->/6@ 5&$/ %>56@ 5&$/
*7<4XDG 3&,(& *7<4XDG
3&,(& +3,2%DQN
;<;< ;< ;<;<
;< % WDQGHP
,>/6@ $>56@

+%0%DQN +%0%DQN

X19799-072619

Figure 1-150: XCVU33P Banks in FSVH2104 Package

UltraScale Device Packaging and Pinouts Send Feedback


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Chapter 1: Packaging Overview

XCVU35P and XCVU45P Bank Diagrams


X-Ref Target - Figure 1-151

*7<4XDG
*7<4XDG &0$&
&0$& ,/.1
,/.1 *7<4XDG
*7<4XDG
+3,2%DQN
+3,2%DQN
;<;<
;<;< ;<
;< ;<
;< ;<;<
;<;<

*7<4XDG
*7<4XDG &0$&
&0$& 6<6021
6<6021 *7<4XDG
*7<4XDG
+3,2%DQN
+3,2%DQN
;<;<
;<;< ;<
;< &RQILJXUDWLRQ
&RQILJXUDWLRQ ;<;<
;<;<

*7<4XDG
*7<4XDG *7<4XDG
*7<4XDG
,/.1
,/.1
;<;<
;<;< +3,2%DQN
+3,2%DQN &RQILJXUDWLRQ
&RQILJXUDWLRQ ;<;<
;<;<
;<
;<
5&$/
5&$/ 5&$/
5&$/

*7<4XDG
*7<4XDG &0$&
&0$& 3&,(
3&,( *7<4XDG
*7<4XDG
+3,2%DQN
+3,2%DQN
;<;<
;<;< ;<
;< ;<
;< ;<;<
;<;<

6/5&URVVLQJ
6/5&URVVLQJ

*7<4XDG
*7<4XDG 3&,(&
3&,( 3&,(&
3&,( *7<4XDG
*7<4XDG
+3,2%DQN
+3,2%DQN
;<;<
;<;< ;<
;< ;<
;< ;<;<
;<;<

*7<4XDG
*7<4XDG &0$&
&0$& 6<6021
6<6021 *7<4XDG
*7<4XDG
+3,2%DQN
+3,2%DQN
;<;<
;<;< ;<
;< &RQILJXUDWLRQ
&RQILJXUDWLRQ ;<;<
;<;<

*7<4XDG
*7<4XDG *7<4XDG
*7<4XDG
&0$&
&0$&
;<;<
;<;< +3,2%DQN
+3,2%DQN &RQILJXUDWLRQ
&RQILJXUDWLRQ ;<;<
;<;<
;<
;<
5&$/
5&$/ 5&$/
5&$/
3&,(
3&,(&
*7<4XDG
*7<4XDG 3&,(&
3&,( *7<4XDG
*7<4XDG
+3,2%DQN
+3,2%DQN ;<
;<
;<;<
;<;< ;<
;< ;<;<
;<;<
WDQGHP
WDQGHP

+%0%DQN
+%0%DQN +%0%DQN
+%0%DQN

X19800-072619

Figure 1-151: XCVU35P and XCVU45P Banks

UltraScale Device Packaging and Pinouts Send Feedback


183
UG575 (v1.19) May 10, 2023
Chapter 1: Packaging Overview

X-Ref Target - Figure 1-152

*7<4XDG *7<4XDG
&0$& +3,2%DQN ,/.1
;<;< ;<;<
;< . ;<
3>/1@ +>51@
*7<4XDG *7<4XDG
&0$& +3,2%DQN 6<6021
;<;< ;<;<
;< - &RQILJXUDWLRQ
2>/1@ *>51@
*7<4XDG *7<4XDG
,/.1 +3,2%DQN
;<;< &RQILJXUDWLRQ ;<;<
;< ,
1>/1@ 5&$/ )>51@ 5&$/
*7<4XDG *7<4XDG
&0$& +3,2%DQN 3&,(
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Figure 1-152: XCVU35P and XCVU45P Banks in FSVH2104 Package

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X-Ref Target - Figure 1-153

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Figure 1-153: XCVU35P and XCVU45P Banks in FSVH2892 Package

UltraScale Device Packaging and Pinouts Send Feedback


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Chapter 1: Packaging Overview

XCVU37P and XCVU47P Bank Diagrams


X-Ref Target - Figure 1-154

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X19803-072619

Figure 1-154: XCVU37P and XCVU47P Banks

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X-Ref Target - Figure 1-155

GTY Quad 135 GTY Quad 235


CMAC HP I/O Bank 75 ILKN
X0Y44-X0Y47 X1Y44-X1Y47
X0Y7 N X1Y3
X [LN] L [RN]
GTY Quad 134 GTY Quad 234
CMAC HP I/O Bank 74 SYSMON
X0Y40-X0Y43 X1Y40-X1Y43
X0Y6 M Configuration
W [LN] K [RN]
GTY Quad 133 GTY Quad 233
ILKN HP I/O Bank 73
X0Y36-X0Y39 Configuration X1Y36-X1Y39
X0Y2 L
V [LN] (RCAL) J [RN] (RCAL)
GTY Quad 132 GTY Quad 232
CMAC HP I/O Bank 72 PCIE4
X0Y32-X0Y35 X1Y32-X1Y35
X0Y5 K X0Y1
U [LN] I [RN]
SLR Crossing
GTY Quad 131 GTY Quad 231
CMAC HP I/O Bank 71 ILKN
X0Y28-X0Y31 X1Y28-X1Y31
X0Y4 J X1Y1
T [LC] H [RC]
GTY Quad 130 GTY Quad 230
CMAC HP I/O Bank 70 SYSMON
X0Y24-X0Y27 X1Y24-X1Y27
X0Y3 I Configuration
S [LC] G [RC]
GTY Quad 129 GTY Quad 229
ILKN HP I/O Bank 69
X0Y20-X0Y23 Configuration X1Y20-X1Y23
X0Y0 G
R [LC] (RCAL) F [RC] (RCAL)
GTY Quad 128 GTY Quad 228
CMAC HP I/O Bank 68 PCIE4
X0Y16-X0Y19 X1Y16-X1Y19
X0Y2 F X0Y0
Q [LC] E [RC]
SLR Crossing
GTY Quad 127 GTY Quad 227
PCIE4C HP I/O Bank 67 PCIE4C
X0Y12-X0Y15 X1Y12-X1Y15
X0Y1 E X1Y1
P [LS] D [RS]
GTY Quad 126 GTY Quad 226
CMAC HP I/O Bank 66 SYSMON
X0Y8-X0Y11 X1Y8-X1Y11
X0Y1 D Configuration
O [LS] C [RS]
GTY Quad 125 GTY Quad 225
CMAC HP I/O Bank 65
X0Y4-X0Y7 Configuration X1Y4-X1Y7
X0Y0 C
N [LS] (RCAL) B [RS] (RCAL)
GTY Quad 124 3&,(& GTY Quad 224
PCIE4C HP I/O Bank 64
X0Y0-X0Y3 ;< X1Y0-X1Y3
X0Y0 B WDQGHP
M [LS] A [RS]

HBM Bank 43 HBM Bank 83

X19804-121620

Figure 1-155: XCVU37P and XCVU47P Banks in FSVH2892 Package

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XCVU57P Bank Diagrams


X-Ref Target - Figure 1-156

GTM Dual 135 CMAC ILKN GTM Dual 235


HP I/O Bank 75
X0Y7 X0Y7 X1Y3 X1Y7

GTM Dual 134 CMAC SYSMON GTM Dual 234


HP I/O Bank 74
X0Y6 X0Y6 Configuration X1Y6
GTM Dual 133 GTM Dual 233
ILKN
X0Y5 HP I/O Bank 73 Configuration X1Y5
X0Y2
(RCAL) (RCAL)
GTM Dual 132 CMAC CMAC GTM Dual 232
HP I/O Bank 72
X0Y4 X0Y5 X0Y5 X1Y4
SLR Crossing
GTM Dual 131 CMAC ILKN GTM Dual 231
HP I/O Bank 71
X0Y3 X0Y4 X1Y1 X1Y3

GTM Dual 130 CMAC SYSMON GTM Dual 230


HP I/O Bank 70
X0Y2 X0Y3 Configuration X1Y2
GTM Dual 129 GTM Dual 229
ILKN
X0Y1 HP I/O Bank 69 Configuration X1Y1
X0Y0
(RCAL) (RCAL)
GTM Dual 128 CMAC CMAC GTM Dual 228
HP I/O Bank 68
X0Y0 X0Y2 X1Y2 X1Y0
SLR Crossing
GTY Quad 127 PCIE4 PCIE4 GTY Quad 227
HP I/O Bank 67
X0Y12-X0Y15 X0Y1 X1Y1 X1Y12-X1Y15

GTY Quad 126 CMAC SYSMON GTY Quad 226


HP I/O Bank 66
X0Y8-X0Y11 X0Y1 Configuration X1Y8-X1Y11
GTY Quad 125 GTY Quad 225
CMAC
X0Y4-X0Y7 HP I/O Bank 65 Configuration X1Y4-X1Y7
X0Y0
(RCAL) (RCAL)
PCIE4
GTY Quad 124 PCIE4 GTY Quad 224
HP I/O Bank 64 X1Y0
X0Y0-X0Y3 X0Y0 X1Y0-X1Y3
(tandem)

HBM Bank 43 HBM Bank 83

X24993-050923

Figure 1-156: XCVU57P Banks

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X-Ref Target - Figure 1-157

GTM Dual 135 CMAC HP I/O Bank 75 ILKN GTM Dual 235
X0Y7 X1Y7
X [LN] X0Y7 I X1Y3 L [RN]
GTM Dual 134 CMAC HP I/O Bank 74 SYSMON GTM Dual 234
X0Y6 X1Y6
W [LN] X0Y6 J Configuration K [RN]
GTM Dual 133 ILKN HP I/O Bank 73 GTM Dual 233
X0Y5 Configuration X1Y5
V [LN] (RCAL) X0Y2 K J [RN] (RCAL)
GTM Dual 132 CMAC HP I/O Bank 72 CMAC GTM Dual 232
X0Y4 X1Y4
U [LN] X0Y5 N X0Y5 I [RN]
SLR Crossing
GTM Dual 131 CMAC HP I/O Bank 71 ILKN GTM Dual 231
X0Y3 X1Y3
T [LC] X0Y4 M X1Y1 H [RC]
GTM Dual 130 CMAC HP I/O Bank 70 SYSMON GTM Dual 230
X0Y2 X1Y2
S [LC] X0Y3 L Configuration G [RC]
GTM Dual 129 ILKN HP I/O Bank 69 GTM Dual 229
X0Y1 Configuration X1Y1
R [LC] (RCAL) X0Y0 G F [RC] (RCAL)
GTM Dual 128 CMAC HP I/O Bank 68 CMAC GTM Dual 228
X0Y0 X1Y0
Q [LC] X0Y2 F X1Y2 E [RC]
SLR Crossing
GTY Quad 127 PCIE4 HP I/O Bank 67 PCIE4 GTY Quad 227
X0Y12-X0Y15 X1Y12-X1Y15
P [LS] X0Y1 E X1Y1 D [RS]
GTY Quad 126 CMAC HP I/O Bank 66 SYSMON GTY Quad 226
X0Y8-X0Y11 X1Y8-X1Y11
O [LS] X0Y1 D Configuration C [RS]
GTY Quad 125 CMAC HP I/O Bank 65 GTY Quad 225
X0Y4-X0Y7 Configuration X1Y4-X1Y7
N [LS] (RCAL) X0Y0 C B [RS] (RCAL)
GTY Quad 124 PCIE4 HP I/O Bank 64 PCIE4 GTY Quad 224
X0Y0-X0Y3 X1Y0 X1Y0-X1Y3
M [LS] X0Y0 B (tandem) A [RS]

HBM Bank 43 HBM Bank 83

X24994-122120

Figure 1-157: XCVU57P Banks in FSVK2892 Package

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Chapter 2

Package Files

About ASCII Package Files


The ASCII package files for each package include a comma-separated-values (CSV) version
and a text version optimized for a browser or text editor in fixed-width fonts. The
information in each of the files includes:

• Device/Package name (family-device-package), with date and time of creation


• Seven columns containing data for each pin:

° Pin—Pin location on the package.

° Pin Name—The name of the assigned pin.

° Memory Byte Group—Memory byte group between 0 and 3 split into upper (U) and
lower (L) halves. For more information on the memory byte group, see the
UltraScale Architecture FPGAs Memory IP Product Guide (PG150).

° Bank—Bank number.

° I/O Type—CONFIG, HD, HR, HP, or GT (GTH, GTY, or GTM) depending on the I/O
type. For more information on the I/O type, see the UltraScale Architecture
SelectIO Resources User Guide (UG571).

° Super Logic Region—Number corresponding to the super logic region (SLR) in the
devices implemented with stacked silicon interconnect (SSI) technology.

° No-Connect—This list of devices is used for migration between devices that have
the same package size and are not connected at that specific pin.
• Total number of pins in the package.

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Chapter 2: Package Files

Package Specifications Designations


Package specifications are designated as evaluation only, engineering sample, or
production. Each designation is defined as follows.

Evaluation Only

These package specifications are based on initial device specifications, package routability
analysis and mechanical package construction. Package specifications with this designation
are not stable and package pinouts are likely to change and these specifications should
only be used for initial system level design feasibility.

Engineering Sample

These package specifications are based on a released package design and validated with ES
engineering sample (ES) devices. Package specifications with this designation are
considered stable, however some pinout and mechanical specifications might change prior
to the production release of the particular device. Package pinouts with this designation are
to be used for PCB and Vivado designs using ES devices.

Production

These package specifications are released coincident with production release of a particular
device. Customers receive formal notification of any subsequent changes.

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Chapter 2: Package Files

ASCII Pinout Files


Links to the ASCII pinout information by device/package are listed in Table 2-1. The pinouts
of XQ devices are identical to the pinouts of their equivalent XC devices in footprint
compatible package. Links in this table to XQ devices open the XC version of the pinout file.
For example, the link to RBA676-XQKU040 opens the FBVA676-XCKU040 pinout file.

Download all available Kintex UltraScale, Kintex UltraScale+, Artix UltraScale+, Virtex
UltraScale, and Virtex UltraScale+ FPGA package/device/pinout files at:

www.xilinx.com/support/package-pinout-files/ultrascale-pkgs.html

Note: All package files are ASCII files in TXT and CSV file format. Only the available files listed in
Table 2-1 are linked and consolidated in this ZIP file.

www.xilinx.com/support/packagefiles/usapackages/usaall.zip

IMPORTANT: With the exception of InFO packages (package names begin with U), all packages are
available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC, and
the third digit in the package name is Q (for example: FFQA1156).

Table 2-1: Package/Device Pinout Files


Package Device
XCAU10P XCAU15P
UBVA368 Engineering Engineering
Sample Sample
XCAU10P XCAU15P XAAU10P XAAU15P
SBVB484
Production Production Production Production
XCAU7P XAAU7P
SBVC484 Engineering Engineering
Sample Sample
XCKU035 XCKU040
FBVA676
Production Production
XCKU3P XCKU5P
FFVA676
Production Production
XCAU10P XCAU15P XCAU20P XCAU25P XCKU3P XCKU5P
FFVB676
Production Production Production Production Production Production
XQKU5P
FFRB676
Production
XQKU040
RBA676
Production

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Chapter 2: Package Files

Table 2-1: Package/Device Pinout Files (Cont’d)


Package Device
XCKU035 XCKU040
SFVA784
Production Production
XCAU20P XCAU25P XCKU3P XCKU5P
SFVB784
Production Production Production Production
XQKU5P
SFRB784
Production
XCKU035 XCKU040
FBVA900
Production Production
XCKU3P XCKU5P XCKU11P
FFVD900
Production Production Production
XCKU9P XCKU13P
FFVE900
Production Production
XCKU025 XCKU035 XCKU040 XCKU060 XCKU095 XCKU11P XCKU15P
FFVA1156
Production Production Production Production Production Production Production
XQKU15P
FFRA1156
Production
XQKU040 XQKU060 XQKU095
RFA1156
Production Production Production
XCVU23P
VSVA1365
Production
XCKU060
FFVA1517
Production
XCKU085 XCKU115
FLVA1517
Production Production
XCKU095 XCVU065 XCVU080 XCVU095 XCVU3P
FFVC1517
Production Production Production Production Production
XQVU3P
FFRC1517
Production
XCVU080 XCVU095
FFVD1517
Production Production
XCKU115 XCVU125
FLVD1517
Production Production
XCKU11P XCKU15P
FFVE1517
Production Production
XQKU15P
FFRE1517
Production

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Chapter 2: Package Files

Table 2-1: Package/Device Pinout Files (Cont’d)


Package Device
XQKU115
RLD1517
Production
XCKU15P
FFVA1760
Production
XCKU095 XCVU080 XCVU095
FFVB1760
Production Production Production
XCKU085 XCKU115 XCVU125
FLVB1760
Production Production Production
XCKU15P
FFVE1760
Production
XCVU19P
FFVJ1760
Production
XCVU23P
FSVJ1760
Production
XCKU115
FLVD1924
Production
XCKU085 XCKU115
FLVF1924
Production Production
XCVU11P
FLGF1924
Production
XQKU115
RLF1924
Production
XCVU31P
FSVH1924
Production
XCVU080 XCVU095
FFVA2104
Production Production
XCKU115 XCVU125 XCVU5P XCVU7P
FLVA2104
Production Production Production Production
XQVU7P
FLRA2104
Production
XCVU9P
FLGA2104
Production
XCVU13P
FHGA2104
Production
XCKU095 XCVU080 XCVU095 XCKU19P
FFVB2104
Production Production Production Production

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Chapter 2: Package Files

Table 2-1: Package/Device Pinout Files (Cont’d)


Package Device
XCKU115 XCVU125 XCVU5P XCVU7P
FLVB2104
Production Production Production Production
XQVU7P
FLRB2104
Production
XCVU160 XCVU190 XCVU9P XCVU11P
FLGB2104
Production Production Production Production
XCVU13P
FHGB2104
Production
XCVU095
FFVC2104
Production
XCVU125 XCVU5P XCVU7P
FLVC2104
Production Production Production
XCVU160 XCVU190 XCVU9P XCVU11P
FLGC2104
Production Production Production Production
XQVU11P
FLRC2104
Production
XCVU13P
FHGC2104
Production
XCVU13P XCVU27P XCVU29P
FIGD2104
Production Production Production
XCVU9P XCVU11P
FSGD2104
Production Production
XCVU33P XCVU35P XCVU45P
FSVH2104
Production Production Production
XCVU440
FLGB2377
Production
XCVU190 XCVU9P XCVU11P XCVU13P
FLGA2577
Production Production Production Production
XCVU13P XCVU27P XCVU29P
FSGA2577
Production Production Production
XCVU440
FLGA2892
Production
XCVU35P XCVU37P XCVU47P
FSVH2892
Production Production Production
XCVU57P
FSVK2892
Production

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Chapter 2: Package Files

Table 2-1: Package/Device Pinout Files (Cont’d)


Package Device
XCVU19P
FSVA3824
Production
XCVU19P
FSVB3824
Production

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Chapter 3

Device Diagrams

Summary
The diagrams in this chapter show a top-view perspective of the package pinout of each
UltraScale and UltraScale+ device/package combination. Table 3-1 through Table 3-4
contain cross references to the device diagrams. The I/O-bank diagram shows the location
of each user I/O and GTH/GTY transceiver and the respective bank or GT quad. The
configuration-power diagram shows the location of every power pin and dedicated as well
as multi-function configuration pin in the package. See Package Specifications
Designations in Chapter 2 for definitions of Evaluation Only, Engineering Sample, and
Production device diagrams.

IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC, and the third digit in the package name is Q (for example: FFQA1156).

Table 3-1: Cross-Reference to Kintex UltraScale and XQ Kintex UltraScale Device Diagrams by
Package
Package Footprint Compatible Devices Package Status
XCKU035 XCKU040
FBVA676 Production
page 204 page 204
XQKU040
RBA676 Production
page 204
XCKU035 XCKU040
SFVA784 Production
page 206 page 206
XCKU035 XCKU040
FBVA900 Production
page 208 page 208
XCKU025 XCKU035 XCKU040 XCKU060 XCKU095
FFVA1156 Production
page 210 page 212 page 214 page 216 page 218
XQKU040 XQKU060 XQKU095
RFA1156 Production
page 214 page 216 page 218
XCKU060
FFVA1517 Production
page 220
XCKU085 XCKU115
FLVA1517 Production
page 222 page 222

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Chapter 3: Device Diagrams

Table 3-1: Cross-Reference to Kintex UltraScale and XQ Kintex UltraScale Device Diagrams by
Package (Cont’d)
Package Footprint Compatible Devices Package Status
XCKU095
FFVC1517 Production
page 224

XCKU115
FLVD1517 Production
page 226

XQKU115
RLD1517 Production
page 226

XCKU095
FFVB1760 Production
page 228

XCKU085 XCKU115
FLVB1760 Production
page 230 page 232

XCKU115
FLVD1924 Production
page 234

XCKU085 XCKU115
FLVF1924 Production
page 236 page 238

XQKU115
RLF1924 Production
page 238

XCKU115
FLVA2104 Production
page 240

XCKU095
FFVB2104 Production
page 242

XCKU115
FLVB2104 Production
page 244

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Chapter 3: Device Diagrams

Table 3-2: Cross-Reference to Virtex UltraScale Device Diagrams by Package


Package Footprint Compatible Devices Package Status
XCVU065 XCVU080 XCVU095
FFVC1517 Production
page 246 page 248 page 248
XCVU080 XCVU095
FFVD1517 Production
page 250 page 250
XCVU125
FLVD1517 Production
page 252
XCVU080 XCVU095
FFVB1760 Production
page 254 page 254
XCVU125
FLVB1760 Production
page 256
XCVU080 XCVU095
FFVA2104 Production
page 258 page 258
XCVU125
FLVA2104 Production
page 260
XCVU080 XCVU095
FFVB2104 Production
page 262 page 262
XCVU125
FLVB2104 Production
page 264
XCVU160 XCVU190
FLGB2104 Production
page 266 page 266
XCVU095
FFVC2104 Production
page 268
XCVU125
FLVC2104 Production
page 270
XCVU160 XCVU190
FLGC2104 Production
page 272 page 272
XCVU440
FLGB2377 Production
page 274
XCVU190
FLGA2577 Production
page 276
XCVU440
FLGA2892 Production
page 278

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Table 3-3: Cross-Reference to Kintex UltraScale+ and XQ Kintex UltraScale+ Device Diagrams by
Package
Package Footprint Compatible Devices Package Status
XCKU3P XCKU5P
FFVA676 Production
page 300 page 300
XCKU3P XCKU5P
FFVB676 Production
page 302 page 302
XQKU5P
FFRB676 Production
page 302
XCKU3P XCKU5P
SFVB784 Production
page 304 page 304
XQKU5P
SFRB784 Production
page 304
XCKU3P XCKU5P XCKU11P
FFVD900 Production
page 306 page 306 page 308
XCKU9P XCKU13P
FFVE900 Production
page 310 page 312
XCKU11P XCKU15P
FFVA1156 Production
page 314 page 316
XQKU15P
FFRA1156 Production
page 316
XCKU11P XCKU15P
FFVE1517 Production
page 318 page 320
XQKU15P
FFRE1517 Production
page 320
XCKU15P
FFVA1760 Production
page 322
XCKU15P
FFVE1760 Production
page 324
XCKU19P
FFVJ1760 Production
page 326
XCKU19P
FFVB2104 Production
page 328

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Chapter 3: Device Diagrams

Table 3-4: Cross-Reference to Virtex UltraScale+ and XQ Virtex UltraScale+ Device Diagrams by
Package
Package Footprint Compatible Devices Package Status
XCVU23P
VSVA1365 Production
page 395
XCVU3P
FFVC1517 Production
page 331
XQVU3P
FFRC1517 Production
page 331
XCVU23P
FSVJ1760 Production
page 333
XCVU11P
FLGF1924 Production
page 335
XCVU31P
FSVH1924 Production
page 337
XCVU5P XCVU7P
FLVA2104 Production
page 339 page 339
XQVU7P
FFRA2104 Production
page 339
XCVU9P
FLGA2104 Production
page 341
XCVU13P
FHGA2104 Production
page 343
XCVU5P XCVU7P
FLVB2104 Production
page 345 page 345
XQVU7P
FLRB2104 Production
page 345
XCVU9P XCVU11P
FLGB2104 Production
page 347 page 349
XCVU13P
FHGB2104 Production
page 351
XCVU5P XCVU7P
FLVC2104 Production
page 353 page 353
XCVU9P XCVU11P
FLGC2104 Production
page 355 page 357
XQVU11P
FLRC2104 Production
page 357
XCVU13P
FHGC2104 Production
page 359

UltraScale Device Packaging and Pinouts Send Feedback


201
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

Table 3-4: Cross-Reference to Virtex UltraScale+ and XQ Virtex UltraScale+ Device Diagrams by
Package (Cont’d)
Package Footprint Compatible Devices Package Status
XCVU9P XCVU11P
FSGD2104 Production
page 361 page 363
XCVU13P
FIGD2104 Production
page 365
XCVU27P XCVU29P
FIGD2104 Production
page 367 page 369
XCVU33P XCVU35P XCVU45P
FSVH2104 Production
page 371 page 373 page 373
XCVU9P XCVU11P XCVU13P
FLGA2577 Production
page 375 page 377 page 379
XCVU13P
FSGA2577 Production
page 379
XCVU27P XCVU29P
FSGA2577 Production
page 381 page 383
XCVU35P XCVU37P XCVU45P XCVU47P
FSVH2892 Production
page 385 page 387 page 385 page 387
XCVU57P
FSVK2892 Production
page 389
XCVU19P
FSVA3824 Production
page 391
XCVU19P
FSVB3824 Production
page 393

UltraScale Device Packaging and Pinouts Send Feedback


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UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

Table 3-5: Cross-Reference to Artix UltraScale+ Device Diagrams by Package


Package Footprint Compatible Devices Package Status
XCAU10P XCAU15P
UBVA368 Engineering Sample
page 298 page 299
XCAU10P XCAU15P XAAU10P XAAU15P
SBVB484 Production
page 290 page 292 page 290 page 292
XCAU7P XAAU7P
SBVC484 Engineering Sample
page 280 page 280
XCAU10P XCAU15P XAAU10P XAAU15P
Production
page 282 page 284 page 282 page 284
FFVB676
XCAU20P XCAU25P
Production
page 286 page 288
XCAU20P XCAU25P
SFVB784 Production
page 294 page 296

UltraScale Device Packaging and Pinouts Send Feedback


203
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FBVA676 Package–XCKU035 and XCKU040 and


RBA676 Package–XQKU040
X-Ref Target - Figure 3-1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

V C 46

VC 46
3
A 3 3 18 6 6 4 2 15 15 16 8 7 7 1 1 A

C
3

O
227 227

V C 66

V C 46
2
B 2 2 18 16 5 4 2 17 18 16 8 9 9 3 3 6 B

C
2

O
227 227

V C 66

V C 46
1
C 15 15 16 5 3 1 17 18 14 13 10 10 4 5 6 C

C
1

O
227

VC 46
0
D 1 1 17 S 13 14 3 1 S 14 13 12 12 4 5 2 2 D

C
0

O
227 227

V C 66

V C 45
E 0 0 17 13 14 12 12 S S 23 23 11 11 S 7 7 E

C
O

O
227

VC 66

V C 46
3 1
F 20 20 22 11 10 10 8 20 21 21 19 10 10 S 9 F

C
3 1

O
226 227

V C 66

VC 4 6
G 3 3 24 24 22 11 7 8 22 20 19 15 17 17 12 9 8 G

C
O

O
226

VC 66

VC 4 5
2 0
H 19 19 23 S 9 7 22 24 24 15 18 13 13 12 8 H

C
2 0

O
226 227

VC 66

VC 45
J 2 2 21 21 23 9 23 23 18 14 11 11 4 J

C
O

O
226

V C 45
1 1
K 19 20 20 16 14 4 K

C
1 1

O
226 226

V C 45
L 1 1 19 21 22 16 S 3 6 L

C
O
226

V C 45
0 0
M 21 22 24 5 3 6 2 M

C
0 0

O
226 226

V C 45
N 0 0 S 24 5 1 1 2 N

C
O
226
3 1
P 3
225
1
225
21 21 23 20 17 17 18 15 P

VC 44
R 3 3 19 23 20 16 16 18 15 R

C
O
225

VC 44
2 0
T 19 22 22 14 13 13 S T

C
2 0

O
225 225

VC 4 4
U 2 2 24 24 14 11 S 10 U

C
O
225

V C 44
1 1
V 22 22 10 10 S 12 12 11 10 V

C
1 1

O
225 224

VC 64

VC 44
W 1 1 23 23 24 24 10 10 8 7 9 9 12 8 7 7 8 8 W

C
O

O
225

VC 64

VC 65
0 0
Y 21 20 20 S S 8 7 11 11 12 8 5 9 9 Y

C
0 0

O
225 224

VC 65

VC 44
AA 0 0 21 19 19 11 11 9 7 S S 13 13 3 5 1 4 AA

C
O

O
225

V C 64

VC 44
3
AB 3 3 18 18 12 12 9 7 S 2 14 14 17 3 1 4 2 AB

C
3

O
224 224 V C 64

V C 65
AC 2 2 17 15 13 13 5 5 1 2 5 15 17 S 6 6 2 AC
C

C
O

O
224

VC 65
2
AD 1 1 17 15 S 14 6 6 3 1 5 15 18 18 23 24 24 22 AD

C
2

O
224 224

VC 64

VC 65
1
AE 16 14 4 S 3 1 3 3 16 16 19 23 20 22 AE

C
1

O
224
VC 64

VC 65
0
AF G 16 4 2 2 1 6 6 4 4 19 21 21 20 AF
V

0 0
C

C
0
O

O
224 224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Bank 44 Quad 226 SelectIO Pins Dedicated Pins Transceiver Pins


Bank 45 Quad 227
Bank 46 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 64 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 65 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 66 # IO_L#P_GC # MGT[H or Y]TXN#

Quad 224 # IO_L#N_GC #


MGTREFCLK#P

Quad 225 VRP # MGTREFCLK#N

ug575_c3_01_071314

Figure 3-1: FBVA676 Package—XCKU035 and XCKU040 and


RBA676 Package—XQKU040 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


204
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A A
B B
C V E C
D V D
E E E
F 13 F
G V E 9 G
H V 11 H
V
J 15 J
K 10 K
L V E 12 19 L
M V 14 M
N E 16 18 N
P 5 20 24 21 P
R V E 4 17 22 23 R
T V 3 8 7 T
U E 2 0 U
V 6 26 26 V
V
W V 25 26 26 26 25 W
Y V 1 25 26 26 26 25 Y
AA E 35 27 26 26 AA
AB 25 31 26 26 29 AB
AC V E 36 32 25 26 29 35 AC
AD V 37 25 26 29 29 33 30 28 29 AD
AE E 25 25 26 26 29 34 29 29 AE
AF 25 25 25 25 29 29 29 29 AF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_02_071314

Figure 3-2: FBVA676 Package—XCKU035 and XCKU040 and


RBA676 Package—XQKU040 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


205
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

SFVA784 (XCKU035 and XCKU040)


X-Ref Target - Figure 3-3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

VC 68

VC 47

V C 46
A 8 8 S 10 S 17 17 23 24 17 17 18 18 9 9 10 S 17 17 S 24 22 22 A

C
O

O
V C 68

V C 67

VC 47
B 7 9 10 16 16 15 23 24 S S 16 16 8 8 10 15 15 16 23 24 21 21 19 B

C
O

O
V C 67

V C 47
C 7 9 11 12 14 15 18 21 22 22 14 14 7 7 12 12 14 16 18 23 20 20 19 C

C
O

O
VC 68

VC 47

VC 46
D 4 11 12 13 14 18 21 20 20 13 13 15 S 11 11 13 14 18 18 18 S 17 D

C
O

O
VC 68

VC 67

VC 46
E 4 3 5 13 S 23 24 19 19 11 11 15 6 6 5 13 23 23 S 14 14 17 16 E

C
O

O
VC 68

VC 67

VC 47
F 3 5 6 22 23 24 6 6 12 12 10 10 5 4 4 24 22 13 13 15 16 F

C
O

O
VC 68

V C 47

V C 46
G 2 6 22 21 21 5 5 3 S 9 8 3 3 2 24 22 21 6 12 12 15 G

C
O

O
VC 68

VC 67

VC 46
H 24 2 1 1 20 19 19 4 3 1 1 9 8 1 1 2 20 21 5 6 11 10 10 H

C
O

O
VC 66

VC 67

VC 46
J 24 S 18 18 20 4 2 2 7 7 19 19 20 5 4 11 9 S J

C
O

O
K 23 23 22 17 17 16 16 15 2 2 3 4 7 9 8 8 K

VC 66

V C 45
L 20 21 22 S 13 14 14 15 3 1 1 7 S 23 L

C
O

O
VC 66

VC 45
M 20 21 19 13 12 12 10 18 18 S 24 24 21 21 23 M

C
O

O
N 19 9 9 11 11 10 17 17 15 15 13 19 19 20 N

VC 66

V C 45
3
P 8 7 16 16 14 13 22 22 20 P

C
3

O
225

VC 45
R 3 3 8 6 6 7 6 6 14 11 11 10 10 R

C
O
225

VC 45
2
T S 5 5 4 4 5 5 12 12 9 9 T

C
2

O
225

VC 66

VC 45
U 2 2 4 4 3 3 8 8 S U

C
O

O
225

VC 44
1 1
V 3 3 2 2 1 1 18 17 7 7 V

C
1 1

O
225 225

VC 44
W 1 1 2 2 23 S 18 13 17 16 W

C
O
225

V C 66
0 0
Y 1 24 19 19 17 20 20 22 23 24 23 22 22 13 15 15 16 Y

C
0 0

O
225 225

V C 65

VC 44
AA 0 0 1 24 18 17 15 S 21 22 23 24 21 21 14 14 S S AA

C
O

O
225

VC 64

VC 44
3 1
AB 23 23 20 18 15 16 19 21 24 24 20 20 11 11 12 9 AB

C
3 1

O
224 224

V C 64

V C 65
AC 3 3 S 22 20 13 13 16 19 S 15 17 18 19 19 7 12 9 10 AC

C
O

O
224

VC 65

VC 44
2 0
AD S 22 21 21 14 14 S 16 15 17 14 18 6 7 8 8 10 AD

C
2 0

O
224 224

VC 64

VC 65
AE 2 2 10 11 11 6 6 1 16 13 13 14 5 5 6 1 1 5 6 AE

C
O

O
224

VC 64

V C 65
1
AF 1 1 10 12 12 4 4 3 1 12 12 11 11 3 3 4 2 5 6 AF
C

C
1
O

O
224 224
VC 64

V C 65

V C 44
AG 0 0 9 9 7 5 3 S 7 8 9 9 1 1 4 2 3 4 AG
C

C
O

O
224

VC 64

VC 44
0
AH G 8 8 7 5 2 2 7 8 10 10 S S 2 2 3 4 AH
V

C
0

O
224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Bank 44 Bank 67 SelectIO Pins Dedicated Pins Transceiver Pins


Bank 45 Quad 224
Bank 46 Quad 225 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V
#

Bank 48 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 64 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 65 # IO_L#N_GC #
MGTREFCLK#P

Bank 66 VRP # MGTREFCLK#N

ug575_c3_03_070615

Figure 3-3: SFVA784 Package—XCKU035 and XCKU040 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


206
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A A
B B
C C
D D
E E
F F
G G
H H
J J
K 12 K
L 11 L
M 10 M
N 1 24 21 N
P 9 22 23 P
R V 19 8 7 R
T V 18 T
U 4 20 U
V V 5 0 V
W V E 17 W
V
Y 3 29 29 29 33 Y
AA E 2 35 29 29 34 AA
V
AB 15 29 29 30 28 AB
AC V E 13 29 27 26 29 29 AC
AD V 6 26 26 29 26 29 25 AD
AE E 14 26 26 26 26 25 25 25 AE
AF V 26 26 26 26 25 25 25 AF
AG V E 25 25 26 26 36 37 25 AG
AH E 16 25 25 26 26 35 25 31 32 AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_04_070615

Figure 3-4: SFVA784 Package—XCKU035 and XCKU040 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


207
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FBVA900 (XCKU035 and XCKU040)


X-Ref Target - Figure 3-5

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

VC 66

VC 47
3
A 23 23 22 24 24 3 3 4 4 1 1 S 7 7 3 1 1 2 A

C
3

O
227

V C 67

V C 48
2
B 3 3 20 20 22 S 1 5 5 6 3 3 5 5 9 9 5 3 4 2 B

C
2

O
227 227

VC 67

VC 48

V C 47
C 2 2 19 19 21 21 18 1 6 2 2 2 2 10 10 5 6 6 4 C

C
O

O
227

VC 66

VC 47
1 1
D 15 15 17 17 18 7 7 S 8 8 4 6 11 11 8 9 7 7 D

C
1 1

O
227 227

V C 66

VC 48
E 1 1 S 13 13 14 16 9 11 11 12 4 6 12 12 8 9 11 11 8 E

C
O

O
227

VC 67

VC 48
0 0
F S 9 11 14 16 15 9 14 12 10 17 13 13 15 S 12 12 8 10 F

C
0 0

O
227 227

VC 67

VC 66

V C 47
G 0 0 9 11 12 12 15 13 13 14 10 17 14 14 15 21 21 14 S 10 G

C
O

O
227

VC 66

VC 47
3 1
H 7 7 10 10 8 17 18 16 16 S 16 16 18 18 19 14 13 13 H

C
3 1

O
226 226

VC 67

VC 48
J 3 3 3 3 5 5 8 17 19 18 20 20 20 21 23 23 19 24 15 15 S J

C
O

O
226

VC 67

V C 66

VC 47
2 0
K 2 4 6 22 19 23 23 20 21 19 S 23 24 17 17 16 K

C
2 0

O
226 226

V C 66

VC 47
L 2 2 1 1 2 4 6 S 22 24 21 21 22 19 S 23 20 18 18 16 L

C
O

O
226

VC 48
1
M 24 22 24 24 22 22 20 3 M

C
1

O
226

VC 46

VC 46
N 1 1 24 24 16 16 9 9 5 3 N

C
O

O
226

VC 46
0
P 22 22 18 18 11 11 5 1 1 P

C
0

O
226

VC 46
R 0 0 20 20 S 17 12 12 7 7 4 R

C
O
226

VC 46
3
T 23 17 14 14 10 6 6 4 T

C
3

O
225

V C 46
U 3 3 23 21 19 13 13 S 10 2 2 U

C
O
225

VC 46
2
V 21 19 15 15 S 8 8 S V

C
2

O
225

V C 45
W 2 2 5 5 4 4 9 9 23 23 21 W

C
O
225

VC 65

VC 64

VC 45
1 1
Y 23 24 24 22 5 5 S 2 2 7 7 20 24 21 Y

C
1 1

O
225 225

VC 64

VC 45
AA 1 1 23 21 21 22 S 3 1 4 4 6 3 6 6 12 20 24 22 19 AA

C
O

O
225

VC 65

VC 45
0 0
AB 19 19 20 20 3 1 2 2 6 6 3 8 12 11 14 22 19 AB

C
0 0

O
225 225

VC 65

VC 44

VC 45
AC 0 0 17 15 18 18 16 7 8 8 10 10 4 6 1 8 11 14 13 15 AC

C
O

O
225

V C 64

VC 45
3 1
AD 17 15 14 14 16 7 12 12 9 9 2 4 1 10 10 S 13 15 17 AD

C
3 1

O
224 224

VC 64

V C 44
AE 3 3 9 13 13 S 10 11 11 S S 1 2 5 5 S 16 16 S 17 AE

C
O

O
224
VC 6 5

VC 44
2 0
AF 9 7 11 C
S 10 17 13 16 16 18 1 8 12 12 13 19 19 18 18 AF

C
2 0 O

O
224 224
VC 65

VC 64

VC 44
AG 2 2 7 11 12 12 17 13 14 14 18 3 3 8 14 13 17 17 21 S AG
C

C
O

O
224

VC 64

V C 44
1
AH 1 1 5 5 8 8 S 19 15 15 20 20 S 11 11 14 18 24 24 21 AH

C
1

O
224 224
V C 65

VC 44
AJ 0 0 1 3 3 2 6 19 21 21 22 22 7 7 9 15 15 18 22 22 23 AJ
C

C
O

O
224
VC 65

VC 64

VC 44
0
AK G 1 2 4 4 6 23 23 24 24 S 10 10 9 16 16 20 20 23 AK
V

C
0
O

O
224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Bank 44 Bank 67 SelectIO Pins Dedicated Pins Transceiver Pins


Bank 45 Quad 224
Bank 46 Quad 225 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Quad 226 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 48 Quad 227 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 64 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 65 # IO_L#N_GC #
MGTREFCLK#P

Bank 66 VRP # MGTREFCLK#N

ug575_c3_05_100715

Figure 3-5: FBVA900 Package—XCKU035 and XCKU040 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


208
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-6

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A E A
B B
C V E C
D V 15 D
E E 9 E
F 10 F
G V E 11 G
H V 12 H
J E J
K 6 K
L V 14 1 L
M V 19 M
N 18 N
V
P P
R V 20 24 21 R
T V 22 23 T
U 0 8 7 U
V
V 17 V
W V 13 W
Y V 5 33 28 30 29 Y
AA E 4 34 29 29 29 35 AA
AB 3 29 29 29 29 AB
AC V E 2 29 26 29 29 26 AC
AD V 16 29 26 26 26 26 AD
AE E 26 26 26 27 26 AE
AF 26 25 26 35 26 AF
AG V E 25 26 26 26 AG
AH V 25 25 25 25 25 AH
AJ E 36 25 25 31 25 AJ
AK 37 32 25 25 25 AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_06_100715

Figure 3-6: FBVA900 Package—XCKU035 and XCKU040 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


209
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVA1156 (XCKU025)
X-Ref Target - Figure 3-7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A 2 4 23 23 A

V C 66
B 2 4 21 20 B

C
O
V C 66
C 3 5 21 20 24 C

C
O
D 3 5 6 19 24 D
E 1 6 19 S 22 E

VC 66
F 1 11 12 S 22 F

C
O
VC 66
G 11 12 13 14 2 2 1 G

C
O

VC 65
H 9 8 13 14 18 S 6 5 1 H

C
O
V C 66

VC 65
J 9 8 10 15 18 6 4 4 5 J

C
O

O
VC 66
K 7 10 15 17 16 24 24 S 10 9 3 3 K

C
O

VC 65
L 7 S 17 16 22 10 8 8 9 7 L

C
O
VC 65
M 22 23 19 12 11 11 7 M

C
O
VC 65
N 23 19 S 12 13 S N

C
O

V C 65
3
P 20 20 18 14 14 13 P

C
3

O
226

VC 65
R 3 3 21 21 18 17 17 15 R

C
O
226
2 1
T 2
226
1
226
16 16 15 T
U 2
226
2 U
1 0
V 1
226
0
226
V
W 1
226
1 W
0 1
Y 0
226
1
225
Y
AA 0
226
0 AA
3 0
AB 3
225
0
225
AB
AC 3
225
3 AC

V C 45
2 1
AD 17 17 16 10 S 24 24 19 19 3 1 AD

C
2 1

O
225 224

VC 4 5

VC 44
AE 2 2 15 16 10 9 7 22 22 23 21 3 1 5 5 7 7 AE

C
O

O
225
VC 64

VC 44
1 0
AF 15 14 13 9 7 20 20 23 21 2 6 8 8 S AF
C

C
1 0
O

O
225 224
VC 64

VC 45

VC 46
AG 1 1 14 13 12 11 18 18 15 15 17 2 4 6 9 9 AG
C

C
O

O
225
VC 4 5

VC 44
0
AH 0 0 18 18 12 11 8 S 14 13 13 17 4 12 12 10 1 5 5 S 17 17 16 18 AH
C

C
0
O

O
225 225
VC 64

VC 44

VC 46
3
AJ 23 23 S S 8 16 16 14 11 S 16 13 11 11 10 1 6 13 15 15 16 18 AJ
C

C
3
O

O
224
VC 64

V C 45

VC 46
2
AK 3 3 24 21 S 5 6 9 12 12 11 16 13 14 14 S 3 3 6 13 14 14 S AK
C

C
2
O

O
224 224
VC 45

VC 46
AL 2 2 24 21 19 5 6 7 9 10 10 8 15 17 17 18 18 4 4 11 12 19 19 24 AL
C

C
O

O
224
VC 64

VC 44

VC 46
1
AM 1 1 S 19 3 4 7 5 5 3 8 15 19 20 21 S 2 2 11 12 S 23 24 AM
C

C
1
O

O
224 224
VC 64

V C 44

VC 46
AN 0 0 22 20 3 4 2 1 3 4 4 2 19 20 24 21 7 9 9 10 21 23 20 22 AN
C

C
O

O
224
VC 45

VC 46
0
AP G 22 20 1 1 2 1 6 6 2 22 22 24 23 23 7 8 8 10 21 20 22 AP
V

C
0
O

O
224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 44 Quad 226 SelectIO Pins Dedicated Pins Transceiver Pins


Bank 45
Bank 46 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 64 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 65 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 66 # IO_L#P_GC # MGT[H or Y]TXN#

Quad 224 # IO_L#N_GC #


MGTREFCLK#P

Quad 225 VRP # MGTREFCLK#N

ug575_c3_07_032416

Figure 3-7: FFVA1156 Package—XCKU025 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


210
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-8

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A n n n n n n n n n n n n n n n n n n n A
B n n n n n n n n n n n n n n n n n n n n B
C V n n E n n n n n n n n n n n n n n V n n C
D n n V n n n n n n n n n n n n n n n n n n n V D
E n n E n n n n n n n n n n n n n n E n n E
F n n n n n n n n n n n n n n n n E n n F
G V n n E n n n n n n n n n n 31 32 37 n n V n n G
H n n V n n n n n n n n n n 25 25 25 36 E n n V H
J n n E n n n n n n 25 25 25 25 n n E n n J
V
K n n n n 10 n n n n n 30 28 35 26 26 25 25 n n V K
L V n n E 11 n n n n n n 29 26 25 25 26 25 n n V n n L
V
M n n V n n 12 29 34 29 26 26 26 25 n n M
N n n E 6 33 29 35 26 26 27 n n E n n N
P n n 13 29 29 29 26 26 26 E n n V P
V
R V 15 29 29 29 29 29 26 n n V n n R
T V 14 n n n 26 26 26 n n T
U E 16 19 n n n n n n n n n U
V 9 18 24 21 n n n n n n n n n n n n n V
W V E 1 20 22 23 n n n n n n n n n n n n n W
Y V 5 8 7 n n n n n n n n n n n n Y
V
AA 4 0 n n n n n n n n n n n n n AA
AB 3 n n n n n n n n n n n n n n AB
AC V E 2 17 n n n n n n n n n n n n n n AC
AD V n n n n n n n n n AD
AE E n n n n n n n AE
AF n n n n n n n n AF
AG V E n n n n n AG
AH V AH
AJ E AJ
AK AK
AL V E AL
AM V AM
AN E AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_08_032416

Figure 3-8: FFVA1156 Package—XCKU025 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


211
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVA1156 (XCKU035)
X-Ref Target - Figure 3-9

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VC 68

VC 67
A 2 4 23 23 1 3 2 2 17 S S 10 8 6 6 4 A

C
O

O
VC 66

V C 67
B 2 4 21 20 1 3 5 5 4 17 15 15 10 8 9 2 4 B

C
O

O
VC 66

V C 67
C 3 5 21 20 24 7 S 6 6 4 16 16 13 12 9 2 5 C

C
O

O
VC 68

VC 67
D 3 5 6 19 24 7 8 11 10 10 18 18 13 12 11 7 5 3 D

C
O

O
V C 68

VC 67
E 1 6 19 S 22 8 11 12 12 20 20 14 14 11 7 1 3 E

C
O

O
VC 66

VC 67
3
F 1 11 12 S 22 9 9 14 14 16 22 23 21 21 19 1 F

C
3

O
227

VC 66

VC 68
G 3 3 11 12 13 14 15 15 13 13 16 22 24 23 19 2 2 1 G

C
O

O
227

V C 68

VC 65
2
H 9 8 13 14 18 S 17 17 18 18 24 S S 6 5 1 H

C
2

O
227

VC 66

VC 65
J 2 2 9 8 10 15 18 19 19 23 22 22 6 4 4 5 J

C
O

O
227

VC 66

VC 68
1
K 7 10 15 17 16 21 23 20 20 24 24 S 10 9 3 3 K

C
1

O
227

VC 68

VC 6 5
L 1 1 7 S 17 16 21 S 24 24 22 10 8 8 9 7 L

C
O

O
227

VC 6 5
0 1
M 22 23 19 12 11 11 7 M

C
0 1

O
227 227

VC 65
N 0 0 23 19 S 12 13 S N

C
O
227

VC 65
3 0
P 20 20 18 14 14 13 P

C
3 0

O
226 227

VC 65
R 3 3 21 21 18 17 17 15 R

C
O
226

VC 4 7
2 1
T 17 17 16 16 15 T

C
2 1

O
226 226

VC 47
U 2 2 15 15 20 20 22 22 S 23 U

C
O
226

VC 47
1 0
V 18 16 16 24 19 19 23 24 S 21 23 V

C
1 0

O
226 226

VC 47

VC 4 8
W 1 1 18 13 13 14 24 21 23 20 24 19 21 W

C
O

O
226

VC 48
0 1
Y S S 11 14 1 1 21 20 22 22 19 Y

C
0 1

O
226 225

VC 47
AA 0 0 9 7 11 12 12 5 16 13 S 17 AA

C
O
226

VC 47

VC 48
3 0
AB 9 10 7 3 6 6 5 16 14 14 13 17 AB

C
3 0

O
225 225

VC 47

VC 4 8
AC 3 3 10 8 8 3 4 4 3 12 12 18 15 AC

C
O

O
225

VC 45

V C 48
2 1
AD 17 17 16 10 S 24 24 19 19 3 1 2 2 3 5 11 11 18 15 AD

C
2 1

O
225 224

VC 45

VC 44

V C 48
AE 2 2 15 16 10 9 7 22 22 23 21 3 1 5 5 7 7 1 2 5 S 9 10 AE
C

C
O

O
225
VC 64

VC 44

V C 48
1 0
AF 15 14 13 9 7 20 20 23 21 2 6 8 8 S 1 2 4 6 9 8 10 AF
C

C
1 0
O

O
225 224
VC 64

VC 45

VC 46
AG 1 1 14 13 12 11 18 18 15 15 17 2 4 6 9 9 4 6 7 7 8 AG
C

C
O

O
225
VC 45

VC 44
0
AH 0 0 18 18 12 11 8 S 14 13 13 17 4 12 12 10 1 5 5 S 17 17 16 18 AH
C

C
0
O

O
225 225
VC 6 4

V C 44

VC 46
3
AJ 23 23 S S 8 16 16 14 11 S 16 13 11 11 10 1 6 13 15 15 16 18 AJ
C

C
3
O

O
224
VC 64

VC 45

VC 46
2
AK 3 3 24 21 S 5 6 9 12 12 11 16 13 14 14 S 3 3 6 13 14 14 S AK
C

C
2
O

O
224 224
VC 45

VC 46
AL 2 2 24 21 19 5 6 7 9 10 10 8 15 17 17 18 18 4 4 11 12 19 19 24 AL
C

C
O

O
224
V C 64

VC 44

VC 46
1
AM 1 1 S 19 3 4 7 5 5 3 8 15 19 20 21 S 2 2 11 12 S 23 24 AM
C

C
1
O

O
224 224
VC 6 4

VC 44

VC 46
AN 0 0 22 20 3 4 2 1 3 4 4 2 19 20 24 21 7 9 9 10 21 23 20 22 AN
C

C
O

O
224
VC 45

VC 46
0
AP G 22 20 1 1 2 1 6 6 2 22 22 24 23 23 7 8 8 10 21 20 22 AP
V

C
0
O

O
224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 44 Bank 67 SelectIO Pins Dedicated Pins Transceiver Pins


Bank 45 Bank 68
Bank 46 Quad 224 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Quad 225 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 48 Quad 226 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 64 Quad 227 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 65 # IO_L#N_GC #
MGTREFCLK#P

Bank 66 VRP # MGTREFCLK#N

ug575_c3_09_100715

Figure 3-9: FFVA1156 Package—XCKU035 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


212
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-10

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A n n n n A
B n n n n n n B
C V n n E V n n C
D n n V n n n n V D
E n n E E n n E
F n n E n n F
G V E 31 32 37 n n V n n G
H V n n 25 25 25 36 E n n V H
J E 25 25 25 25 n n E n n J
V
K n n 10 30 28 35 26 26 25 25 n n V K
L V E 11 29 26 25 25 26 25 n n V n n L
V
M V 12 29 34 29 26 26 26 25 n n M
N E 6 33 29 35 26 26 27 n n E n n N
P 13 29 29 29 26 26 26 E n n V P
V
R V 15 29 29 29 29 29 26 n n V n n R
T V 14 26 26 26 n n T
U E 16 19 U
V 9 18 24 21 V
W V E 1 20 22 23 W
Y V 5 8 7 Y
V
AA 4 0 AA
AB 3 AB
AC V E 2 17 AC
AD V AD
AE E AE
AF AF
AG V E AG
AH V AH
AJ E AJ
AK AK
AL V E AL
AM V AM
AN E AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_10_100715

Figure 3-10: FFVA1156 Package—XCKU035 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


213
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVA1156 (XCKU040) and RFA1156 (XQKU040)


X-Ref Target - Figure 3-11

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VC 68

VC 67
3
A 2 4 23 23 1 3 2 2 17 S S 10 8 6 6 4 A

C
3

O
228

VC 66

VC 6 7
2
B 3 3 2 4 21 20 1 3 5 5 4 17 15 15 10 8 9 2 4 B

C
2

O
228 228

VC 66

V C 67
C 2 2 3 5 21 20 24 7 S 6 6 4 16 16 13 12 9 2 5 C

C
O

O
228

VC 68

VC 67
1
D 1 1 3 5 6 19 24 7 8 11 10 10 18 18 13 12 11 7 5 3 D

C
1

O
228 228

VC 68

VC 67
0
E 1 6 19 S 22 8 11 12 12 20 20 14 14 11 7 1 3 E

C
0

O
228

VC 66

VC 67
3
F 0 0 1 11 12 S 22 9 9 14 14 16 22 23 21 21 19 1 F

C
3

O
227 228

VC 66

VC 68
G 3 3 11 12 13 14 15 15 13 13 16 22 24 23 19 2 2 1 G

C
O

O
227

V C 68

VC 6 5
2 1
H 9 8 13 14 18 S 17 17 18 18 24 S S 6 5 1 H

C
2 1

O
227 228

VC 66

VC 6 5
J 2 2 9 8 10 15 18 19 19 23 22 22 6 4 4 5 J

C
O

O
227

VC 66

VC 68
1 0
K 7 10 15 17 16 21 23 20 20 24 24 S 10 9 3 3 K

C
1 0

O
227 228

VC 68

VC 65
L 1 1 7 S 17 16 21 S 24 24 22 10 8 8 9 7 L

C
O

O
227

VC 65
0 1
M 22 23 19 12 11 11 7 M

C
0 1

O
227 227

VC 65
N 0 0 23 19 S 12 13 S N

C
O
227

VC 6 5
3 0
P 20 20 18 14 14 13 P

C
3 0

O
226 227

V C 65
R 3 3 21 21 18 17 17 15 R

C
O
226

VC 47
2 1
T 17 17 16 16 15 T

C
2 1

O
226 226

VC 47
U 2 2 15 15 20 20 22 22 S 23 U

C
O
226

VC 47
1 0
V 18 16 16 24 19 19 23 24 S 21 23 V

C
1 0

O
226 226

VC 47

VC 48
W 1 1 18 13 13 14 24 21 23 20 24 19 21 W

C
O

O
226

VC 4 8
0 1
Y S S 11 14 1 1 21 20 22 22 19 Y

C
0 1

O
226 225

VC 47
AA 0 0 9 7 11 12 12 5 16 13 S 17 AA

C
O
226

V C 47

VC 48
3 0
AB 9 10 7 3 6 6 5 16 14 14 13 17 AB

C
3 0

O
225 225

VC 4 7

V C 48
AC 3 3 10 8 8 3 4 4 3 12 12 18 15 AC

C
O

O
225

V C 45

VC 48
2 1
AD 17 17 16 10 S 24 24 19 19 3 1 2 2 3 5 11 11 18 15 AD

C
2 1

O
225 224

VC 45

V C 44

VC 48
AE 2 2 15 16 10 9 7 22 22 23 21 3 1 5 5 7 7 1 2 5 S 9 10 AE

C
O

O
225
VC 64

VC 44

VC 48
1 0
AF 15 14 13 9 7 20 20 23 21 2 6 8 8 S 1 2 4 6 9 8 10 AF
C

C
1 0
O

O
225 224
VC 64

VC 45

VC 46
AG 1 1 14 13 12 11 18 18 15 15 17 2 4 6 9 9 4 6 7 7 8 AG
C

C
O

O
225
V C 45

VC 44
0
AH 0 0 18 18 12 11 8 S 14 13 13 17 4 12 12 10 1 5 5 S 17 17 16 18 AH
C

C
0
O

O
225 225
VC 6 4

V C 44

VC 46
3
AJ 23 23 S S 8 16 16 14 11 S 16 13 11 11 10 1 6 13 15 15 16 18 AJ
C

C
3
O

O
224
VC 64

VC 45

VC 46
2
AK 3 3 24 21 S 5 6 9 12 12 11 16 13 14 14 S 3 3 6 13 14 14 S AK
C

C
2
O

O
224 224
VC 4 5

VC 46
AL 2 2 24 21 19 5 6 7 9 10 10 8 15 17 17 18 18 4 4 11 12 19 19 24 AL
C

C
O

O
224
V C 64

V C 44

VC 46
1
AM 1 1 S 19 3 4 7 5 5 3 8 15 19 20 21 S 2 2 11 12 S 23 24 AM
C

C
1
O

O
224 224
VC 64

VC 4 4

VC 46
AN 0 0 22 20 3 4 2 1 3 4 4 2 19 20 24 21 7 9 9 10 21 23 20 22 AN
C

C
O

O
224
VC 45

VC 46
0
AP G 22 20 1 1 2 1 6 6 2 22 22 24 23 23 7 8 8 10 21 20 22 AP
V

C
0
O

O
224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 44 Bank 67 SelectIO Pins Dedicated Pins Transceiver Pins


Bank 45 Bank 68
Bank 46 Quad 224 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Quad 225 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 48 Quad 226 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 64 Quad 227 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 65 Quad 228 # IO_L#N_GC #


MGTREFCLK#P

Bank 66 VRP # MGTREFCLK#N

ug575_c3_11_100715

Figure 3-11: FFVA1156 Package—XCKU040 and RFA1156 Package—XQKU040 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


214
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-12

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A n n A
B n n B
C V E V n n C
D V n n V D
E E E n n E
F E n n F
G V E 31 32 37 n n V n n G
H V 25 25 25 36 E n n V H
J E 25 25 25 25 n n E n n J
V
K 10 30 28 35 26 26 25 25 n n V K
L V E 11 29 26 25 25 26 25 n n V n n L
V
M V 12 29 34 29 26 26 26 25 n n M
N E 6 33 29 35 26 26 27 n n E n n N
P 13 29 29 29 26 26 26 E n n V P
V
R V 15 29 29 29 29 29 26 n n V n n R
T V 14 26 26 26 n n T
U E 16 19 U
V 9 18 24 21 V
W V E 1 20 22 23 W
Y V 5 8 7 Y
V
AA 4 0 AA
AB 3 AB
AC V E 2 17 AC
AD V AD
AE E AE
AF AF
AG V E AG
AH V AH
AJ E AJ
AK AK
AL V E AL
AM V AM
AN E AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_12_100715

Figure 3-12: FFVA1156 Package—XCKU040 and RFA1156 Package—XQKU040


Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


215
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVA1156 (XCKU060) and RFA1156 (XQKU060)


X-Ref Target - Figure 3-13

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VC 68

VC 67
3
A 2 4 23 23 1 3 2 2 17 S S 10 8 6 6 4 G A

V
C

C
3

O
228

V C 66

V C 67
2
B 3 3 2 4 21 20 1 3 5 5 4 17 15 15 10 8 9 2 4 3 3 B

C
2

O
228 228 128

VC 66

VC 67
3
C 2 2 3 5 21 20 24 7 S 6 6 4 16 16 13 12 9 2 5 C

C
3

O
228 128

VC 68

VC 67
1
D 1 1 3 5 6 19 24 7 8 11 10 10 18 18 13 12 11 7 5 3 2 2 D

C
1

O
228 228 128

VC 68

VC 67
0 2
E 1 6 19 S 22 8 11 12 12 20 20 14 14 11 7 1 3 E

C
0 2

O
228 128

V C 66

VC 67
3 1
F 0 0 1 11 12 S 22 9 9 14 14 16 22 23 21 21 19 1 F

C
3 1

O
227 228 128

VC 66

VC 68
0
G 3 3 11 12 13 14 15 15 13 13 16 22 24 23 19 2 2 1 1 1 G

C
0

O
227 128 128

V C 68

VC 65
2 1
H 9 8 13 14 18 S 17 17 18 18 24 S S 6 5 1 0 0 H

C
2 1

O
227 228 128

VC 66

VC 6 5
1 3
J 2 2 9 8 10 15 18 19 19 23 22 22 6 4 4 5 J

C
1 3

O
227 128 127

VC 66

VC 68
1 0
K 7 10 15 17 16 21 23 20 20 24 24 S 10 9 3 3 3 3 K

C
1 0

O
227 228 127

V C 68

V C 65
0 2
L 1 1 7 S 17 16 21 S 24 24 22 10 8 8 9 7 L

C
0 2

O
227 128 127

VC 65
0 1
M 22 23 19 12 11 11 7 2 2 M

C
0 1

O
227 227 127

VC 65
1 1
N 0 0 23 19 S 12 13 S N

C
1 1

O
227 127 127

VC 65
3 0
P 20 20 18 14 14 13 1 1 P

C
3 0

O
226 227 127

VC 65
0 0
R 3 3 21 21 18 17 17 15 R

C
0 0

O
226 127 127

VC 47
2 1
T 17 17 16 16 15 0 0 T

C
2 1

O
226 226 127

VC 47
U 2 2 15 15 20 20 22 22 S 23 U

C
O
226

VC 4 7
1 0
V 18 16 16 24 19 19 23 24 S 21 23 V

C
1 0

O
226 226

VC 47

VC 48
W 1 1 18 13 13 14 24 21 23 20 24 19 21 W

C
O

O
226

VC 48
0 1
Y S S 11 14 1 1 21 20 22 22 19 Y

C
0 1

O
226 225

V C 47
AA 0 0 9 7 11 12 12 5 16 13 S 17 AA

C
O
226

VC 47

VC 48
3 0
AB 9 10 7 3 6 6 5 16 14 14 13 17 AB

C
3 0

O
225 225

VC 4 7

VC 48
AC 3 3 10 8 8 3 4 4 3 12 12 18 15 AC

C
O

O
225

VC 45

VC 48
2 1
AD 17 17 16 10 S 24 24 19 19 3 1 2 2 3 5 11 11 18 15 AD

C
2 1

O
225 224

VC 45

VC 44

V C 48
AE 2 2 15 16 10 9 7 22 22 23 21 3 1 5 5 7 7 1 2 5 S 9 10 AE
C

C
O

O
225
VC 64

VC 44

VC 48
1 0
AF 15 14 13 9 7 20 20 23 21 2 6 8 8 S 1 2 4 6 9 8 10 AF
C

C
1 0
O

O
225 224
VC 64

VC 45

VC 46
AG 1 1 14 13 12 11 18 18 15 15 17 2 4 6 9 9 4 6 7 7 8 AG
C

C
O

O
225
VC 45

VC 44
0
AH 0 0 18 18 12 11 8 S 14 13 13 17 4 12 12 10 1 5 5 S 17 17 16 18 AH
C

C
0
O

O
225 225
VC 6 4

V C 44

VC 46
3
AJ 23 23 S S 8 16 16 14 11 S 16 13 11 11 10 1 6 13 15 15 16 18 AJ
C

C
3
O

O
224
VC 64

VC 45

VC 46
2
AK 3 3 24 21 S 5 6 9 12 12 11 16 13 14 14 S 3 3 6 13 14 14 S AK
C

C
2
O

O
224 224
VC 45

VC 46
AL 2 2 24 21 19 5 6 7 9 10 10 8 15 17 17 18 18 4 4 11 12 19 19 24 AL
C

C
O

O
224
V C 64

V C 44

VC 46
1
AM 1 1 S 19 3 4 7 5 5 3 8 15 19 20 21 S 2 2 11 12 S 23 24 AM
C

C
1
O

O
224 224
VC 64

VC 44

VC 46
AN 0 0 22 20 3 4 2 1 3 4 4 2 19 20 24 21 7 9 9 10 21 23 20 22 AN
C

C
O

O
224
V C 45

VC 46
0
AP G 22 20 1 1 2 1 6 6 2 22 22 24 23 23 7 8 8 10 21 20 22 AP
V

C
0
O

O
224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 44 Bank 67 Quad 228 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 68
Bank 46 Quad 127 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Quad 128 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 48 Quad 224 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 64 Quad 225 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 65 Quad 226 # IO_L#N_GC #


MGTREFCLK#P

Bank 66 Quad 227 VRP # MGTREFCLK#N

ug575_c3_13_100715

Figure 3-13: FFVA1156 Package—XCKU060 and RFA1156 Package—XQKU060 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


216
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-14

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A A
B B
C V E V C
D V V D
E E E E
F E F
G V E 31 32 37 V G
H V 25 25 25 36 E V H
J E 25 25 25 25 E J
V
K 10 30 28 35 26 26 25 25 V K
L V E 11 29 26 25 25 26 25 V L
V
M V 12 29 34 29 26 26 26 25 M
N E 6 33 29 35 26 26 27 E N
P 13 29 29 29 26 26 26 E V P
V
R V 15 29 29 29 29 29 26 V R
T V 14 26 26 26 T
U E 16 19 U
V 9 18 24 21 V
W V E 1 20 22 23 W
Y V 5 8 7 Y
V
AA 4 0 AA
AB 3 AB
AC V E 2 17 AC
AD V AD
AE E AE
AF AF
AG V E AG
AH V AH
AJ E AJ
AK AK
AL V E AL
AM V AM
AN E AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_14_100715

Figure 3-14: FFVA1156 Package—XCKU060 and RFA1156 Package—XQKU060


Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


217
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVA1156 (XCKU095) and RFA1156 (XQKU095)


X-Ref Target - Figure 3-15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VC 67

VC 68
3
A 2 4 23 23 1 3 2 2 17 S S 10 8 6 6 4 G A

V
C

C
3

O
228

VC 66

VC 68
2
B 3 3 2 4 21 20 1 3 5 5 4 17 15 15 10 8 9 2 4 3 3 B

C
2

O
228 228 130

VC 66

VC 68
3
C 2 2 3 5 21 20 24 7 S 6 6 4 16 16 13 12 9 2 5 C

C
3

O
228 130

V C 67

VC 68
1
D 1 1 3 5 6 19 24 7 8 11 10 10 18 18 13 12 11 7 5 3 2 2 D

C
1

O
228 228 130

VC 67

VC 68
0 2
E 1 6 19 S 22 8 11 12 12 20 20 14 14 11 7 1 3 E

C
0 2

O
228 130

VC 66

VC 68
3 1
F 0 0 1 11 12 S 22 9 9 14 14 16 22 23 21 21 19 1 F

C
3 1

O
227 228 130

V C 66

VC 67
0
G 3 3 11 12 13 14 15 15 13 13 16 22 24 23 19 2 2 1 1 1 G

C
0

O
227 130 130

VC 67

VC 65
2 1
H 9 8 13 14 18 S 17 17 18 18 24 S 6 5 1 0 0 H

C
2 1

O
227 228 130

VC 66

VC 65
1 3
J 2 2 9 8 10 15 18 19 19 23 22 22 6 4 4 5 J

C
1 3

O
227 130 129

V C 66

VC 67
1 0
K 7 10 15 17 16 21 23 20 20 24 24 S 10 9 3 3 3 3 K

C
1 0

O
227 228 129

VC 67

VC 65
0 2
L 1 1 7 S 17 16 21 S 24 24 22 10 8 8 9 7 L

C
0 2

O
227 130 129

VC 65
0 1
M 22 23 19 12 11 11 7 2 2 M

C
0 1

O
227 227 129

VC 65
1 1
N 0 0 23 19 S 12 13 S N

C
1 1

O
227 129 129

VC 65
3 0
P 20 20 18 14 14 13 1 1 P

C
3 0

O
226 227 129

V C 65
0 0
R 3 3 21 21 18 17 17 15 R

C
0 0

O
226 129 129

VC 47
2 1
T 17 17 16 16 15 0 0 T

C
2 1

O
226 226 129

VC 47
U 2 2 15 15 20 20 22 22 S 23 U

C
O
226

VC 47
1 0
V 18 16 16 24 19 19 23 24 S 21 23 V

C
1 0

O
226 226

VC 47

V C 48
W 1 1 18 13 13 14 24 21 23 20 24 19 21 W

C
O

O
226

V C 48
0 1
Y S S 11 14 1 1 21 20 22 22 19 Y

C
0 1

O
226 225

VC 4 7
AA 0 0 9 7 11 12 12 5 16 13 S 17 AA

C
O
226

VC 47

VC 48
3 0
AB 9 10 7 3 6 6 5 16 14 14 13 17 AB

C
3 0

O
225 225

VC 47

VC 48
AC 3 3 10 8 8 3 4 4 3 12 12 18 15 AC

C
O

O
225

V C 44

VC 48
2 1
AD 17 17 16 10 S 24 24 19 19 3 1 2 2 3 5 11 11 18 15 AD

C
2 1

O
225 224

VC 4 4

VC 45

VC 4 8
AE 2 2 15 16 10 9 7 22 22 23 21 3 1 5 5 7 7 1 2 5 S 9 10 AE
C

C
O

O
225
VC 64

VC 45

VC 48
1 0
AF 15 14 13 9 7 20 20 23 21 2 6 8 8 S 1 2 4 6 9 8 10 AF
C

C
1 0
O

O
225 224
VC 64

VC 44

VC 46
AG 1 1 14 13 12 11 18 18 15 15 17 2 4 6 9 9 4 6 7 7 8 AG
C

C
O

O
225
VC 44

VC 45
0
AH 0 0 18 18 12 11 8 S 14 13 13 17 4 12 12 10 1 5 5 S 17 17 16 18 AH
C

C
0
O

O
225 225
VC 64

VC 4 5

VC 46
3
AJ 23 23 S S 8 16 16 14 11 S 16 13 11 11 10 1 6 13 15 15 16 18 AJ
C

C
3
O

O
224
VC 64

VC 44

VC 46
2
AK 3 3 24 21 S 5 6 9 12 12 11 16 13 14 14 S 3 3 6 13 14 14 S AK
C

C
2
O

O
224 224
VC 44

VC 46
AL 2 2 24 21 19 5 6 7 9 10 10 8 15 17 17 18 18 4 4 11 12 19 19 24 AL
C

C
O

O
224
V C 64

V C 45

VC 46
1
AM 1 1 S 19 3 4 7 5 5 3 8 15 19 20 21 S 2 2 11 12 S 23 24 AM
C

C
1
O

O
224 224
VC 64

V C 45

VC 46
AN 0 0 22 20 3 4 2 1 3 4 4 2 19 20 24 21 7 9 9 10 21 23 20 22 AN
C

C
O

O
224
VC 44

VC 46
0
AP G 22 20 1 1 2 1 6 6 2 22 22 24 23 23 7 8 8 10 21 20 22 AP
V

C
0
O

O
224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 44 Bank 67 Quad 228 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 68
Bank 46 Quad 129 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Quad 130 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 48 Quad 224 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 64 Quad 225 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 65 Quad 226 # IO_L#N_GC #


MGTREFCLK#P

Bank 66 Quad 227 VRP # MGTREFCLK#N

ug575_c3_15_100715

Figure 3-15: FFVA1156 Package—XCKU095 and RFA1156 Package—XQKU095 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


218
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-16

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A A
B B
C V E V C
D V V D
E E E E
F E F
G V E 31 32 37 V G
H V 25 25 25 36 E V H
J E 25 25 25 25 E J
V
K 10 30 28 35 26 26 25 25 V K
L V E 11 29 26 25 25 26 25 V L
V
M V 12 29 34 29 26 26 26 25 M
N E 6 33 29 35 26 26 27 E N
P 13 29 29 29 26 26 26 E V P
V
R V 15 29 29 29 29 29 26 V R
T V 14 26 26 26 T
U E 16 19 U
V 9 18 24 21 V
W V E 1 20 22 23 W
Y V 5 8 7 Y
V
AA 4 0 AA
AB 3 AB
AC V E 2 17 AC
AD V AD
AE E AE
AF AF
AG V E AG
AH V AH
AJ E AJ
AK AK
AL V E AL
AM V AM
AN E AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_16_100715

Figure 3-16: FFVA1156 Package—XCKU095 and RFA1156 Package—XQKU095


Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


219
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVA1517 (XCKU060)
X-Ref Target - Figure 3-17

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

VC 6 6

VC 48

VC 46
A 19 19 21 21 24 24 21 23 23 S 21 24 S 23 23 19 22 S 24 22 17 17 A

C
O

O
VC 66

VC 6 8

VC 47
B 22 24 23 23 22 21 23 23 22 21 24 23 23 S 19 24 22 24 22 20 18 16 B

C
O

O
VC 67

VC 47
C 22 20 24 S 22 20 19 24 22 20 19 21 21 19 21 24 20 20 23 20 18 16 15 C

C
O

O
VC 67

VC 48

V C 46
D 20 15 15 17 20 19 S 24 20 19 22 22 19 21 18 16 S 23 21 19 14 15 D

C
O

O
V C 66

VC 68

VC 46
E 18 18 13 17 16 18 17 17 17 18 20 20 15 17 18 16 14 13 21 19 14 13 E

C
O

O
VC 68

VC 47
F 16 16 14 13 16 18 15 17 S 18 16 16 15 17 17 15 14 13 S 7 12 13 S F

C
O

O
V C 67

VC 48

V C 46
G S 14 11 11 S 13 15 15 15 16 16 18 18 17 15 11 12 9 7 11 12 8 G

C
O

O
VC 66

VC 48

VC 46
H S 7 12 S 14 14 13 13 13 14 14 14 13 13 9 11 12 8 9 11 10 10 8 H

C
O

O
VC 66

VC 68

VC 47
J 7 12 9 10 12 11 11 7 12 12 S 14 11 9 7 7 8 5 5 1 2 2 J

C
O

O
V C 67

VC 47

VC 46
K 10 10 9 10 7 12 9 7 11 11 10 12 12 11 S 10 10 3 1 6 4 K

C
O

O
VC 67

VC 48

VC 46
L 8 8 5 7 9 9 9 S 8 8 10 9 S 5 6 3 3 3 6 4 L

C
O

O
V C 66

VC 68
M 4 3 5 8 8 10 10 8 7 7 9 5 6 1 1 M

C
O

O
VC 68

VC 47
3
N 4 1 3 3 3 5 5 4 4 2 8 6 1 4 3 3 N

C
3

O
128 128

VC 67

VC 48
1 2
P 1 6 6 2 1 1 6 5 2 4 4 6 1 4 2 P

C
1 2

O
128 128

V C 66

VC 48
1
R 2 2 2 6 6 6 5 3 1 2 3 3 5 2 2 2 R

C
1

O
128 128

VC 68
0
T 4 4 3 1 2 5 1 1 T

C
0

O
128 128
0
U 0
128
0
128
0 U
3 1 3
V 3
228
3
228
3
127
1
127
3 V
2 1 2
W 2
228
1
228
3
127
3
127
2 W
1 0
Y 1
228
2
228
2
127
0 2
127
2 Y
0 1
AA 1
228
1 0
228
1
127
1
127
1 AA
0 1 0
AB 0
228
0
228
0
126
1
127
0 AB
3 1 3
AC 3
227
1
227
0
127
0
126
3 AC

VC 64

VC 45
2 0
AD 3 3 24 24 21 S 24 24 19 21 3 3 AD

C
2 0

O
227 227 126 126
V C 65

VC 45
0 2
AE 2 2 23 21 S 21 23 22 22 22 21 23 19 21 23 24 21 2 2 AE
C

C
0 2
O

O
227 227 126 126

VC 44
1 1 1
AF 23 21 22 20 23 22 24 20 21 23 22 20 23 24 23 21 G AF

V
1 1

C
1 1 1

O
227 227 226 126

V C 64

VC 24
0 0
AG 0 0 19 22 20 19 19 24 20 19 19 22 20 24 24 23 S 1 1 AG
C

C
0 0

O
227 227 126 126
VC 65

VC 45
3 0
AH 3 3 19 17 15 17 17 20 20 S 18 18 18 17 S 22 19 20 20 0 0 AH
C

C
3 0
O

O
226 226 226 126
VC 65

VC 44

VC 24
2
AJ 2 2 17 15 16 15 18 18 16 16 S 18 15 17 22 19 15 17 18 S AJ
C

C
2
O

O
226 226
V C 64

VC 24

VC 25
1 1
AK 1 1 18 18 16 15 16 16 17 17 14 13 15 S 13 13 15 17 16 18 23 23 22 22 AK
C

C
1 1
O

O
226 226 225
VC 64

VC 45

VC 25
0
AL 0 0 13 14 14 S 13 14 14 15 14 13 16 16 14 14 14 13 16 S 21 21 20 20 24 AL
C

C
0
O

O
226 226
VC 65

V C 44

VC 24
3 0
AM 3 3 13 12 S S 13 12 15 12 11 8 8 12 11 14 13 12 11 17 17 19 19 24 AM
C

C
3 0
O

O
225 225 225
VC 44

VC 24
2
AN 2 2 11 11 12 S 11 11 12 12 11 9 7 12 11 9 S 12 11 7 15 14 14 16 18 AN
C

C
2
O

O
225 225
VC 64

VC 45

VC 25
1 1
AP 1 1 10 10 8 9 10 10 S 10 9 7 10 S 9 10 8 8 7 15 S 13 16 18 AP
C

C
1 1
O

O
225 225 224
V C 65

V C 44

VC 25
0
AR 0 0 9 7 8 9 7 7 8 10 8 8 10 7 7 5 10 9 9 5 13 11 12 AR
C

C
0
O

O
225 225
VC 44

VC 24
3 0
AT 3 3 9 7 6 4 5 5 6 8 6 5 5 3 5 6 6 5 3 6 11 12 10 AT
C

C
3 0
O

O
224 224 224
VC 64

VC 45

VC 25
2
AU 2 2 5 6 4 3 3 6 S 4 6 4 4 3 4 4 5 1 3 6 7 9 10 AU
C

C
2
O

O
224 224
VC 65

VC 45

VC 25
1
AV G 5 3 1 2 1 1 4 2 4 3 1 6 6 1 2 5 1 2 2 7 9 8 8 AV
V

1 1
C

C
1
O

O
224 224
V C 65

VC 44

V C 24
0
AW 0 0 3 1 S 2 4 2 2 2 3 1 2 2 1 2 3 3 1 1 4 4 S AW
C

C
0
O

O
224 224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Bank 24 Bank 65 Quad 225 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 25 Bank 66 Quad 226
Bank 44 Bank 67 Quad 227 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 45 Bank 68 Quad 228 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 46 Quad 126 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 47 Quad 127 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 48 Quad 128 # IO_L#N_GC #


MGTREFCLK#P

Bank 64 Quad 224 VRP # MGTREFCLK#N

ug575_c3_17_100715

Figure 3-17: FFVA1517 Package—XCKU060 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


220
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-18

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A n n n n A
B n n V n n E n n B
C V n n E n n C
D n n V n n E n n D
E V n n E n n E
F n n V n n E n n F
G V n n E n n G
H n n V n n E n n H
J V n n E n n J
K n n V n n E n n K
L V n n E n n L
M n n V n n E n n M
N V n n E n n V N
P n n V n n E n n 15 E V P
R V n n E n n 9 E V R
V
T n n V n n 10 19 E V T
U V n n E n n 11 18 E V U
V
V V 12 E V V
V
W V E 1 20 V W
Y V 13 24 21 E Y
V
AA V E 14 17 22 23 V AA
V
AB V 16 8 7 E V AB
AC V E 4 0 E V AC
V
AD V 5 3 28 30 E V AD
AE V E 2 33 29 35 E V AE
AF V E 6 34 29 29 29 E V AF
AG V E 29 29 29 V AG
AH V E 29 29 26 AH
AJ V E 29 26 26 AJ
AK V E 29 29 26 AK
AL V E 26 26 26 27 AL
AM V E 26 26 35 AM
AN V E 26 26 26 AN
AP V E 26 26 25 AP
AR V E 26 25 25 AR
AT V E 26 25 25 25 AT
AU V E 25 25 25 AU
AV V E 25 25 36 31 AV
AW 25 37 25 32 AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_18_100715

Figure 3-18: FFVA1517 Package—XCKU060 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


221
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVA1517 (XCKU085 and XCKU115)


X-Ref Target - Figure 3-19

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

VC 66

V C 48

VC 46
3
A 3 3 19 19 21 21 24 24 21 23 23 S 21 24 S 23 23 19 22 S 24 22 17 17 A

C
3

O
232 232

VC 66

VC 68

VC 4 7
2
B G 22 24 23 23 22 21 23 23 22 21 24 23 23 S 19 24 22 24 22 20 18 16 B

V
2 2

C
2

O
232 232

VC 67

V C 47
1
C 1 1 22 20 24 S 22 20 19 24 22 20 19 21 21 19 21 24 20 20 23 20 18 16 15 C

C
1

O
232 232

VC 67

V C 48

V C 46
0 1
D 0 0 20 15 15 17 20 19 S 24 20 19 22 22 19 21 18 16 S 23 21 19 14 15 D

C
0 1

O
232 232 232

VC 66

VC 6 8

VC 46
3
E 3 3 18 18 13 17 16 18 17 17 17 18 20 20 15 17 18 16 14 13 21 19 14 13 E

C
3

O
231 231

VC 68

VC 47
2 0
F 2 2 16 16 14 13 16 18 15 17 S 18 16 16 15 17 17 15 14 13 S 7 12 13 S F

C
2 0

O
231 231 232

VC 67

VC 48

VC 46
1
G 1 1 S 14 11 11 S 13 15 15 15 16 16 18 18 17 15 11 12 9 7 11 12 8 G

C
1

O
231 231

VC 66

VC 48

V C 46
0 1
H 0 0 S 7 12 S 14 14 13 13 13 14 14 14 13 13 9 11 12 8 9 11 10 10 8 H

C
0 1

O
231 231 231

VC 66

VC 68

VC 47
3
J 3 3 7 12 9 10 12 11 11 7 12 12 S 14 11 9 7 7 8 5 5 1 2 2 J

C
3

O
230 230

V C 67

VC 47

VC 46
2 0
K 2 2 10 10 9 10 7 12 9 7 11 11 10 12 12 11 S 10 10 3 1 6 4 K

C
2 0

O
230 230 231

V C 67

VC 48

VC 46
1
L 1 1 8 8 5 7 9 9 9 S 8 8 10 9 S 5 6 3 3 3 6 4 L

C
1

O
230 230

VC 66

VC 68
0 1
M 0 0 4 3 5 8 8 10 10 8 7 7 9 5 6 1 1 M

C
0 1

O
230 230 230

VC 68

VC 47
3 3
N 3 3 4 1 3 3 3 5 5 4 4 2 8 6 1 4 3 3 N

C
3 3

O
229 229 128 128

VC 67

V C 48
2 0 1 2
P 2 2 1 6 6 2 1 1 6 5 2 4 4 6 1 4 2 P

C
2 0 1 2

O
229 229 230 128 128

V C 66

VC 48
1 1 1
R 2 2 2 6 6 6 5 3 1 2 3 3 5 2 2 2 R

C
1 1 1

O
229 229 128 128

VC 68
0 0
T 1 1 4 4 3 1 2 5 1 1 T

C
0 0

O
229 229 128 128
0 0
U 0
229
0 0
229
0
128
0
128
0 U
3 1 3
V 3
228
3
228
3
127
1
127
3 V
2 1 2
W 2
228
1
228
3
127
3
127
2 W
1 0
Y 1
228
2
228
2
127
0 2
127
2 Y
0 1
AA 1
228
1 0
228
1
127
1
127
1 AA
0 1 0
AB 0
228
0
228
0
126
1
127
0 AB
3 1 3
AC 3
227
1
227
0
127
0
126
3 AC

VC 64

VC 45
2 0
AD 3 3 24 24 21 S 24 24 19 21 3 3 AD

C
2 0

O
227 227 126 126
V C 65

V C 45
0 2
AE 2 2 23 21 S 21 23 22 22 22 21 23 19 21 23 24 21 2 2 AE
C

C
0 2
O

O
227 227 126 126

VC 44
1 1 1
AF 23 21 22 20 23 22 24 20 21 23 22 20 23 24 23 21 G AF

V
1 1

C
1 1 1

O
227 227 226 126

V C 64

VC 2 4
0 0
AG 0 0 19 22 20 19 19 24 20 19 19 22 20 24 24 23 S 1 1 AG
C

C
0 0

O
227 227 126 126
VC 65

VC 45
3 0
AH 3 3 19 17 15 17 17 20 20 S 18 18 18 17 S 22 19 20 20 0 0 AH
C

C
3 0
O

O
226 226 226 126
VC 6 5

VC 44

VC 24
2
AJ 2 2 17 15 16 15 18 18 16 16 S 18 15 17 22 19 15 17 18 S AJ
C

C
2
O

O
226 226
V C 64

VC 24

VC 25
1 1
AK 1 1 18 18 16 15 16 16 17 17 14 13 15 S 13 13 15 17 16 18 23 23 22 22 AK
C

C
1 1
O

O
226 226 225
VC 64

VC 45

VC 25
0
AL 0 0 13 14 14 S 13 14 14 15 14 13 16 16 14 14 14 13 16 S 21 21 20 20 24 AL
C

C
0
O

O
226 226
V C 65

VC 44

VC 24
3 0
AM 3 3 13 12 S S 13 12 15 12 11 8 8 12 11 14 13 12 11 17 17 19 19 24 AM
C

C
3 0
O

O
225 225 225
VC 44

VC 24
2
AN 2 2 11 11 12 S 11 11 12 12 11 9 7 12 11 9 S 12 11 7 15 14 14 16 18 AN
C

C
2
O

O
225 225
VC 64

VC 45

V C 25
1 1
AP 1 1 10 10 8 9 10 10 S 10 9 7 10 S 9 10 8 8 7 15 S 13 16 18 AP
C

C
1 1
O

O
225 225 224
V C 65

VC 44

VC 25
0
AR 0 0 9 7 8 9 7 7 8 10 8 8 10 7 7 5 10 9 9 5 13 11 12 AR
C

C
0
O

O
225 225
VC 4 4

V C 24
3 0
AT 3 3 9 7 6 4 5 5 6 8 6 5 5 3 5 6 6 5 3 6 11 12 10 AT
C

C
3 0
O

O
224 224 224
V C 64

VC 45

V C 25
2
AU 2 2 5 6 4 3 3 6 S 4 6 4 4 3 4 4 5 1 3 6 7 9 10 AU
C

C
2
O

O
224 224
VC 65

V C 45

VC 25
1
AV G 5 3 1 2 1 1 4 2 4 3 1 6 6 1 2 5 1 2 2 7 9 8 8 AV
V

1 1
C

C
1
O

O
224 224
VC 65

VC 44

VC 24
0
AW 0 0 3 1 S 2 4 2 2 2 3 1 2 2 1 2 3 3 1 1 4 4 S AW
C

C
0
O

O
224 224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Bank 24 Bank 65 Quad 225 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 25 Bank 66 Quad 226
Bank 44 Bank 67 Quad 227 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 45 Bank 68 Quad 228 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 46 Quad 126 Quad 229 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 47 Quad 127 Quad 230 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 48 Quad 128 Quad 231 # IO_L#N_GC #


MGTREFCLK#P

Bank 64 Quad 224 Quad 232 VRP # MGTREFCLK#N

ug575_c3_19_100715

Figure 3-19: FLVA1517 Package—XCKU085 and XCKU115 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


222
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-20

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A A
B V E B
C V E C
D V E D
E V E E
F V E F
G V E G
H V E H
J V E J
K V E K
L V E L
M V E M
N V E V N
P V E 15 E V P
R V E 9 E V R
V
T V 10 19 E V T
U V E 11 18 E V U
V
V V 12 E V V
V
W V E 1 20 V W
Y V 13 24 21 E Y
V
AA V E 14 17 22 23 V AA
V
AB V 16 8 7 E V AB
AC V E 4 0 E V AC
V
AD V 5 3 28 30 E V AD
AE V E 2 33 29 35 E V AE
AF V E 6 34 29 29 29 E V AF
AG V E 29 29 29 V AG
AH V E 29 29 26 AH
AJ V E 29 26 26 AJ
AK V E 29 29 26 AK
AL V E 26 26 26 27 AL
AM V E 26 26 35 AM
AN V E 26 26 26 AN
AP V E 26 26 25 AP
AR V E 26 25 25 AR
AT V E 26 25 25 25 AT
AU V E 25 25 25 AU
AV V E 25 25 36 31 AV
AW 25 37 25 32 AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_20_100715

Figure 3-20: FLVA1517 Package—XCKU085 and XCKU115 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


223
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVC1517 (XCKU095)
X-Ref Target - Figure 3-21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

V C 48

VC 45
A 3 3 20 22 24 24 23 22 24 3 3 1 2 1 1 4 23 23 19 3 3 A

C
O

O
228 129

V C 48

VC 4 5
3 3
B 20 22 21 23 23 22 21 24 6 1 4 2 3 4 2 2 22 19 24 B

C
3 3

O
228 129

VC 47

VC 46

V C 44
2 2
C 2 2 19 21 23 S 19 21 S 5 6 4 5 3 6 6 21 22 24 2 2 C

C
2 2

O
228 228 129 129

VC 48

V C 45
D 1 1 19 S 17 S 19 20 20 5 S 7 8 5 S 7 7 21 S 20 20 1 1 D

C
O

O
228 129

VC 48

VC 45
1 1
E 15 13 17 18 16 17 17 18 9 7 8 10 10 9 9 8 17 15 15 16 E

C
1 1

O
228 129

VC 47

VC 4 6

V C 44
F 0 0 16 15 14 13 18 16 14 14 18 9 12 12 10 10 12 12 8 17 18 14 16 S 0 0 F

C
O

O
228 129

VC 47

VC 46

VC 44
0 0
G 16 14 12 12 10 13 13 15 15 11 11 14 14 11 11 14 14 18 14 13 13 G

C
0 0

O
228 129

VC 48

V C 45
H 3 3 7 8 8 11 10 7 9 12 S 18 18 13 13 16 16 13 13 7 7 12 9 9 3 3 H

C
O

O
227 128

VC 47

VC 46

VC 44
3 3
J 7 9 9 11 7 9 11 12 17 15 15 S 18 18 17 15 8 8 11 12 J

C
3 3

O
227 128

VC 47

VC 46

V C 44
K 2 2 6 6 S 8 11 10 10 17 16 16 22 23 17 15 S 10 11 S 2 2 K

C
O

O
227 128

V C 48

VC 45
2 1 1 2
L 5 5 4 8 4 4 6 20 20 21 22 23 20 20 10 2 2 L

C
2 1 1 2

O
227 228 129 128

VC 48

VC 45
M 1 1 2 3 3 4 5 5 3 6 23 21 24 24 22 22 24 5 1 1 3 1 1 M

C
O

O
227 128

VC 47

VC 46

V C 44
1 0 0 1
N 2 1 1 1 3 2 2 23 19 19 S 21 24 5 6 6 3 N

C
1 0 0 1

O
227 228 129 128

V C 44
P 0 0 1 S 21 19 19 4 4 0 0 P

C
O
227 128
0 1 1 0
R 0
227
1
227 128
1
128
0 R
T 3
226
3 3
127
3 T
3 0 0 3
U 3
226
0
227 128
0
127
3 U
V 2
226
2 2
127
2 V
2 1 1 2
W 2
226
1
226 127
1
127
2 W
Y Y
1 0 0 1
AA 1
226
0
226 127
0
127
1 AA
AB 1
226
1 1
127
1 AB
0 1 1 0
AC 0
226
1
225 126
1
127
0 AC
AD 0
226
0 0
127
0 AD
3 0 0 3
AE 3
225
0
225 126
0
126
3 AE
VC 68

VC 66

VC 65
AF 3 3 2 2 2 23 S 21 22 3 3 AF
C

C
O

O
225 126
V C 67

VC 84
2 1 1 2
AG 4 5 1 1 2 6 1 1 4 24 24 23 21 19 21 23 22 AG
C

C
2 1 1 2
O

O
225 224 125 126
V C 67

VC 84
AH 2 2 4 5 1 3 1 4 4 6 3 4 5 6 20 20 21 19 23 20 20 2 2 AH
C

C
O

O
225 126
VC 68

VC 66

VC 65
1 0 0 1
AJ 2 6 3 5 5 3 3 3 5 6 22 22 19 19 24 24 S AJ
C

C
1 0 0 1
O

O
225 224 125 126
VC 67

VC 8 4
AK 1 1 2 6 9 S 7 7 10 S 8 8 10 17 18 18 16 15 16 16 18 1 1 AK
C

C
O

O
225 126
VC 67

VC 84
0 0
AL 8 9 7 7 9 12 10 8 7 12 10 9 17 14 16 S 15 14 18 13 AL
C

C
0 0
O

O
225 126
VC 68

VC 66

VC 65
AM 0 0 10 8 12 12 S 9 11 12 8 7 11 12 9 15 15 14 13 17 17 14 13 S 0 0 AM
C

C
O

O
225 126
VC 68

VC 66

VC 65
3 3
AN 10 11 11 16 16 11 14 14 18 11 14 14 16 11 11 13 10 11 11 9 9 AN
C

C
3 3
O

O
224 125
V C 67

V C 94
AP 3 3 S 14 14 18 18 S 15 13 18 18 18 13 16 9 7 12 12 7 10 12 12 S 3 3 AP
C

C
O

O
224 125
VC 68

VC 94

VC 65
2 2
AR 13 13 17 15 16 15 17 13 15 15 17 13 9 7 10 10 7 8 8 6 AR
C

C
2 2
O

O
224 125
VC 68

VC 66

V C 65
AT 2 2 17 15 22 16 17 20 20 S 17 S 20 S 8 8 6 3 4 6 2 2 AT
C

C
O

O
224 125
V C 67

V C 94

1 1
AU 1 1 19 20 22 24 S 21 22 23 23 19 20 S 5 5 6 3 4 1 1 AU
C

1 1
O

224 224 125 125


V C 67

V C 94

0 0
AV G 19 20 21 24 23 21 19 22 21 19 22 22 4 4 3 1 2 2 5 G AV
V

V
C

0 0
O

224 125
V C 68

VC 66

VC 65
AW 0 0 S 21 23 23 23 19 24 24 21 24 24 2 2 3 1 1 1 5 0 0 AW
C

C
O

O
224 125

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Bank 44 Bank 68 Quad 224 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 84 Quad 225
Bank 46 Bank 94 Quad 226 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Quad 125 Quad 227 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 48 Quad 126 Quad 228 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 65 Quad 127 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 66 Quad 128 # IO_L#N_GC #


MGTREFCLK#P

Bank 67 Quad 129 VRP # MGTREFCLK#N

ug575_c3_21_100715

Figure 3-21: FFVC1517 Package—XCKU095 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


224
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-22

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A A
B V V B
C C
D V V D
E V V E
F F
G V V G
H H
J V V J
K E E K
L V V L
M E E M
N V V N
V V
P 11 10 12 P
R V 1 V R
T E 9 E T
U V 15 6 V U
V V
V 13 14 V
W V V W
Y E E 4 19 17 24 21 E E Y
AA V 22 23 V AA
V V
AB 2 0 8 7 AB
AC V 5 18 V AC
AD E 3 20 E AD
AE E 16 E AE
V V
AF 29 29 AF
AG V 29 29 33 29 V AG
AH E 29 34 29 29 E AH
AJ V 30 28 35 V AJ
AK E 26 26 26 29 E AK
AL V 26 26 29 26 V AL
AM 29 29 26 26 27 AM
AN V 26 26 26 26 26 V AN
AP 25 26 26 26 35 AP
AR V 25 25 25 25 V AR
AT V 25 25 25 V AT
AU 25 25 25 AU
AV 31 32 25 AV
AW 36 37 25 AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_22_100715

Figure 3-22: FFVC1517 Package—XCKU095 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


225
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVD1517 (XCKU115) and RLD1517 (XQKU115)


X-Ref Target - Figure 3-23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

VC 7 3
3 3 3
A G 18 15 24 21 21 24 22 20 20 A

V
3 3 3 3

C
3 3 3

O
232 232 133 132 132

V C 72
2 3 2
B 2 2 18 15 22 24 23 24 22 23 21 3 3 2 2 B

C
2 3 2

O
232 232 233 133 132 132

VC 72
1 2 1
C 1 1 3 3 16 20 22 19 23 23 19 19 21 1 1 C

C
1 2 1

O
232 232 233 133 132 132

VC 73
0 2 0
D 0 0 S 16 20 19 S S 17 15 S 2 2 0 0 D

C
0 2 0

O
232 232 233 133 132 132

VC 73

VC 72
3 1
E 3 3 2 2 13 13 17 9 11 17 15 13 1 1 3 3 E

C
3 1

O
231 231 233 133 133 131

VC 72
2 1 1 3
F 2 2 14 14 17 9 7 11 14 13 18 0 0 F

C
2 1 1 3

O
231 231 233 133 133 131

V C 72
1 0 0
G 1 1 12 11 11 9 7 12 12 14 18 2 2 G

C
1 0 0

O
231 233 233 133 131

VC 73
0 0 2
H 1 1 0 0 12 7 9 10 10 8 8 16 16 24 24 S H

C
0 0 2

O
231 231 233 133 131

VC 73

VC 72
1
J 0 0 S 10 10 7 S 3 3 2 18 16 16 21 21 22 22 23 23 1 1 J

C
1

O
231 233 131

VC 72

VC 71
3 0 1 1
K 3 3 8 8 5 5 6 5 2 4 4 18 15 15 14 14 20 20 K

C
3 0 1 1

O
230 230 233 132 131

VC 73

VC 71
2 1
L 1 3 4 4 6 5 6 1 17 17 S S 13 13 19 19 0 0 L

C
2 1

O
230 232 131

VC 73

V C 71
1 0 0 0
M 2 2 1 3 2 2 6 1 10 10 12 12 5 5 6 M

C
1 0 0 0

O
230 230 232 132 131

VC 7 1
1
N 1 1 8 11 11 3 3 6 N

C
1

O
230 231

VC 71
0 0 1
P 0 0 8 9 9 1 1 4 4 P

C
0 0 1

O
230 230 231 131

VC 71
3 1
R 7 7 2 2 R

C
3 1

O
229 230
2 0 0
T 2
229
3
229
3 0
230 131
0 T
1
U 2
229
2 1
229
U
1
V 1
229
1
229
1 V
0 0
W 0
229
0
229
W
3 3
Y G Y

V
3 0 0 3
228 229 128
1 1
AA 3
228
3 1
228 128
1 3
128
3 AA
2 0 2
AB G AB

V
2 2 2 0 2
228 228 128 128
1 0
AC 1
228
0
228
2
128
2 AC
0 1 1 1
AD 0
228
1
228
1
1
227
23 23 S 127
1
128
1 AD
V C 84

VC 66
0
AE 0 0 21 21 S S S 23 24 24 S 10 10 1 1 AE
C

C
0
O

O
228 227 128

VC 66

VC 67
3 1 0 0
AF 3 3 19 19 22 24 23 20 20 22 18 17 16 16 23 22 22 9 9 AF

C
3 1 0 0

O
227 227 226 127 128

VC 65

VC 6 6
2 0
AG 20 22 24 23 21 22 18 17 15 15 21 21 8 8 7 0 0 AG
C

C
2 0

O
227 226 128
V C 84

V C 66
1 1 1 3
AH 2 2 20 18 18 21 19 19 24 12 14 14 13 20 20 6 12 7 AH
C

C
1 1 1 3
O

O
227 227 225 126 127
VC 8 4

VC 66
0
AJ 1 1 16 17 17 16 24 S 12 11 13 10 19 6 12 11 11 3 3 AJ
C

C
0
O

O
227 225 127
VC 65

VC 67
0 1 0 2
AK 0 0 16 14 15 15 S 16 18 9 9 11 10 19 1 3 4 4 AK
C

C
0 1 0 2
O

O
227 227 224 126 127
VC 65

VC 67
0
AL 3 3 S 14 13 13 17 15 15 18 7 7 8 8 1 3 5 5 2 2 AL
C

C
0
O

O
226 224 127

V C 66
3 1
AM 2 2 3 3 12 11 17 14 14 6 6 4 2 2 AM
C
3 1

O
226 226 224 127
V C 65

2 3
AN 2 2 12 11 9 13 13 5 2 2 4 1 1 AN
C

2 3
O

226 224 224 127


V C 94

1 2 0
AP 1 1 S 8 9 12 12 11 5 3 3 AP
C

1 2 0
O

226 226 224 127


VC 94

VC 66

0
AR 0 0 1 1 8 7 7 S 11 1 1 0 0 AR
C

0
O

226 226 224 127


VC 65

3 1 3
AT 3 3 10 10 S 10 10 9 6 6 5 3 3 AT
C

3 1 3
O

225 225 224 126 126


VC 94

2 2
AU 2 2 0 0 6 6 5 3 7 9 2 4 5 2 2 AU
C

2 2
O

225 225 224 126 126


V C 94

1 0 1
AV 1 1 4 5 3 1 7 2 4 1 3 1 1 AV
C

1 0 1
O

225 225 224 126 126


V C 65

0 0
AW G 4 2 2 1 8 8 S 1 3 AW
V

0 0 0 0
C

0 0
O

225 225 126 126

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Bank 65 Quad 126 Quad 226 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 66 Quad 127 Quad 227
Bank 67 Quad 128 Quad 228 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 71 Quad 131 Quad 229 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 72 Quad 132 Quad 230 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 73 Quad 133 Quad 231 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 84 Quad 224 Quad 232 # IO_L#N_GC #


MGTREFCLK#P

Bank 94 Quad 225 Quad 233 VRP # MGTREFCLK#N

ug575_c3_23_100715

Figure 3-23: FLVD1517 Package—XCKU115 and RLD1517 Package—XQKU115 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


226
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A E V V A
B V E E E V B
C V V E V V C
D V E E E V D
E V V E V V E
F V E E E V V F
G V V E E G
H V E V H
J V V E E J
K V E V K
L V E E E L
M V E 15 V M
N V E E 1 E n n N
P V E 9 V n n P
R V E 12 E n n R
V
T V 11 V n n T
V
U V E 10 n n U
V
V V 13 20 0 n n n n V
V
W V E 6 n n n n W
V
Y V 19 24 21 n n Y
V
AA V E 14 22 23 AA
V
AB V 16 18 17 8 7 V AB
V
AC V E 4 AC
AD V E 5 V AD
AE V E 3 35 E AE
AF V E 2 33 29 29 29 V AF
AG V E 34 29 29 E AG
AH V E 29 29 29 30 V AH
AJ V E E 26 28 E AJ
AK V E 27 26 29 V AK
AL V V E 29 26 26 29 E AL
AM V E 29 26 26 n n V AM
AN V V E 26 26 n n E AN
AP V E E 26 26 26 E n n V n n V AP
AR V V E 35 26 n n V n n V AR
AT V E E 26 26 26 25 25 25 E n n V AT
AU V V E 25 26 31 25 25 n n V V AU
AV V E E 25 32 25 36 25 E n n V AV
AW E 25 25 25 37 25 n n V V AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_24_100715

Figure 3-24: FLVD1517 Package—XCKU115 and RLD1517 Package—XQKU115


Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


227
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVB1760 (XCKU095)
X-Ref Target - Figure 3-25

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

VC 71

VC 51
A 24 24 21 23 24 24 23 23 21 21 23 23 S 23 23 24 17 17 16 G A

V
3 3

C
O

O
131

VC 70

VC 49

VC 50
3
B 22 21 23 22 22 21 S 22 22 19 S 8 10 21 24 22 15 16 B

C
3

O
131

VC 71

VC 50
2
C 22 20 19 20 19 19 21 20 24 24 19 8 10 19 21 22 15 S 18 2 2 C

C
2

O
131 131

VC 7 1

VC 51
1
D 20 19 S 20 18 17 17 20 15 17 17 11 19 20 20 13 14 18 D

C
1

O
131

VC 70

V C 49

VC 50
3 0
E 3 3 17 S 18 16 16 18 15 16 16 15 12 11 9 S 11 13 14 3 1 1 E

C
3 0

O
231 231 131 131

VC 49

VC 50
2
F 2 2 17 16 16 18 14 14 13 15 S 18 18 12 9 9 9 11 12 3 1 F

C
2

O
231 231

V C 71

VC 50
1 1 3
G 1 1 15 14 14 10 12 13 S 14 14 13 6 6 7 10 10 12 2 1 0 0 G

C
1 1 3

O
231 231 231 131 130

VC 70

VC 51
0
H 0 0 15 13 13 10 12 11 11 12 11 11 13 5 7 S 7 8 2 5 6 3 3 H

C
0

O
231 231 130

VC 70

VC 49

V C 50
3 2
J 3 3 10 10 12 12 11 8 9 S 10 12 9 S 4 5 7 8 5 6 2 2 J

C
3 2

O
230 230 130 130

VC 71

VC 48
2 0
K 8 8 9 9 11 8 7 9 8 10 7 9 4 3 3 15 17 17 4 4 1 1 K

C
2 0

O
230 231 130

VC 71

VC 51
1 1 1
L 2 2 6 5 7 7 S 7 6 6 8 7 6 6 2 1 15 16 13 10 10 9 L

C
1 1 1

O
230 230 131 130

VC 70

VC 49

VC 48
1
M 1 1 6 4 5 1 3 3 5 4 5 5 3 4 2 1 16 13 11 12 9 0 0 M

C
1

O
230 230 130

VC 70

VC 49

VC 48
0 0 0
N 0 0 4 3 3 1 1 5 2 4 1 3 2 4 18 18 14 14 11 12 8 7 N

C
0 0 0

O
230 230 131 130

VC 71

VC 48
3 0
P 2 2 1 2 1 2 S 23 23 19 S 8 7 3 3 P

C
3 0

O
229 230 129

VC 48
2 1 3
R 3 3 S 21 19 6 6 R

C
2 1 3

O
229 229 130 129

VC 48
1
T 2 2 21 24 20 3 5 5 2 2 T

C
1

O
229 229 129

VC 48
1 0 2
U 1 1 24 20 2 3 1 U

C
1 0 2

O
229 229 130 129
0
V 0
229
0
0
229
22 22 2 4 4 1 1
129
1 V

VC 47
0 1 1
W 3 3 24 19 19 18 16 16 W

C
0 1 1

O
229 228 129 129

V C 47
3 1
Y 22 24 21 18 15 15 0 0 Y

C
3 1

O
228 228 129
2 0 0
AA 2
228
2
228
2 22 23 23 21 14 14 17 129
0
129
0 AA

VC 47
1 0
AB S 20 20 13 13 17 3 3 AB

C
1 0

O
228 228 128

VC 47
0 1 3
AC 1 1 6 6 11 12 12 S AC

C
0 1 3

O
228 228 128 128

V C 47
1
AD 0 0 3 4 4 11 10 10 2 2 AD

C
1

O
228 227 128

V C 47
3 0 2
AE 3 3 3 2 2 S 8 AE

C
3 0 2

O
227 227 128 128

V C 47
0
AF 2 2 1 1 5 5 9 8 7 1 1 AF

C
0

O
227 227 128

VC 46
2 1
AG 1 1 24 24 23 23 21 16 16 18 9 7 AG

C
2 1

O
227 227 128
VC 66

VC 67
1 1
AH 23 23 21 S 7 4 3 20 S 24 21 17 17 18 S 24 22 0 0 AH
C

C
1 1
O

O
227 226 128
VC 66

VC 67

VC 46
0 0
AJ 0 0 22 22 21 9 9 7 2 2 4 3 14 20 22 24 15 15 14 14 24 22 AJ
C

C
0 0
O

O
227 227 128
VC 67

VC 46

V C 45
3 0
AK 20 20 19 19 12 12 S 8 1 1 5 14 22 19 19 S 13 13 21 19 20 20 23 23 AK
C

C
3 0
O

O
226 226
V C 66

VC 67

V C 46
2
AL 3 3 17 13 13 11 11 10 8 6 6 5 13 13 17 S 12 12 21 19 23 23 19 19 21 17 S AL
C

C
2
O

O
226 226
V C 66

V C 67

V C 46
1
AM 2 2 17 15 18 14 5 3 10 7 9 11 11 S 17 15 10 11 11 1 4 6 6 22 21 17 15 15 AM
C

C
1
O

O
226 225
VC 66

V C 67

VC 46

V C 45
1
AN 1 1 15 18 14 5 3 1 7 9 12 12 16 15 10 9 9 7 1 3 4 S 22 24 13 18 18 AN
C

C
1
O

O
226 226
VC 66

VC 65

V C 45
0
AP 0 0 S 6 6 1 2 8 8 10 S 16 18 18 S 8 8 7 2 3 5 24 13 14 16 AP
C

C
0
O

O
226 226
VC 84

VC 65

VC 46
3 0
AR 3 3 16 16 4 4 2 2 10 5 5 24 23 5 2 5 20 20 8 14 16 9 AR
C

C
3 0
O

O
225 225 225
VC 9 4

VC 44

V C 45
2
AT 2 2 23 23 21 S 5 3 3 2 6 6 3 3 24 23 2 2 3 5 15 17 7 8 11 11 9 AT
C

C
2
O

O
225 225
V C 94

V C 65

VC 45
1 1
AU 1 1 19 21 24 24 5 4 4 4 1 20 20 19 21 4 4 3 15 17 18 7 12 12 10 10 AU
C

C
1 1
O

O
225 225 224
VC 84

VC 65

VC 44
0
AV 0 0 19 22 22 20 20 1 6 2 2 4 1 22 22 19 21 1 1 13 13 16 18 S 5 5 AV
C

C
0
O

O
225 225
VC 84

VC 65

VC 44

VC 45
3 0
AW 3 3 13 13 14 11 1 6 S 8 12 11 11 13 17 17 6 6 14 14 S 16 23 1 3 3 AW
C

C
3 0
O

O
224 224 224
VC 94

VC 44

V C 45
2
AY 2 2 15 15 14 11 12 12 8 8 7 12 14 14 13 15 12 12 11 11 22 19 19 23 1 6 6 AY
C

C
2
O

O
224 224
VC 94

VC 65

VC 44
1
BA G 17 18 18 16 9 7 7 8 7 9 9 16 S 15 8 10 9 9 S 22 21 21 4 2 2 BA
V

1 1
C

C
1
O

O
224 224
VC 84

VC 65

VC 44
0
BB 0 0 17 16 S S 9 10 10 10 10 S 16 18 18 8 10 7 7 20 20 24 24 S 4 BB
C

C
0
O

O
224 224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Bank 44 Bank 65 Quad 129 Quad 229 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 66 Quad 130 Quad 230
Bank 46 Bank 67 Quad 131 Quad 231 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Bank 70 Quad 224 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 48 Bank 71 Quad 225 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 49 Bank 84 Quad 226 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 50 Bank 94 Quad 227 # IO_L#N_GC #


MGTREFCLK#P

Bank 51 Quad 128 Quad 228 VRP # MGTREFCLK#N

ug575_c3_25_100715

Figure 3-25: FFVB1760 Package—XCKU095 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


228
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-26

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A n n n n n n A
B n n E n n E V V B
C n n V n n E n n C
D V n n V n n E V D
E V E n n E
F E E V V F
G V E V G
H V E E H
J V E V J
K V E K
L V E V L
M V E E M
N V E V N
V
P V P
V
R V 6 V R
T V E 15 E T
U V E 1 19 V U
V
V V 9 V
V
W V 10 18 V W
Y V 11 E Y
AA V E 12 20 24 21 V AA
V
AB V 13 22 23 AB
V
AC V 14 0 8 7 V AC
AD V E 16 E AD
AE V E 4 17 V AE
AF V 5 E AF
V
AG V 3 n n V AG
AH V E 2 E AH
AJ E AJ
AK V AK
AL V E AL
AM V E AM
AN V E AN
AP V 35 AP
AR V E 25 25 30 33 AR
AT V E E 25 25 25 25 28 34 AT
AU E 25 25 36 29 29 29 29 AU
AV V E 31 32 25 37 29 29 29 29 AV
AW V E 25 26 26 26 26 29 29 AW
AY V E E 25 25 26 26 26 26 26 AY
BA V E 25 26 26 26 27 26 BA
BB 26 26 35 26 29 29 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_26_100715

Figure 3-26: FFVB1760 Package—XCKU095 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


229
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVB1760 (XCKU085)
X-Ref Target - Figure 3-27

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

VC 50

VC 53
A G 24 24 21 23 24 24 23 23 21 21 23 23 23 23 24 17 17 16 G A

V
C

C
O

O
VC 49

V C 51

VC 5 2
B 22 21 23 22 22 21 S 22 22 19 S 21 24 22 15 16 B

C
O

O
V C 50

VC 52
C 22 20 19 20 19 19 21 20 24 24 19 19 21 22 15 S 18 C

C
O

O
VC 50

VC 53
D 20 19 S 20 18 17 17 20 15 17 17 19 20 20 13 14 18 D

C
O

O
VC 49

VC 51

V C 52
3
E 3 3 17 S 18 16 16 18 15 16 16 15 S 11 13 14 3 E

C
3

O
232 232

VC 51

VC 52
2
F 2 2 17 16 16 18 14 14 13 15 S 18 18 9 9 11 12 3 1 F

C
2

O
232 232

VC 5 0

VC 52
1 1 3
G 1 1 15 14 14 10 12 13 S 14 14 13 10 10 12 2 1 G

C
1 1 3

O
232 232 232 132

V C 49

VC 53
0
H 0 0 15 13 13 10 12 11 11 12 11 11 13 S 7 8 2 5 6 3 3 H

C
0

O
232 232 132

VC 49

VC 51

VC 52
3 2
J 3 3 10 10 12 12 11 8 9 S 10 12 9 S 7 8 5 6 2 2 J

C
3 2

O
231 231 132 132

VC 50

VC 48
2 0
K 8 8 9 9 11 8 7 9 8 10 7 9 15 17 17 4 4 1 1 K

C
2 0

O
231 232 132

V C 50

VC 53
1 1
L 2 2 6 5 7 7 S 7 6 6 8 7 6 6 15 16 13 10 10 9 L

C
1 1

O
231 231 132

VC 49

VC 51

V C 48
1
M 1 1 6 4 5 1 3 3 5 4 5 5 3 4 16 13 11 12 9 0 0 M

C
1

O
231 231 132

VC 49

V C 51

VC 48
0 0
N 0 0 4 3 3 1 1 5 2 4 1 3 2 4 18 18 14 14 11 12 8 7 N

C
0 0

O
231 231 132

VC 50

VC 48
3 0
P 2 2 1 2 1 2 S 23 23 19 S 8 7 3 3 P

C
3 0

O
230 231 131

V C 48
2 1 3
R 3 3 S 21 19 6 6 R

C
2 1 3

O
230 230 132 131

VC 48
1
T 2 2 21 24 20 3 5 5 2 2 T

C
1

O
230 230 131

VC 4 8
1 0 2
U 1 1 24 20 2 3 1 U

C
1 0 2

O
230 230 132 131
0
V 0
230
0
0
230
22 22 2 4 4 1 1
131
1 V

VC 47
0 1 1
W 3 3 24 19 19 18 16 16 W

C
0 1 1

O
230 228 131 131

VC 47
3 1
Y 22 24 21 18 15 15 0 0 Y

C
3 1

O
228 228 131
2 0 0
AA 2
228
2
228
2 22 23 23 21 14 14 17 131
0
131
0 AA

VC 4 7
1 0
AB S 20 20 13 13 17 3 3 AB

C
1 0

O
228 228 128

VC 47
0 1 3
AC 1 1 6 6 11 12 12 S AC

C
0 1 3

O
228 228 128 128

V C 47
1
AD 0 0 3 4 4 11 10 10 2 2 AD

C
1

O
228 227 128

VC 47
3 0 2
AE 3 3 3 2 2 S 8 AE

C
3 0 2

O
227 227 128 128

VC 47
0
AF 2 2 1 1 5 5 9 8 7 1 1 AF

C
0

O
227 227 128

VC 46
2 1
AG 24 24 23 23 21 16 16 18 9 7 G AG

V
1 1

C
2 1

O
227 227 128
V C 66

VC 67
1 1
AH 23 23 21 S 7 4 3 20 S 24 21 17 17 18 S 24 22 0 0 AH
C

C
1 1
O

O
227 226 128
VC 66

VC 67

VC 46
0 0
AJ 0 0 22 22 21 9 9 7 2 2 4 3 14 20 22 24 15 15 14 14 24 22 AJ
C

C
0 0
O

O
227 227 128
VC 67

VC 46

VC 45
3 0
AK 20 20 19 19 12 12 S 8 1 1 5 14 22 19 19 S 13 13 21 19 20 20 23 23 AK
C

C
3 0
O

O
226 226
VC 66

V C 67

VC 46
2
AL 3 3 17 13 13 11 11 10 8 6 6 5 13 13 17 S 12 12 21 19 23 23 19 19 21 17 S AL
C

C
2
O

O
226 226
VC 66

VC 67

VC 46
1
AM 2 2 17 15 18 14 5 3 10 7 9 11 11 S 17 15 10 11 11 1 4 6 6 22 21 17 15 15 AM
C

C
1
O

O
226 225
VC 66

VC 67

VC 46

V C 45
1
AN 1 1 15 18 14 5 3 1 7 9 12 12 16 15 10 9 9 7 1 3 4 S 22 24 13 18 18 AN
C

C
1
O

O
226 226
VC 66

V C 65

VC 45
0
AP 0 0 S 6 6 1 2 8 8 10 S 16 18 18 S 8 8 7 2 3 5 24 13 14 16 AP
C

C
0
O

O
226 226
VC 84

V C 65

VC 46
3 0
AR 3 3 16 16 4 4 2 2 10 5 5 24 23 5 2 5 20 20 8 14 16 9 AR
C

C
3 0
O

O
225 225 225
VC 94

VC 44

V C 45
2
AT 2 2 23 23 21 S 5 3 3 2 6 6 3 3 24 23 2 2 3 5 15 17 7 8 11 11 9 AT
C

C
2
O

O
225 225
VC 94

VC 65

VC 45
1 1
AU 1 1 19 21 24 24 5 4 4 S 4 1 20 20 19 21 4 4 3 15 17 18 7 12 12 10 10 AU
C

C
1 1
O

O
225 225 224
VC 84

VC 65

VC 44
0
AV 0 0 19 22 22 20 20 1 6 2 2 4 1 22 22 19 21 1 1 13 13 16 18 S 5 5 AV
C

C
0
O

O
225 225
V C 84

VC 65

VC 44

VC 45
3 0
AW 3 3 13 13 14 11 1 6 S 8 12 11 11 13 17 17 6 6 14 14 S 16 23 1 3 3 AW
C

C
3 0
O

O
224 224 224
VC 94

VC 44

VC 45
2
AY 2 2 15 15 14 11 12 12 8 8 7 12 14 14 13 15 12 12 11 11 22 19 19 23 1 6 6 AY
C

C
2
O

O
224 224
VC 94

VC 65

VC 44
1
BA G 17 18 18 16 9 7 7 8 7 9 9 16 S 15 8 10 9 9 S 22 21 21 4 2 2 BA
V

1 1
C

C
1
O

O
224 224
VC 84

V C 65

VC 44
0
BB 0 0 17 16 S S 9 10 10 10 10 S 16 18 18 8 10 7 7 20 20 24 24 S 4 BB
C

C
0
O

O
224 224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Bank 44 Bank 52 Quad 132 Quad 232 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 65 Quad 224
Bank 46 Bank 66 Quad 225 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Bank 67 Quad 226 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 48 Bank 84 Quad 227 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 49 Bank 94 Quad 228 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 50 Quad 128 Quad 230 # IO_L#N_GC #


MGTREFCLK#P

Bank 51 Quad 131 Quad 231 VRP # MGTREFCLK#N

ug575_c3_27_100715

Figure 3-27: FLVB1760 Package—XCKU085 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


230
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-28

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A n n n n n n n A
B n n E n n E n n V n n V B
C n n V n n E n n n n n n n n C
D V n n V n n E n V n n D
E V E n n n n n n n n n E
F E E n n V V F
G V E n n n n n V G
H V E n n E H
J V E n n V J
K V n n n E K
L V E n n n n V L
M V E n n n E M
N V E n n V N
V
P V n P
V
R V 6 V R
T V E 15 E T
U V E 1 19 V U
V
V V 9 V
V
W V 10 18 V W
Y V 11 E Y
AA V E 12 20 24 21 V AA
V
AB V 13 22 23 AB
V
AC V 14 0 8 7 V AC
AD V E 16 E AD
AE V E 4 17 V AE
AF V 5 E AF
V
AG V 3 V AG
AH V E 2 E AH
AJ E AJ
AK V AK
AL V E AL
AM V E AM
AN V E AN
AP V 35 AP
AR V E 25 25 30 33 AR
AT V E E 25 25 25 25 28 34 AT
AU E 25 25 36 29 29 29 29 AU
AV V E 31 32 25 37 29 29 29 29 AV
AW V E 25 26 26 26 26 29 29 AW
AY V E E 25 25 26 26 26 26 26 AY
BA V E 25 26 26 26 27 26 BA
BB 26 26 35 26 29 29 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_28_100715

Figure 3-28: FLVB1760 Package—XCKU085 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


231
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVB1760 (XCKU115)
X-Ref Target - Figure 3-29

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

VC 50

VC 53
3
A G 24 24 21 23 24 24 23 23 21 21 23 23 S 23 23 24 17 17 16 G A

V
3 3 3 3

C
3

O
233 233 133

VC 49

V C 51

VC 52
2 3
B 2 2 22 21 23 22 22 21 S 22 22 19 S 8 10 21 24 22 15 16 B

C
2 3

O
233 233 133

V C 50

VC 5 2
1 1 2
C 1 1 22 20 19 20 19 19 21 20 24 24 19 8 10 19 21 22 15 S 18 2 2 C

C
1 1 2

O
233 233 233 133 133

VC 50

V C 53
0 1
D 0 0 20 19 S 20 18 17 17 20 15 17 17 11 19 20 20 13 14 18 D

C
0 1

O
233 233 133

V C 49

VC 51

VC 52
3 0 0
E 3 3 17 S 18 16 16 18 15 16 16 15 12 11 9 S 11 13 14 3 1 1 E

C
3 0 0

O
232 232 233 133 133

VC 51

VC 52
2
F 2 2 17 16 16 18 14 14 13 15 S 18 18 12 9 9 9 11 12 3 1 F

C
2

O
232 232

VC 50

VC 52
1 1 3
G 1 1 15 14 14 10 12 13 S 14 14 13 6 6 7 10 10 12 2 1 0 0 G

C
1 1 3

O
232 232 232 133 132

VC 49

V C 53
0
H 0 0 15 13 13 10 12 11 11 12 11 11 13 5 7 S 7 8 2 5 6 3 3 H

C
0

O
232 232 132

V C 49

V C 51

VC 52
3 2
J 3 3 10 10 12 12 11 8 9 S 10 12 9 S 4 5 7 8 5 6 2 2 J

C
3 2

O
231 231 132 132

VC 50

VC 48
2 0
K 8 8 9 9 11 8 7 9 8 10 7 9 4 3 3 15 17 17 4 4 1 1 K

C
2 0

O
231 232 132

VC 50

V C 53
1 1 1
L 2 2 6 5 7 7 S 7 6 6 8 7 6 6 2 1 15 16 13 10 10 9 L

C
1 1 1

O
231 231 133 132

V C 49

VC 51

VC 48
1
M 1 1 6 4 5 1 3 3 5 4 5 5 3 4 2 1 16 13 11 12 9 0 0 M

C
1

O
231 231 132

VC 49

VC 51

VC 48
0 0 0
N 0 0 4 3 3 1 1 5 2 4 1 3 2 4 18 18 14 14 11 12 8 7 N

C
0 0 0

O
231 231 133 132

VC 50

VC 48
3 0
P 2 2 1 2 1 2 S 23 23 19 S 8 7 3 3 P

C
3 0

O
230 231 131

VC 48
2 1 3
R 3 3 S 21 19 6 6 R

C
2 1 3

O
230 230 132 131

V C 48
1
T 2 2 21 24 20 3 5 5 2 2 T

C
1

O
230 230 131

V C 48
1 0 2
U 1 1 24 20 2 3 1 U

C
1 0 2

O
230 230 132 131
0
V 0
230
0 0
230
22 22 2 4 4 1 1
131
1 V

VC 47
0 1 1
W 3 3 24 19 19 18 16 16 W

C
0 1 1

O
230 228 131 131

VC 47
3 1
Y 22 24 21 18 15 15 0 0 Y

C
3 1

O
228 228 131
2 0 0
AA 2
228
2
228
2 22 23 23 21 14 14 17 131
0
131
0 AA

VC 47
1 0
AB S 20 20 13 13 17 3 3 AB

C
1 0

O
228 228 128

VC 47
0 1 3
AC 1 1 6 6 11 12 12 S AC

C
0 1 3

O
228 228 128 128

V C 47
1
AD 0 0 3 4 4 11 10 10 2 2 AD

C
1

O
228 227 128

V C 47
3 0 2
AE 3 3 3 2 2 S 8 AE

C
3 0 2

O
227 227 128 128

V C 47
0
AF 2 2 1 1 5 5 9 8 7 1 1 AF

C
0

O
227 227 128

VC 46
2 1
AG 24 24 23 23 21 16 16 18 9 7 G AG

V
1 1

C
2 1

O
227 227 128
V C 66

V C 67
1 1
AH 23 23 21 S 7 4 3 20 S 24 21 17 17 18 S 24 22 0 0 AH
C

C
1 1
O

O
227 226 128
VC 66

V C 67

VC 4 6
0 0
AJ 0 0 22 22 21 9 9 7 2 2 4 3 14 20 22 24 15 15 14 14 24 22 AJ
C

C
0 0
O

O
227 227 128
VC 67

VC 46

VC 45
3 0
AK 20 20 19 19 12 12 S 8 1 1 5 14 22 19 19 S 13 13 21 19 20 20 23 23 AK
C

C
3 0
O

O
226 226
V C 66

VC 67

VC 46
2
AL 3 3 17 13 13 11 11 10 8 6 6 5 13 13 17 S 12 12 21 19 23 23 19 19 21 17 S AL
C

C
2
O

O
226 226
VC 66

V C 67

VC 46
1
AM 2 2 17 15 18 14 5 3 10 7 9 11 11 S 17 15 10 11 11 1 4 6 6 22 21 17 15 15 AM
C

C
1
O

O
226 225
V C 66

VC 67

VC 46

VC 4 5
1
AN 1 1 15 18 14 5 3 1 7 9 12 12 16 15 10 9 9 7 1 3 4 S 22 24 13 18 18 AN
C

C
1
O

O
226 226
VC 66

VC 65

VC 45
0
AP 0 0 S 6 6 1 2 8 8 10 S 16 18 18 S 8 8 7 2 3 5 24 13 14 16 AP
C

C
0
O

O
226 226
VC 8 4

VC 65

V C 46
3 0
AR 3 3 16 16 4 4 2 2 10 5 5 24 23 5 2 5 20 20 8 14 16 9 AR
C

C
3 0
O

O
225 225 225
VC 94

V C 44

VC 45
2
AT 2 2 23 23 21 S 5 3 3 2 6 6 3 3 24 23 2 2 3 5 15 17 7 8 11 11 9 AT
C

C
2
O

O
225 225
VC 94

VC 65

VC 45
1 1
AU 1 1 19 21 24 24 5 4 4 S 4 1 20 20 19 21 4 4 3 15 17 18 7 12 12 10 10 AU
C

C
1 1
O

O
225 225 224
VC 84

VC 65

VC 44
0
AV 0 0 19 22 22 20 20 1 6 2 2 4 1 22 22 19 21 1 1 13 13 16 18 S 5 5 AV
C

C
0
O

O
225 225
V C 84

VC 65

VC 44

VC 45
3 0
AW 3 3 13 13 14 11 1 6 S 8 12 11 11 13 17 17 6 6 14 14 S 16 23 1 3 3 AW
C

C
3 0
O

O
224 224 224
VC 94

VC 44

VC 4 5
2
AY 2 2 15 15 14 11 12 12 8 8 7 12 14 14 13 15 12 12 11 11 22 19 19 23 1 6 6 AY
C

C
2
O

O
224 224
VC 94

VC 65

VC 44
1
BA G 17 18 18 16 9 7 7 8 7 9 9 16 S 15 8 10 9 9 S 22 21 21 4 2 2 BA
V

1 1
C

C
1
O

O
224 224
VC 84

V C 65

VC 44

0
BB 0 0 17 16 S S 9 10 10 10 10 S 16 18 18 8 10 7 7 20 20 24 24 S 4 BB
C

0
O

224 224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Bank 44 Bank 52 Quad 131 Quad 230 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 53 Quad 132 Quad 231
Bank 46 Bank 65 Quad 133 Quad 232 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Bank 66 Quad 224 Quad 233 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#
V

Bank 48 Bank 67 Quad 225 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 49 Bank 84 Quad 226 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 50 Bank 94 Quad 227 # IO_L#N_GC #


MGTREFCLK#P

Bank 51 Quad 128 Quad 228 VRP # MGTREFCLK#N

ug575_c3_29_100715

Figure 3-29: FLVB1760 Package—XCKU115 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


232
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-30

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A A
B E E V V B
C V E C
D V V E V D
E V E E
F E E V V F
G V E V G
H V E E H
J V E V J
K V E K
L V E V L
M V E E M
N V E V N
V
P V P
V
R V 6 V R
T V E 15 E T
U V E 1 19 V U
V
V V 9 V
V
W V 10 18 V W
Y V 11 E Y
AA V E 12 20 24 21 V AA
V
AB V 13 22 23 AB
V
AC V 14 0 8 7 V AC
AD V E 16 E AD
AE V E 4 17 V AE
AF V 5 E AF
V
AG V 3 V AG
AH V E 2 E AH
AJ E AJ
AK V AK
AL V E AL
AM V E AM
AN V E AN
AP V 35 AP
AR V E 25 25 30 33 AR
AT V E E 25 25 25 25 28 34 AT
AU E 25 25 36 29 29 29 29 AU
AV V E 31 32 25 37 29 29 29 29 AV
AW V E 25 26 26 26 26 29 29 AW
AY V E E 25 25 26 26 26 26 26 AY
BA V E 25 26 26 26 27 26 BA
BB 26 26 35 26 29 29 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_30_100715

Figure 3-30: FLVB1760 Package—XCKU115 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


233
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVD1924 (XCKU115)
X-Ref Target - Figure 3-31

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

V C 73

VC 53

VC 51
A G 10 10 S 22 22 21 21 22 22 S 24 20 20 S 22 20 S 22 22 21 24 24 23 18 G A

V
C

C
O

O
V C 71

V C 72

VC 51
3
B 9 9 20 19 24 24 19 19 24 24 23 23 24 22 21 20 23 20 20 21 23 22 22 18 3 3 B

C
3

O
233 133

VC 71

VC 72

VC 52
2 3
C 3 3 7 7 20 19 23 23 20 21 21 24 22 21 21 24 21 19 24 23 19 19 21 20 17 S 16 15 C

C
2 3

O
233 233 133

V C 73

VC 53

VC 51
D 2 2 8 11 12 12 16 S 18 20 23 23 S 22 19 23 23 19 24 S 16 17 21 20 19 17 16 15 2 2 D

C
O

O
233 133

VC 71

VC 53

VC 51
1 2
E 1 1 8 11 13 13 16 16 18 15 15 17 15 15 19 17 17 15 18 16 17 15 S 19 14 14 13 E

C
1 2

O
233 233 133

VC 71

VC 72

VC 52
0
F 3 4 14 15 15 16 14 14 17 17 18 18 18 13 15 18 14 13 15 S 11 11 13 6 6 1 1 F

C
0

O
233 133

VC 71

VC 73

VC 52

VC 51
3 1
G 0 0 3 4 5 14 18 S 13 13 17 13 13 16 18 13 14 16 14 13 12 10 10 12 12 4 5 G

C
3 1

O
232 233 133

V C 73

VC 53

VC 51
H 3 3 1 2 5 17 17 18 11 12 12 S 14 14 16 S 14 16 11 11 12 10 10 8 9 4 5 3 0 0 H

C
O

O
232 133

VC 71

V C 72

VC 52
2 0
J 2 2 1 2 6 6 S 7 11 10 S 11 12 8 S 11 12 9 9 7 8 8 9 7 2 3 J

C
2 0

O
232 232 133

VC 70

V C 72

VC 52

VC 51
K 1 1 21 24 S 18 18 8 7 9 10 11 12 7 8 11 12 9 S 7 8 21 19 S 7 2 3 3 K

C
O

O
232 132

VC 73

V C 53

VC 5 0
1 1 3
L 21 23 24 16 16 17 8 9 S 10 9 7 10 10 8 9 6 6 2 21 19 24 17 15 1 1 L

C
1 1 3

O
232 233 132

VC 70

VC 53

VC 50
M 0 0 22 23 14 14 17 6 3 3 10 9 4 2 8 7 7 4 2 23 22 24 17 15 18 2 2 M

C
O

O
232 132

VC 70

V C 72

VC 52
0 0 1 2
N 19 22 13 13 15 15 6 5 5 1 4 2 6 4 5 5 5 4 23 22 20 20 16 18 N

C
0 0 1 2

O
232 233 133 132

V C 73

VC 52

VC 50
P 3 3 19 20 20 11 12 S 4 4 2 1 3 5 6 4 5 3 3 3 10 11 13 14 14 16 1 1 P

C
O

O
231 132

VC 70

VC 53

V C 50
3 1 0 1
R S 11 10 12 9 1 1 2 3 5 6 2 1 3 1 1 10 11 12 13 S R

C
3 1 0 1

O
231 232 133 132

VC 70

VC 72

VC 50
0 1
T 2 2 3 6 10 8 9 6 2 1 9 7 12 6 6 4 0 0 T

C
0 1

O
231 232 132 132
2 0
U 2
231
1
231
1 3 4 6 8 9 7 8 8 2 4 3
131
3
132
0 U

VC 5 0
1 1 0 3
V 4 5 7 7 S 5 5 2 V

C
1 1 0 3

O
231 231 132 131

VC 70

VC 50
0 2
W 0 0 2 2 5 3 3 1 2 2 W
C

C
0 2
O

O
231 231 131 131
0 1
Y 3
227
3 0
231
S 1 1 1 131
1 1
131
1 Y
3 1
AA 3
227
2
227
2 0
131
0
131
1 AA
2 1 0 0
AB 2
227
1
227 131
0
131
0 AB
1 3
AC 1
227
1
227
1 24 3
128
3
128
3 AC
0 1
AD 0
227
0
0
227
S 24 128
1
2
128
2 AD

V C 47
0 2
AE 3 3 23 23 21 22 1 1 AE

C
0 2

O
227 226 128 128
VC 67

VC 47
3 1 0 1
AF 22 24 S 19 21 20 22 AF
C

C
3 1 0 1
O

O
226 226 128 128
2 0
AG 2
226
2
226
2 22 20 24 18 17 17 19 20 S 0
128
0
128
0 AG

VC 47
0 1 3
AH 1 1 20 23 23 18 14 11 9 9 AH

C
0 1 3

O
226 226 127 127
VC 67

VC 84

VC 4 7
1 2
AJ 0 0 19 19 21 21 S 24 S 23 24 S 24 15 16 16 14 11 7 7 3 3 AJ
C

C
1 2
O

O
226 226 127 127
V C 65

V C 47
0 1 0
AK S 17 17 16 18 24 22 22 23 22 22 24 20 24 22 15 13 13 12 12 10 2 2 AK
C

C
0 1 0
O

O
226 225 127 127
VC 65

VC 45
3 0 1 1
AL 15 14 16 18 7 20 20 21 21 20 20 S 20 22 24 24 5 8 8 10 AL
C

C
3 0 1 1
O

O
225 225 126 127
V C 67

VC 84

V C 47
AM 3 3 6 15 14 13 11 7 23 23 21 21 19 19 23 23 21 21 23 22 22 5 3 1 1 4 1 1 AM
C

C
O

O
225 127
VC 67

VC 84

V C 44
2 1 0 0
AN 4 6 13 12 12 11 19 19 16 16 17 17 18 18 19 19 S 23 19 20 3 6 4 AN
C

C
2 1 0 0
O

O
225 224 126 127
V C 65

VC 45

VC 47
AP 2 2 4 3 2 5 8 8 9 17 18 18 S 13 18 18 16 16 21 21 17 19 20 2 2 6 0 0 AP
C

C
O

O
225 127
VC 67

VC 45

VC 46
1 0 3
AR 3 2 5 10 10 9 17 14 14 15 13 14 16 14 17 17 16 18 17 15 15 S 23 23 21 AR
C

C
1 0 3
O

O
225 224 126
VC 67

VC 8 4

V C 44
AT 1 1 1 1 S S 23 13 13 15 15 14 16 S 14 15 16 14 18 13 S 19 19 24 24 21 3 3 AT
C

C
O

O
225 126
VC 66

VC 6 5

VC 44

VC 46
0 2
AU 0 0 17 17 21 21 23 22 S 12 15 12 12 9 13 13 15 14 11 11 13 20 20 22 22 17 AU
C

C
0 2
O

O
225 225 126
V C 66

VC 45

VC 46
AV 3 3 15 15 24 19 19 22 S 12 11 7 10 11 11 9 11 11 S S 12 12 10 S 13 18 18 17 2 2 AV
C

C
O

O
224 126
VC 66

VC 94

VC 44
3 1
AW 2 2 18 18 13 24 20 20 2 10 11 7 S 10 7 7 10 12 7 9 9 8 10 16 16 13 15 15 AW
C

C
3 1
O

O
224 224 126
VC 66

VC 94

VC 44

VC 46
2
AY S 13 14 14 6 2 10 8 9 8 8 5 5 10 12 9 7 7 7 8 14 14 11 11 1 1 AY
C

C
2
O

O
224 126
V C 65

VC 45

VC 46
1 0
BA 1 1 16 16 9 11 6 4 5 8 9 5 6 2 S 8 8 9 6 5 1 3 3 12 9 S BA
C

C
1 0
O

O
224 224 126
VC 66

VC 94

VC 46

0
BB 9 12 12 11 4 5 6 6 5 6 2 3 6 6 5 3 2 6 3 5 1 5 8 12 9 0 0 BB
C

0
O

224 126
V C 66

VC 94

VC 44

BC 0 0 7 7 10 3 3 1 4 4 3 1 4 3 1 4 5 3 1 2 1 3 2 4 5 8 10 7 BC
C

C
O

224
V C 65

VC 45

BD G 8 8 10 S 1 2 2 3 1 S 4 1 4 2 2 1 4 4 1 2 4 6 6 VC 46 10 7 G BD
V

V
C

C
O

O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Bank 44 Bank 65 Bank 94 Quad 225 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 66 Quad 126 Quad 226
Bank 46 Bank 67 Quad 127 Quad 227 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Bank 70 Quad 128 Quad 231 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#
V

Bank 50 Bank 71 Quad 131 Quad 232 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 51 Bank 72 Quad 132 Quad 233 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 52 Bank 73 Quad 133 # IO_L#N_GC #


MGTREFCLK#P

Bank 53 Bank 84 Quad 224 VRP # MGTREFCLK#N

ug575_c3_31_100715

Figure 3-31: FLVD1924 Package—XCKU115 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


234
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-32

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A A
B E B
C V V C
D V E V D
E E E E
F V E V F
G V V G
H V E V H
J V E J
K V E V K
L V V L
M V E V M
N V E N
P V E E V P
R V 10 V R
T V E 12 E V T
V
U V 11 E E U
V V E 1 E V V
V V
W V 9 V W
Y V E 15 E V Y
V
AA V E E AA
AB V E 6 19 18 E V AB
AC V E 13 17 24 21 E E AC
AD V E 14 0 20 22 23 E V AD
V V
AE V 8 7 V AE
AF V E 16 E V AF
V V
AG V 5 E AG
AH V E 4 E V AH
AJ V E 3 30 35 E V AJ
AK V E 2 28 29 29 E V AK
AL V 29 29 29 E AL
AM V E 34 33 29 E V AM
AN V 29 29 26 26 V AN
AP V E 29 29 29 V AP
AR V 29 26 26 E AR
AT V E 26 26 26 V AT
AU V 27 26 26 V AU
AV V E 35 26 26 25 V AV
AW V 26 26 25 E AW
AY V E 26 25 26 V AY
BA E 25 26 25 V BA
BB V E 25 25 25 V BB
BC V 25 25 25 36 V BC
BD E 32 31 25 37 25 BD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_32_100715

Figure 3-32: FLVD1924 Package—XCKU115 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


235
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVF1924 (XCKU085)
X-Ref Target - Figure 3-33

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

VC 71

VC 72

VC 52
A G 3 3 2 24 24 23 24 24 23 18 G A

V
C

C
O

O
VC 73

V C 52
3
B 3 3 1 5 2 22 20 20 23 23 22 22 18 B

C
3

O
232 232

V C 73

VC 53
2
C 2 2 1 5 4 4 22 21 19 21 20 17 S 16 15 C

C
2

O
232 232

VC 71

V C 72

V C 52
1
D 1 1 6 6 S 21 19 21 20 19 17 16 15 D

C
1

O
232 232

V C 70

VC 72

VC 52
0
E 0 0 S 10 10 7 17 17 15 S 19 14 14 13 E

C
0

O
232 232

VC 73

VC 53
3
F 3 3 S 8 11 7 9 18 18 15 S 11 11 13 6 6 F

C
3

O
231 231

VC 71

VC 53

VC 52
2
G 2 2 23 8 12 11 9 16 14 14 S 10 12 12 4 5 G

C
2

O
231 231

VC 71

VC 72

VC 52
1
H 1 1 24 24 21 21 23 12 13 13 16 13 13 10 8 9 4 5 3 H

C
1

O
231 231

V C 70

V C 73

V C 53
0
J 0 0 22 22 19 19 14 14 15 12 12 11 8 9 7 2 3 J

C
0

O
231 231

V C 73

VC 53

VC 52
K 3 3 20 20 17 17 16 18 18 15 10 11 S 21 19 S 7 2 3 3 K

C
O

O
230 132

VC 71

V C 72

V C 51
3 3
L 16 13 15 15 16 17 17 8 8 10 9 21 19 24 17 15 1 1 L

C
3 3

O
230 132

V C 70

VC 72

V C 51
1
M 2 2 16 S 13 18 S 24 19 5 7 7 9 23 22 24 17 15 18 2 2 M

C
1

O
230 232 132

VC 70

VC 73

VC 53
2 0 2
N S 14 14 18 24 19 23 5 3 6 23 22 20 20 16 18 N

C
2 0 2

O
230 232 132

VC 71

V C 53

V C 51
1
P 1 1 10 12 9 9 20 22 23 1 3 6 4 10 11 13 14 14 16 1 1 P

C
1

O
230 231 132

VC 70

VC 72

VC 51
1 0 1
R 10 12 11 11 20 22 21 21 1 2 4 10 11 12 13 S R

C
1 0 1

O
230 231 132

VC 70

VC 73

VC 5 1
1 1
T 0 0 6 8 8 7 7 S 2 9 7 12 6 6 4 0 0 T

C
1 1

O
230 230 132 132
0 0
U 0
230
3
229
3 6 4 3 5 5 9 7 8 8 2 4 3
131
3
132
0 U

VC 51
3 0 0 3
V 4 3 1 1 S 5 5 2 V

C
3 0 0 3

O
229 230 132 131
V C 70

VC 51
2 2
W 2 2 2 2 C
S 3 3 1 2 2 W

C
2 2
O

O
229 229 131 131
1 1
Y 1
229
1 1
229
1 131
1 1
131
1 Y
1 1
AA 1
229
0
229
0 0
131
0
131
1 AA
0 0 0 0
AB 0
229
0
229 131
0
131
0 AB
3 3
AC 3
228
3
228
3 24 3
128
3
128
3 AC
1 1
AD 2
228
2
1
228
S 24 128
1
2
128
2 AD

VC 4 6
2 2
AE 1 1 23 23 21 22 1 1 AE

C
2 2

O
228 228 128 128

VC 46
1 0 0 1
AF S 19 21 20 22 AF

C
1 0 0 1

O
228 228 128 128
0 0
AG 0
228
0
228
0 S 18 17 17 19 20 S 0
128
0
128
0 AG

VC 46
3 1 1 3
AH 24 24 17 18 18 14 11 9 9 AH

C
3 1 1 3

O
227 227 127 127
VC 68

VC 66

VC 46
2 2
AJ 3 3 22 22 17 18 4 2 5 23 15 16 16 14 11 7 7 3 3 AJ
C

C
2 2
O

O
227 227 127 127
VC 67

VC 46
0 0
AK 2 2 23 20 20 15 16 4 2 1 2 6 6 5 23 24 24 15 13 13 12 12 10 2 2 AK
C

C
0 0
O

O
227 227 127 127
VC 67

VC 65
1 1 1 1
AL 23 21 15 13 16 2 1 5 3 3 21 19 22 24 24 5 8 8 10 AL
C

C
1 1 1 1
O

O
227 226 126 127
VC 6 8

VC 66

VC 46
0
AM 1 1 19 19 21 13 S 6 6 5 4 4 1 21 19 20 22 23 22 22 5 3 1 1 4 1 1 AM
C

C
0
O

O
227 226 127
V C 68

VC 66

V C 44
0 1 0 0
AN 10 S 14 14 7 7 3 3 1 8 7 17 20 S S 23 19 20 3 6 4 AN
C

C
0 1 0 0
O

O
227 225 126 127
VC 67

VC 65

V C 46
0
AP 0 0 10 8 12 12 5 9 10 10 10 8 7 17 15 18 21 21 17 19 20 2 2 6 0 0 AP
C

C
0
O

O
227 225 127
VC 68

VC 65

VC 45
3 1 3
AR 9 8 11 11 5 9 8 8 10 12 11 9 15 18 16 16 18 17 15 15 S 23 23 21 AR
C

C
3 1 3
O

O
226 224 126
VC 68

VC 6 6

V C 44
0
AT 3 3 9 4 6 6 1 12 12 S 12 11 9 S 13 16 16 14 18 13 S 19 19 24 24 21 3 3 AT
C

C
0
O

O
226 224 126
VC 67

V C 44

VC 45
2 2
AU 2 2 7 7 4 3 1 11 11 15 S 14 13 15 13 14 14 14 11 11 13 20 20 22 22 17 AU
C

C
2 2
O

O
226 226 126
V C 68

VC 65

V C 45
1
AV 1 1 2 2 3 14 14 13 15 14 13 15 S 11 11 S S 12 12 10 S 13 18 18 17 2 2 AV
C

C
1
O

O
226 226 126
VC 66

VC 44
0 1
AW 0 0 3 3 S 16 13 17 18 18 17 17 12 12 9 9 9 8 10 16 16 13 15 15 AW
C

C
0 1
O

226 226 224 O 126


VC 6 7

VC 44

VC 45
3
AY 3 3 2 2 16 18 17 19 19 16 16 8 10 7 9 7 7 8 14 14 11 11 1 1 AY
C

C
3
O

O
225 224 224 126
VC 67

VC 65

VC 45
3 2 0
BA 2 2 1 1 18 20 20 S 20 20 S 8 10 7 6 5 1 3 3 12 9 S BA
C

C
3 2 0
O

O
225 225 224 224 126
VC 66

VC 45

2 1
BB 1 1 S 21 22 21 21 24 4 4 5 5 2 6 3 5 1 5 8 12 9 0 0 BB
C

2 1
O

225 225 224 126


VC 66

V C 44

1 0
BC 0 0 23 21 19 22 23 24 22 2 1 1 3 2 1 3 2 4 5 8 10 7 BC
C

1 0
O

225 224 224


VC 67

VC 65

V C 45
0
BD G 23 19 24 24 23 22 2 6 6 3 4 4 1 2 4 6 6 10 7 G BD
V

V
0 0
C

C
0
O

225 225 O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Bank 44 Bank 68 Quad 132 Quad 231 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 70 Quad 224 Quad 232
Bank 46 Bank 71 Quad 225 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 51 Bank 72 Quad 226 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 52 Quad 126 Quad 227 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 65 Quad 127 Quad 228 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 66 Quad 128 Quad 229 # IO_L#N_GC #


MGTREFCLK#P

Bank 67 Quad 131 Quad 230 VRP # MGTREFCLK#N

ug575_c3_33_100715

Figure 3-33: FLVF1924 Package—XCKU085 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


236
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-34

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A n n V n n E n n n n n n n A
B V E n n E n n n n n n n n n B
C V E n n E n n n n n n n n n V n n C
D V V E n n n n n n n n n n n V D
E V E n n E n n n n n n n n E n n E
F V E E n n n n n n n n n n n V F
G V E n n n n n n n V n n G
H V E n n n n n n n n n n V H
J V E n n n n n n n n E n n J
K V E n n n n n n n n n V K
L V n n E n n n n n n V L
M V E n n n n n n V M
N V E n n n n n n n n E N
P V E 12 n n n n n E V P
R V n n n n n n n V R
T V E 11 n n n n n E V T
V
U V 10 E E U
V V E 1 E V V
V V
W V 9 V W
Y V E 15 E V Y
V
AA V E E AA
AB V E 6 19 18 E V AB
AC V E 13 17 24 21 E E AC
AD V E 14 0 20 22 23 E V AD
V V
AE V 8 7 V AE
AF V E 16 E V AF
V V
AG V 5 4 E AG
AH V E 3 E V AH
AJ V E 2 33 E V AJ
AK V E 34 30 28 E V AK
AL V E 29 29 29 E AL
AM V E 29 29 29 29 E V AM
AN V E 29 29 35 V AN
AP V E 29 26 29 V AP
AR V E 26 29 26 E AR
AT V E 27 26 26 V AT
AU V E 26 26 26 V AU
AV V E 26 26 35 V AV
AW V E 26 26 26 E AW
AY V E E 25 26 25 26 V AY
BA V E E 25 25 26 25 V BA
BB V V E E 25 25 25 25 V BB
BC V V E 31 36 37 25 V BC
BD V E E 32 25 25 25 BD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_34_100715

Figure 3-34: FLVF1924 Package—XCKU085 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


237
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVF1924 (XCKU115) and RLF1924 (XQKU115)


X-Ref Target - Figure 3-35

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

VC 71

VC 72

VC 52
3
A G 3 3 2 2 2 24 24 23 S 22 22 21 24 24 23 18 G A

V
3 3

C
3

O
233 233

VC 73

VC 52
3 2
B 3 3 1 5 2 1 1 4 22 20 20 23 23 20 20 21 23 22 22 18 3 3 B

C
3 2

O
232 232 233 133

VC 73

VC 53
2 1 3
C 2 2 2 2 1 5 4 4 5 4 6 22 21 19 24 23 19 19 21 20 17 S 16 15 C

C
2 1 3

O
232 232 233 233 133

VC 71

VC 72

V C 52
1
D 1 1 1 1 6 6 3 5 6 S 21 19 24 S 16 17 21 20 19 17 16 15 2 2 D

C
1

O
232 232 233 133

VC 70

VC 72

VC 52
0 0 2
E 0 0 S 10 10 7 3 10 10 9 17 17 15 18 16 17 15 S 19 14 14 13 E

C
0 0 2

O
232 232 233 133

V C 73

VC 53
3
F 3 3 0 0 S 8 11 7 9 8 7 9 18 18 15 18 14 13 15 S 11 11 13 6 6 1 1 F

C
3

O
231 231 233 133

VC 71

VC 53

V C 52
2 1
G 2 2 23 8 12 11 9 8 12 7 16 14 14 S 14 13 12 10 10 12 12 4 5 G

C
2 1

O
231 231 133

VC 71

VC 72

VC 52
1
H 1 1 24 24 21 21 23 12 13 13 S 12 11 11 16 13 13 11 11 12 10 10 8 9 4 5 3 0 0 H

C
1

O
231 231 133

V C 70

VC 73

V C 53
0 0
J 0 0 22 22 19 19 14 14 15 S 14 14 15 12 12 11 9 9 7 8 8 9 7 2 3 J

C
0 0

O
231 231 133

VC 73

VC 53

VC 52
1
K 3 3 20 20 17 17 16 18 18 15 16 13 13 15 10 11 S S 7 8 21 19 S 7 2 3 3 K

C
1

O
230 233 132

VC 71

VC 7 2

VC 51
3 0 3
L 16 13 15 15 16 17 17 18 16 17 8 8 10 9 6 6 2 21 19 24 17 15 1 1 L

C
3 0 3

O
230 233 132

VC 70

VC 72

VC 51
1
M 2 2 16 S 13 18 S 24 19 20 18 21 17 5 7 7 9 4 2 23 22 24 17 15 18 2 2 M

C
1

O
230 232 132

VC 70

VC 73

VC 53
2 0 1 2
N S 14 14 18 24 19 23 20 21 S 5 3 6 5 5 4 23 22 20 20 16 18 N

C
2 0 1 2

O
230 232 133 132

VC 71

VC 53

V C 51
1
P 1 1 10 12 9 9 20 22 23 22 22 23 1 3 6 4 3 3 10 11 13 14 14 16 1 1 P

C
1

O
230 231 132

VC 7 0

VC 72

VC 51
1 0 0 1
R 10 12 11 11 20 22 21 21 24 24 23 1 2 4 1 1 10 11 12 13 S R

C
1 0 0 1

O
230 231 133 132

VC 70

VC 73

VC 51
1 1
T 0 0 6 8 8 7 7 S 19 19 2 9 7 12 6 6 4 0 0 T

C
1 1

O
230 230 132 132
0 0
U 0
230
3
229
3 6 4 3 5 5 9 7 8 8 2 4 3
131
3
132
0 U

VC 51
3 0 0 3
V 4 3 1 1 S 5 5 2 V

C
3 0 0 3

O
229 230 132 131

VC 70

VC 51
2 2
W 2 2 2 2 C
S 3 3 1 2 2 W

C
2 2
O

O
229 229 131 131
1 1
Y 1
229
1 1
229
1 131
1 1
131
1 Y
1 1
AA 1
229
0
229
0 0
131
0
131
1 AA
0 0 0 0
AB 0
229
0
229 131
0
131
0 AB
3 3
AC 3
228
3
228
3 24 3
128
3
128
3 AC
1 1
AD 2
228
2
1
228
S 24 128
1
2
128
2 AD

VC 46
2 2
AE 1 1 23 23 21 22 1 1 AE

C
2 2

O
228 228 128 128

VC 46
1 0 0 1
AF S 19 21 20 22 AF

C
1 0 0 1

O
228 228 128 128
0 0
AG 0
228
0
228
0 S 18 17 17 19 20 S 0
128
0
128
0 AG

VC 46
3 1 1 3
AH 24 24 17 18 18 14 11 9 9 AH

C
3 1 1 3

O
227 227 127 127
VC 68

VC 6 6

VC 4 6
2 2
AJ 3 3 22 22 17 18 4 2 5 23 15 16 16 14 11 7 7 3 3 AJ
C

C
2 2
O

O
227 227 127 127
V C 67

VC 46
0 0
AK 2 2 23 20 20 15 16 4 2 1 2 6 6 5 23 24 24 15 13 13 12 12 10 2 2 AK
C

C
0 0
O

O
227 227 127 127
VC 67

VC 65
1 1 1 1
AL 23 21 15 13 16 2 1 5 3 3 21 19 22 24 24 5 8 8 10 AL
C

C
1 1 1 1
O

O
227 226 126 127
V C 68

VC 66

VC 46
0
AM 1 1 19 19 21 13 S 6 6 5 4 4 1 21 19 20 22 23 22 22 5 3 1 1 4 1 1 AM
C

C
0
O

O
227 226 127
VC 68

V C 66

V C 44
0 1 0 0
AN 10 S 14 14 7 7 3 3 1 8 7 17 20 S S 23 19 20 3 6 4 AN
C

C
0 1 0 0
O

O
227 225 126 127
V C 67

V C 65

V C 46
0
AP 0 0 10 8 12 12 5 9 10 10 10 8 7 17 15 18 21 21 17 19 20 2 2 6 0 0 AP
C

C
0
O

O
227 225 127
VC 68

VC 65

VC 45
3 1 3
AR 9 8 11 11 5 9 8 8 10 12 11 9 15 18 16 16 18 17 15 15 S 23 23 21 AR
C

C
3 1 3
O

O
226 224 126
VC 68

V C 66

VC 44
0
AT 3 3 9 4 6 6 1 12 12 S 12 11 9 S 13 16 16 14 18 13 S 19 19 24 24 21 3 3 AT
C

C
0
O

O
226 224 126
VC 67

VC 44

VC 45
2 2
AU 2 2 7 7 4 3 1 11 11 15 S 14 13 15 13 14 14 14 11 11 13 20 20 22 22 17 AU
C

C
2 2
O

O
226 226 126
V C 68

VC 6 5

VC 45
1
AV 1 1 2 2 3 14 14 13 15 14 13 15 S 11 11 S S 12 12 10 S 13 18 18 17 2 2 AV
C

C
1
O

O
226 226 126
VC 66

VC 44
0 1
AW 0 0 3 3 S 16 13 17 18 18 17 17 12 12 9 9 9 8 10 16 16 13 15 15 AW
C

C
0 1
O

226 226 224 O 126


VC 67

VC 44

VC 45
3
AY 3 3 2 2 16 18 17 19 19 16 16 8 10 7 9 7 7 8 14 14 11 11 1 1 AY
C

C
3
O

O
225 224 224 126
V C 67

VC 65

VC 45
3 2 0
BA 2 2 1 1 18 20 20 S 20 20 S 8 10 7 6 5 1 3 3 12 9 S BA
C

C
3 2 0
O

O
225 225 224 224 126
VC 66

VC 45

2 1
BB 1 1 S 21 22 21 21 24 4 4 5 5 2 6 3 5 1 5 8 12 9 0 0 BB
C

2 1
O

225 225 224 126


V C 66

V C 44

1 0
BC 0 0 23 21 19 22 23 24 22 2 1 1 3 2 1 3 2 4 5 8 10 7 BC
C

1 0
O

225 224 224


V C 67

V C 65

VC 45
0
BD G 23 19 24 24 23 22 2 6 6 3 4 4 1 2 4 6 6 10 7 G BD
V

V
0 0
C

C
0
O

225 225 O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Bank 44 Bank 67 Quad 128 Quad 228 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 68 Quad 131 Quad 229
Bank 46 Bank 70 Quad 132 Quad 230 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 51 Bank 71 Quad 133 Quad 231 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#
V

Bank 52 Bank 72 Quad 224 Quad 232 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 53 Bank 73 Quad 225 Quad 233 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 65 Quad 126 Quad 226 # IO_L#N_GC #


MGTREFCLK#P

Bank 66 Quad 127 Quad 227 VRP # MGTREFCLK#N

ug575_c3_35_100715

Figure 3-35: FLVF1924 Package—XCKU115 and RLF1924 Package—XQKU115 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


238
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-36

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A V E A
B V E E B
C V E E V C
D V V E V D
E V E E E E
F V E E V F
G V E V G
H V E V H
J V E E J
K V E V K
L V E V L
M V E V M
N V E E N
P V E 12 E V P
R V V R
T V E 11 E V T
V
U V 10 E E U
V V E 1 E V V
V V
W V 9 V W
Y V E 15 E V Y
V
AA V E E AA
AB V E 6 19 18 E V AB
AC V E 13 17 24 21 E E AC
AD V E 14 0 20 22 23 E V AD
V V
AE V 8 7 V AE
AF V E 16 E V AF
V V
AG V 5 4 E AG
AH V E 3 E V AH
AJ V E 2 33 E V AJ
AK V E 34 30 28 E V AK
AL V E 29 29 29 E AL
AM V E 29 29 29 29 E V AM
AN V E 29 29 35 V AN
AP V E 29 26 29 V AP
AR V E 26 29 26 E AR
AT V E 27 26 26 V AT
AU V E 26 26 26 V AU
AV V E 26 26 35 V AV
AW V E 26 26 26 E AW
AY V E E 25 26 25 26 V AY
BA V E E 25 25 26 25 V BA
BB V V E E 25 25 25 25 V BB
BC V V E 31 36 37 25 V BC
BD V E E 32 25 25 25 BD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_36_100715

Figure 3-36: FLVF1924 Package—XCKU115 and RLF1924 Package—XQKU115


Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


239
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVA2104 (XCKU115)
X-Ref Target - Figure 3-37

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

VC 7 1

VC 73

V C 53

VC 51
A G 10 10 S 12 22 22 21 21 22 22 S 24 20 20 S 22 20 S 22 22 21 24 24 23 18 16 16 A

C
O

O
V C 71

VC 72

V C 51
B 9 9 11 12 20 19 24 24 19 19 24 24 23 23 24 22 21 20 23 20 20 21 23 22 22 18 15 3 3 B

C
O

O
133

VC 71

VC 72

VC 52
C 3 3 8 7 7 11 20 19 23 23 20 21 21 24 22 21 21 24 21 19 24 23 19 19 21 20 19 S 15 17 C

C
O

O
233

VC 73

VC 53

VC 51
3
D 8 6 4 4 13 S S 18 20 23 23 S 22 19 23 23 19 24 S 16 17 21 20 S 19 13 17 2 2 D

C
3

O
233 133

VC 71

VC 53

V C 51
3
E 2 2 6 2 13 14 16 16 18 15 15 17 15 15 19 17 17 15 18 16 17 15 7 S 14 14 13 E

C
3

O
233 133

V C 71

VC 72

V C 52
2
F 1 1 3 3 2 14 16 17 16 14 14 17 17 18 18 18 13 15 18 14 13 15 7 11 11 6 6 3 1 1 F

C
2

O
233 233 133

VC 71

VC 73

V C 52

V C 51
2
G 0 0 1 1 5 15 17 S 13 13 17 13 13 16 18 13 14 16 14 13 12 10 10 12 12 4 3 G

C
2

O
233 133

V C 73

V C 53

VC 51
1
H 3 3 5 15 18 18 11 12 12 S 14 14 16 S 14 16 11 11 12 10 10 8 9 4 2 2 0 0 H

C
1

O
233 232 133

VC 70

VC 72

VC 52
1 1
J 2 2 21 24 S 7 11 10 S 11 12 8 S 11 12 9 9 7 8 8 9 5 1 1 J

C
1 1

O
232 233 133

VC 72

VC 52
0
K 1 1 21 24 23 23 8 7 9 10 11 12 7 8 11 12 9 S 7 8 21 19 S 5 3 3 K

C
0

O
233 232 132

VC 73

V C 53

VC 5 0
0 0
L 22 20 20 17 8 9 S 10 9 7 10 10 8 9 6 6 2 21 19 24 17 15 G L

V
0 0

C
0 0

O
232 233 133

VC 70

VC 53

VC 50
3
M 3 3 22 19 19 17 6 3 3 10 9 4 2 8 7 7 4 2 23 22 24 17 15 18 2 2 M

C
3

O
232 231 132

VC 70

VC 72

V C 52
1 1 3
N S 13 13 15 6 5 5 1 4 2 6 4 5 5 5 4 23 22 20 20 16 18 N

C
1 1 3

O
232 133 132

VC 73

VC 52

VC 50
2
P 2 2 16 18 14 15 4 4 2 1 3 5 6 4 5 3 3 3 10 11 13 14 14 16 1 1 P

C
2

O
232 231 132

VC 70

VC 53

V C 50
1 0 0 2
R 16 18 11 14 S 1 1 2 3 5 6 2 1 3 1 1 10 11 12 13 S R

C
1 0 0 2

O
232 232 VC 70 133 132

V C 72

VC 50
0 1
T 1 1 10 12 11 9 9 6 2 1 7 7 12 6 6 4 0 0 T
C

C
0 1
O

O
232 231 132 132
3 1 1
U 3
231
1
231
10 4 12 7 8 8 8 2 4 3
131
3
132
1 U
2 0
V 2
231
0
231
0 3 4 6 7 8 S 2 5 5 132
0 V
V C 70

VC 50
1 0 0
W 3 6 S 9 1 3 2 2 W
C

C
1 0 0
O

O
231 231 131 132
0 1 3
Y 0
231
3
227
3 5 1 2 9 1 3 131
1
131
3 Y
3 1 2
AA 3
227
1
227
5 1 2 1
131
1
131
2 AA
2 0 1
AB 2
227
2
227
2
131
0
131
1 AB
1 0 0
AC 1
227
0
227
0
131
0
131
0 AC
0 1 3
AD 0
227
1
227
1
128
1
128
3 AD
3 1 2
AE 3
226
1
226
3
128
3
128
2 AE
2 0 1
AF 2
226
0
227
0
128
0
128
1 AF
1 0 0
AG 1
226
0
226
23 24 24 22 2
128
2
128
0 AG

VC 47
0 1
AH 3 3 S 23 21 21 22 AH

C
0 1

O
226 226 127
3 1 3
AJ 3
225
1
225
22 22 17 17 14 19 20 20 1
128
1
127
3 AJ

VC 47
2 0
AK 2 2 21 24 24 20 18 18 14 19 11 S 0 0 AK

C
2 0

O
225 226 127 128
V C 67

V C 84

V C 47
0 2
AL 21 19 20 24 24 23 24 S 24 15 16 16 13 11 7 7 3 3 AL
C

C
0 2
O

O
225 127 127
VC 65

VC 47
1 1
AM 1 1 23 23 19 S S 22 22 23 22 22 24 20 24 22 15 S 13 12 12 9 2 2 AM
C

C
1 1
O

O
225 226 126 127
V C 65

VC 45

1 0 1
AN 0 0 15 15 18 17 20 20 21 21 20 20 S 20 22 24 24 10 8 8 9 AN
C

1 0 1
O

226 224 126 127


VC 67

V C 84

VC 47
0
AP 3 3 16 14 18 17 23 23 21 21 19 19 23 23 21 21 23 22 22 10 3 5 5 1 1 1 AP
C

C
0
O

O
225 225 127
VC 84

VC 44
0 0
AR 2 2 16 14 13 S 19 19 16 16 17 17 18 18 19 19 S 23 19 20 3 6 1 AR
C

C
0 0
O

225 224 127


VC 6 5

VC 45

VC 47
3
AT 1 1 1 13 7 7 17 18 18 S 13 18 18 16 16 21 21 17 19 20 2 2 6 4 4 0 0 AT
C

C
3
O

O
224 225 127
VC 67

V C 45

VC 46
3
AU 0 0 6 1 11 11 8 17 14 14 15 13 14 16 14 17 17 16 18 17 15 15 S 23 23 21 AU
C

C
3
O

O
225 126
V C 67

V C 84

VC 44

2
AV 16 16 4 6 12 12 9 8 13 13 15 15 14 16 S 14 15 16 14 18 13 S 19 19 24 24 21 3 3 AV
C

2
O

224 126
VC 66

V C 65

VC 44

VC 46
2
AW 3 3 18 18 4 3 2 5 9 S S 12 15 12 12 9 13 13 15 14 11 11 13 20 20 22 22 17 AW
C

C
2
O

O
224 126
V C 67

VC 45

VC 46
1
AY 17 17 13 3 2 5 10 10 S 12 11 7 10 11 11 9 11 11 S S 12 12 10 S 13 18 18 17 2 2 AY
C

C
1
O

224 126
VC 67

V C 94

V C 44

1
BA 2 2 15 13 S 23 22 22 10 11 7 S 10 7 7 10 12 7 9 9 8 10 16 16 13 15 15 BA
C

1
O

224 126
V C 66

VC 94

VC 44

VC 46
0
BB 15 14 14 S 24 24 23 20 10 8 9 8 8 5 5 10 12 9 7 7 7 8 14 14 11 11 1 1 BB
C

C
0
O

O
224 126
VC 66

VC 65

VC 4 5

V C 46

0
BC 1 1 12 12 11 3 19 19 21 20 8 9 5 6 2 S 8 8 9 6 5 1 3 3 12 9 S BC
C

0
O

224 126
VC 66

VC 94

VC 46

BD G 7 7 11 3 1 4 21 6 6 5 6 2 3 6 6 5 3 2 6 3 5 1 5 8 12 9 BD
V

0 0
C

C
O

126
VC 66

VC 94

VC 44

BE 0 0 8 8 9 9 1 4 5 6 4 4 3 1 4 3 1 4 5 3 1 2 1 3 2 4 5 8 10 7 BE
C

C
O

224
VC 66

VC 65

V C 45

VC 46

BF S 10 10 2 2 5 6 2 2 3 1 S 4 1 4 2 2 1 4 4 1 2 4 6 6 10 7 G BF
V
C

C
O

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Bank 44 Bank 65 Bank 94 Quad 225 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 66 Quad 126 Quad 226
Bank 46 Bank 67 Quad 127 Quad 227 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Bank 70 Quad 128 Quad 231 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#
V

Bank 50 Bank 71 Quad 131 Quad 232 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 51 Bank 72 Quad 132 Quad 233 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 52 Bank 73 Quad 133 # IO_L#N_GC #


MGTREFCLK#P

Bank 53 Bank 84 Quad 224 VRP # MGTREFCLK#N

ug575_c3_37_100715

Figure 3-37: FLVA2104 Package—XCKU115 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


240
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-38

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
A V A
B V V V B
C V V C
D V D
E V E
F V F
G V V G
H V H
J V V J
K V E K
L V V L
M V E M
N V V V N
P E E P
R V V R
V
T V T
U V 10 E V U
V
V E V V V
V
W V E 12 E W
Y E 11 E V Y
V
AA V E E AA
AB E 1 E V AB
AC V E 9 24 21 E E AC
V
AD E 15 19 18 22 23 E V AD
V
AE V E 6 17 8 7 E AE
V
AF E 0 20 E V AF
V
AG V E 13 E AG
AH E 14 V V AH
AJ V E 16 E V AJ
AK E V AK
AL V V E 5 28 30 E V AL
AM V E 4 35 29 29 V AM
AN V E 3 29 29 29 V AN
AP V E 2 34 33 29 E AP
AR V E 29 29 26 26 V AR
AT V E 29 29 29 AT
AU V 29 26 26 V AU
AV V 26 26 26 AV
AW 27 26 26 V AW
AY V 35 26 26 25 AY
BA 26 26 25 V BA
BB V 26 25 26 BB
BC 25 26 25 V BC
BD V 25 25 25 BD
BE V 25 25 25 36 V V BE
BF V 32 31 25 37 25 BF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_38_100715

Figure 3-38: FLVA2104 Package—XCKU115 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


241
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVB2104 (XCKU095)
X-Ref Target - Figure 3-39

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

VC 6 9

VC 71

V C 50
A 21 21 22 24 S 23 24 22 22 23 24 22 22 23 24 22 22 19 17 15 15 10 9 A

C
O

O
VC 69

VC 71

V C 50
B 20 22 23 24 23 24 21 19 23 24 21 19 23 24 S 23 19 17 16 16 10 9 G B

V
C

C
O

O
VC 70

VC 51

VC 50
C 19 20 23 S 22 19 21 19 20 20 21 19 S 20 24 23 21 20 13 13 12 12 C

C
O

O
V C 70

V C 51

VC 50
D 19 S 17 18 22 19 20 20 17 17 18 S 18 20 21 24 21 20 18 14 11 8 7 D

C
O

O
V C 69

V C 71

VC 50
E 15 17 18 16 16 17 17 16 16 18 S 17 18 21 S 23 24 18 14 S 11 8 7 E

C
O

O
VC 7 0

VC 49
F 15 13 14 18 18 15 15 15 14 14 S 17 16 16 19 23 24 6 6 2 S F

C
O

O
VC 70

VC 51

VC 50
G 13 14 16 16 14 14 S 15 13 13 14 14 15 19 20 21 5 4 2 G

C
O

O
VC 69

VC 71

VC 50
H 9 11 10 10 13 13 10 S 11 12 13 11 11 15 20 21 22 5 4 1 1 H

C
O

O
VC 71

V C 49
J 9 11 12 12 11 12 12 10 11 12 10 13 12 12 16 17 22 3 3 3 3 J

C
O

O
131

VC 70

V C 51
3 1 3
K 3 3 7 8 8 7 11 9 S 8 9 10 10 10 8 16 17 14 18 S K

C
3 1 3

O
231 231 231 131

VC 69

VC 51
2 2
L 2 2 7 5 S 7 8 8 9 8 9 7 7 9 8 7 15 14 18 10 2 2 L

C
2 2

O
231 231 131 131

V C 69

VC 71

VC 4 9
1 0 1
M 1 1 5 6 1 3 3 6 2 5 5 S 9 7 15 13 13 10 1 1 M

C
1 0 1

O
231 231 231 131 131

VC 70

V C 49
0 1 0
N 0 0 1 2 6 1 2 4 6 2 3 4 6 5 4 11 12 12 9 0 0 N

C
0 1 0

O
231 231 131 131 131

V C 70

VC 51
3 1 3
P 3 3 1 2 3 4 2 4 5 1 3 4 6 6 5 4 7 11 S 9 3 3 P

C
3 1 3

O
230 230 230 130 130

VC 69

VC 71

V C 49
2 0 2
R 2 2 3 4 5 1 6 3 2 1 7 8 8 2 2 2 R

C
2 0 2

O
230 230 131 130 130

VC 49
1 0 1
T 1 1 3 2 1 6 3 2 1 1 1 T

C
1 0 1

O
230 230 230 130 130
0 1 0
U 0
230
0
230
0 6 5 3 1 130
1 0
130
0
130
0 U
3 1 3
V 3
229
3
229
3
1
229
5 4 4 3
129
3
129
3 V

V C 46
2 0 2
W 2 2 21 22 24 24 2 2 W

C
2 0 2

O
229 229 130 129 129
1 0 1
Y 1
229
1
229
1 0
229
21 22 23 23 1
129
1
129
1 Y
0 1 0
AA 0
229
0
229
0 19 19 20 129
1 0
129
0
129
0 AA

VC 46
3 1 3
AB 3 3 S 20 3 3 AB

C
3 1 3

O
228 228 228 128 128
2 0 2
AC 2
228
2
228
2 16 17 17 18 129
0 2
128
2
128
2 AC
1 0 1
AD 1
228
1
228
1
0
228
S 16 14 18 1
128
1
128
1 AD

VC 46
0 1 0
AE 0 0 15 13 13 14 0 0 AE

C
0 1 0

O
228 228 128 128 128

VC 4 6
3 1 3
AF 3 3 15 12 12 9 3 3 AF

C
3 1 3

O
227 227 227 127 127
2 0 2
AG 2
227
2
227
2 5 5 11 11 9 128
0 2
127
2
127
2 AG
1 0 1
AH 1
227
1
227
1
0
227
4 4 10 10 8 7 1
127
1
127
1 AH

VC 4 6
0 1 0
AJ 0 0 1 2 3 3 6 8 7 0 0 AJ

C
0 1 0

O
227 227 127 127 127

VC 46
3 1 3
AK 3 3 1 2 6 S 3 3 AK

C
3 1 3

O
226 226 226 126 126
VC 66

V C 65

2 0 2
AL 2 2 24 23 22 23 24 24 23 22 21 24 24 24 24 23 S 24 2 2 AL
C

2 0 2
O

226 226 127 126 126


VC 67

VC 84

VC 45
1 0 1
AM 1 1 24 23 21 22 23 24 24 23 22 21 22 23 22 22 23 23 24 1 1 AM
C

C
1 0 1
O

O
226 226 226 126 126
VC 66

VC 44
0 1 0
AN 0 0 21 21 21 19 19 20 19 19 20 21 22 23 20 21 23 22 22 21 0 0 AN
C

C
0 1 0
O

O
226 226 126 126 126
VC 66

VC 65

3 1 3
AP 3 3 22 20 20 S 17 20 18 S 20 21 19 19 20 21 20 19 20 21 3 3 AP
C

3 1 3
O

225 225 225 125 125


V C 67

V C 84

VC 45
2 0 2
AR 2 2 22 19 19 16 17 18 S 16 17 16 S 17 18 20 19 S 20 2 2 AR
C

C
2 0 2
O

O
225 225 126 125 125
VC 84

VC 44

1 0 1
AT 1 1 S S 17 16 15 13 14 16 17 18 16 17 18 18 18 S 19 19 1 1 AT
C

1 0 1
O

225 225 225 125 125


VC 66

V C 65

0 1 0
AU 0 0 15 16 17 18 15 13 14 S 15 18 S 15 15 16 17 17 15 S 0 0 AU
C

0 1 0
O

225 225 125 125 125


VC 67

VC 65

3 1 0 3
AV 3 3 15 16 18 S 11 12 10 15 13 14 13 14 14 16 14 15 18 17 AV
C

3 1 0 3
O

224 224 224 125 124


VC 84

V C 44

2 0 2
AW 13 13 14 14 11 12 9 10 13 14 10 13 12 13 13 14 18 17 16 16 3 3 AW
C

2 0 2
O

224 224 124 124


V C 66

VC 44

1
AY 8 8 12 9 9 7 8 9 11 12 10 11 11 12 11 12 12 15 14 14 AY
C

1
O

124
VC 67

VC 65

VC 45

1 0 1
BA G 10 12 12 7 12 11 11 7 8 7 11 12 10 7 9 9 9 11 10 15 13 12 BA
V

1 0 1
O

224 124 124


V C 67

VC 94

VC 45

BB 2 2 10 11 8 8 7 10 10 S 5 6 7 8 9 10 7 8 8 9 8 8 10 13 12 11 10 6 2 2 BB
C

C
O

224 124
VC 68

V C 94

VC 44

V C 45
0 0
BC 9 9 11 7 7 6 6 5 6 4 8 9 S 3 6 6 S 6 7 7 S 7 11 10 6 5 BC
C

C
0 0
O

O
224 124
VC 68

V C 66

VC 65

VC 45

BD 1 1 6 6 S 4 5 5 3 3 4 6 5 2 3 4 3 6 4 4 5 7 8 9 5 4 1 1 BD
C

C
O

224 124
VC 67

VC 94

VC 45

BE 1 2 4 4 5 4 2 3 1 3 6 5 4 2 5 4 2 3 3 2 2 5 8 9 3 2 4 BE
C

C
O

O
VC 68

VC 94

VC 44

BF 0 0 1 2 3 3 5 1 1 2 1 2 2 S 4 1 1 5 2 1 1 3 1 1 S 3 2 1 1 0 0 BF
C

C
O

224 124

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Bank 44 Bank 67 Quad 125 Quad 225 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 68 Quad 126 Quad 226
Bank 46 Bank 69 Quad 127 Quad 227 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 49 Bank 70 Quad 128 Quad 228 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#
V

Bank 50 Bank 71 Quad 129 Quad 229 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 51 Bank 84 Quad 130 Quad 230 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 65 Bank 94 Quad 131 Quad 231 # IO_L#N_GC #


MGTREFCLK#P

Bank 66 Quad 124 Quad 224 VRP # MGTREFCLK#N

ug575_c3_39_100715

Figure 3-39: FFVB2104 Package—XCKU095 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


242
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
A n n E n n E n n A
B V E n n B
C n n n n n n E n n V C
D n n n n V n n V n n D
E n n V n n E n n E
F n n n n V n n V V n n F
G n n V n n E n n G
H n n n n V n n V n n H
J n n V n n E n n J
K V n n V K
L V E n n E L
M V E V M
N V E E N
P V E V P
V
R V 12 E R
T V E V T
V
U V 11 E U
V V 10 E V V
W V E 1 V W
V
Y V 9 V Y
AA E 15 V AA
V
AB V V AB
V
AC V 6 19 V AC
AD V 13 E V AD
V
AE V 14 17 18 V AE
AF V E V AF
AG V E 16 0 20 24 21 E AG
V
AH V 5 22 23 V AH
AJ V E 3 8 7 V AJ
V
AK V 2 V AK
AL V E 4 29 30 28 E AL
AM V 29 29 33 E V AM
AN V E 29 34 29 V AN
AP E 29 29 29 E V AP
AR V E 26 35 29 29 E AR
AT V 26 29 29 E V AT
AU V E 27 26 26 V AU
AV E 26 26 26 V AV
AW E 26 26 26 E AW
AY 26 26 26 26 E AY
BA 25 26 26 V V BA
BB 25 25 25 BB
BC V 25 25 35 V BC
BD V 25 25 25 V BD
BE V 25 25 31 25 n n V BE
BF 25 32 36 37 BF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_40_100715
X-Ref Target - Figure 3-40

Figure 3-40: FFVB2104 Package—XCKU095 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


243
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVB2104 (XCKU115)
X-Ref Target - Figure 3-41

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

VC 71

VC 73

VC 5 2
3
A 3 3 21 21 22 24 S 23 24 22 22 23 24 22 22 23 24 22 22 19 17 15 15 10 9 A

C
3

O
233 233

VC 71

V C 73

VC 52
1
B 20 22 23 24 23 24 21 19 23 24 21 19 23 24 S 23 19 17 16 16 10 9 G B

V
C

C
1

O
233

V C 72

VC 53

V C 52
2
C G 19 20 23 S 22 19 21 19 20 20 21 19 S 20 24 23 21 20 13 13 12 12 C

V
2 2

C
2

O
233 233

VC 72

VC 53

V C 52
1 0
D 1 1 19 S 17 18 22 19 20 20 17 17 18 S 18 20 21 24 21 20 18 14 11 8 7 D

C
1 0

O
233 233 233

VC 71

V C 73

VC 52
0
E 0 0 15 17 18 16 16 17 17 16 16 18 S 17 18 21 S 23 24 18 14 S 11 8 7 E

C
0

O
233 233

VC 72

VC 51
3 1
F 3 3 15 13 14 18 18 15 15 15 14 14 S 17 16 16 19 23 24 6 6 2 S F

C
3 1

O
232 232 232

VC 72

VC 53

VC 52
2
G 2 2 13 14 16 16 14 14 S 15 13 13 14 14 15 19 20 21 5 4 2 G

C
2

O
232 232

VC 71

V C 73

VC 52
1 0
H 1 1 9 11 10 10 13 13 10 S 11 12 13 11 11 15 20 21 22 5 4 1 1 H

C
1 0

O
232 232 232

VC 73

V C 51
0
J 0 0 9 11 12 12 11 12 12 10 11 12 10 13 12 12 16 17 22 3 3 3 3 J

C
0

O
232 232 133

VC 72

V C 53
3 1 3
K 3 3 7 8 8 7 11 9 S 8 9 10 10 10 8 16 17 14 18 S K

C
3 1 3

O
231 231 231 133

VC 71

VC 5 3
2 2
L 2 2 7 5 S 7 8 8 9 8 9 7 7 9 8 7 15 14 18 10 2 2 L

C
2 2

O
231 231 133 133

VC 71

VC 73

VC 51
1 0 1
M 1 1 5 6 1 3 3 6 2 5 5 S 9 7 15 13 13 10 1 1 M

C
1 0 1

O
231 231 231 133 133

VC 72

VC 51
0 1 0
N 0 0 1 2 6 1 2 4 6 2 3 4 6 5 4 11 12 12 9 0 0 N

C
0 1 0

O
231 231 133 133 133

V C 72

VC 53
3 1 3
P 3 3 1 2 3 4 2 4 5 1 3 4 6 6 5 4 7 11 S 9 3 3 P

C
3 1 3

O
230 230 230 132 132

VC 71

VC 73

VC 5 1
2 0 2
R 2 2 3 4 5 1 6 3 2 1 7 8 8 2 2 2 R

C
2 0 2

O
230 230 133 132 132

VC 5 1
1 0 1
T 1 1 3 2 1 6 3 2 1 1 1 T

C
1 0 1

O
230 230 230 132 132
0 1 0
U 0
230
0
230
0 6 5 3 1 132
1 0
132
0
132
0 U
3 1 3
V 3
229
3
229
3
1
229
5 4 4 3
131
3
131
3 V

V C 46
2 0 2
W 2 2 21 22 24 24 2 2 W

C
2 0 2

O
229 229 132 131 131
1 0 1
Y 1
229
1
229
1 0
229
21 22 23 23 1
131
1
131
1 Y
0 1 0
AA 0
229
0
229
0 19 19 20 131
1 0
131
0
131
0 AA

VC 46
3 1
AB 3 3 S 20 AB

C
3 1

O
228 228 228
2 0
AC 2
228
2
228
2 16 17 17 18 131
0 AC
1 0
AD 1
228
1
228
1
0
228
S 16 14 18 AD

VC 46
0
AE 0 0 15 13 13 14 AE

C
0

O
228 228

V C 46
3 1
AF 3 3 15 12 12 9 AF

C
3 1

O
227 227 227
2
AG 2
227
2
227
2 5 5 11 11 9 AG
1 0
AH 1
227
1
227
1
0
227
4 4 10 10 8 7 AH

VC 46
0
AJ 0 0 1 2 3 3 6 8 7 AJ

C
0

O
227 227

VC 46
3 1 3
AK 3 3 1 2 6 S 3 3 AK

C
3 1 3

O
226 226 226 128 128
VC 66

VC 65

2 2
AL 2 2 24 23 22 23 24 24 23 22 21 24 24 24 24 23 S 24 2 2 AL
C

2 2
O

226 226 128 128


VC 67

VC 84

V C 45
1 0 1
AM 1 1 24 23 21 22 23 24 24 23 22 21 22 23 22 22 23 23 24 1 1 AM
C

C
1 0 1
O

O
226 226 226 128 128
VC 6 6

V C 44
0 1 0
AN 0 0 21 21 21 19 19 20 19 19 20 21 22 23 20 21 23 22 22 21 0 0 AN
C

C
0 1 0
O

O
226 226 128 128 128
VC 66

VC 65

3 1 3
AP 3 3 22 20 20 S 17 20 18 S 20 21 19 19 20 21 20 19 20 21 3 3 AP
C

3 1 3
O

225 225 225 127 127


VC 67

VC 84

VC 45
2 0 2
AR 2 2 22 19 19 16 17 18 S 16 17 16 S 17 18 20 19 S 20 2 2 AR
C

C
2 0 2
O

O
225 225 128 127 127
VC 84

VC 44

1 0 1
AT 1 1 S S 17 16 15 13 14 16 17 18 16 17 18 18 18 S 19 19 1 1 AT
C

1 0 1
O

225 225 225 127 127


VC 66

VC 65

0 1 0
AU 0 0 15 16 17 18 15 13 14 S 15 18 S 15 15 16 17 17 15 S 0 0 AU
C

0 1 0
O

225 225 127 127 127


VC 67

V C 65

3 1 0 3
AV 3 3 15 16 18 S 11 12 10 15 13 14 13 14 14 16 14 15 18 17 AV
C

3 1 0 3
O

224 224 224 127 126


VC 84

V C 44

2 0 2
AW 13 13 14 14 11 12 9 10 13 14 10 13 12 13 13 14 18 17 16 16 3 3 AW
C

2 0 2
O

224 224 126 126


VC 66

VC 44

1
AY 8 8 12 9 9 7 8 9 11 12 10 11 11 12 11 12 12 15 14 14 AY
C

1
O

126
VC 67

VC 65

VC 45

1 0 1
BA G 10 12 12 7 12 11 11 7 8 7 11 12 10 7 9 9 9 11 10 15 13 12 BA
V

1 0 1
O

224 126 126


V C 67

VC 94

VC 45

BB 2 2 10 11 8 8 7 10 10 S 5 6 7 8 9 10 7 8 8 9 8 8 10 13 12 11 10 6 2 2 BB
C

C
O

224 126
VC 68

V C 94

VC 44

V C 45
0 0
BC 9 9 11 7 7 6 6 5 6 4 8 9 S 3 6 6 S 6 7 7 S 7 11 10 6 5 BC
C

C
0 0
O

O
224 126
VC 68

V C 66

VC 65

VC 45

BD 1 1 6 6 S 4 5 5 3 3 4 6 5 2 3 S 4 3 6 4 4 5 7 8 9 5 4 1 1 BD
C

C
O

224 126
VC 6 7

VC 94

V C 45

BE 1 2 4 4 5 4 2 3 1 3 6 5 4 2 5 4 2 3 3 2 2 5 8 9 3 2 4 V G BE
C

C
O

O
VC 68

VC 94

VC 44

BF 0 0 1 2 3 3 5 1 1 2 1 2 2 S 4 1 1 5 2 1 1 3 1 1 S 3 2 1 1 0 0 BF
C

C
O

224 126

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Bank 44 Bank 67 Quad 127 Quad 227 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 68 Quad 128 Quad 228
Bank 46 Bank 71 Quad 131 Quad 229 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 51 Bank 72 Quad 132 Quad 230 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#
V

Bank 52 Bank 73 Quad 133 Quad 231 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 53 Bank 84 Quad 224 Quad 232 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 65 Bank 94 Quad 225 Quad 233 # IO_L#N_GC #


MGTREFCLK#P

Bank 66 Quad 126 Quad 226 VRP # MGTREFCLK#N

ug575_c3_41_100715

Figure 3-41: FLVB2104 Package—XCKU115 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


244
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-42

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
A E E n n A
B V E B
C E n n V C
D V V n n D
E V E n n E
F V V V n n F
G V E n n G
H V V n n H
J V E n n J
K V n n V K
L V E n n E L
M V E V M
N V E E N
P V E V P
V
R V 12 E R
T V E V T
V
U V 11 E U
V V 10 E V V
W V E 1 V W
V
Y V 9 V Y
AA E 15 V AA
V
AB V n n V n n AB
V
AC V 6 19 V n n n n AC
AD V 13 E n n V n n AD
V
AE V 14 17 18 n n V n n n n AE
AF V E n n V n n AF
AG V E 16 0 20 24 21 n n E n n n n AG
V
AH V 5 22 23 n n V n n AH
AJ V E 3 8 7 n n V n n n n AJ
V
AK V 2 V AK
AL V E 4 29 30 28 n n E AL
AM V 29 29 33 E V AM
AN V E 29 34 29 V AN
AP E 29 29 29 E V AP
AR V E 26 35 29 29 E AR
AT V 26 29 29 E V AT
AU V E 27 26 26 V AU
AV E 26 26 26 V AV
AW E 26 26 26 E AW
AY 26 26 26 26 E AY
BA 25 26 26 V V BA
BB 25 25 25 BB
BC V 25 25 35 V BC
BD V 25 25 25 V BD
BE V 25 25 31 25 V BE
BF 25 32 36 37 BF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_42_100715

Figure 3-42: FLVB2104 Package—XCKU115 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


245
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVC1517 (XCVU065)
X-Ref Target - Figure 3-43

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

V C 48

VC 45
A 3 3 20 22 24 24 23 22 24 3 3 1 2 1 1 4 23 23 19 3 3 A

C
O

O
228 128

VC 48

VC 45
3 3
B 20 22 21 23 23 22 21 24 6 1 4 2 3 4 2 2 22 19 24 B

C
3 3

O
228 128

VC 47

VC 46

V C 44
2 2
C 2 2 19 21 23 S 19 21 S 5 6 4 5 3 6 6 21 22 24 2 2 C

C
2 2

O
228 228 128 128

V C 48

VC 45
D 1 1 19 S 17 S 19 20 20 5 S 7 8 5 S 7 7 21 S 20 20 1 1 D

C
O

O
228 128

VC 48

VC 45
1 1
E 15 13 17 18 16 17 17 18 9 7 8 10 10 9 9 8 17 15 15 16 E

C
1 1

O
228 128

V C 47

VC 46

VC 44
F 0 0 16 15 14 13 18 16 14 14 18 9 12 12 10 10 12 12 8 17 18 14 16 S 0 0 F

C
O

O
228 128

VC 47

VC 46

VC 44
0 0
G 16 14 12 12 10 13 13 15 15 11 11 14 14 11 11 14 14 18 14 13 13 G

C
0 0

O
228 128

V C 48

VC 45
H 3 3 7 8 8 11 10 7 9 12 S 18 18 13 13 16 16 13 13 7 7 12 9 9 3 3 H

C
O

O
227 127

VC 47

VC 46

VC 44
3 3
J 7 9 9 11 7 9 11 12 17 15 15 S 18 18 17 15 8 8 11 12 J

C
3 3

O
227 127

VC 47

VC 46

VC 44
K 2 2 6 6 S 8 11 10 10 17 16 16 22 23 17 15 S 10 11 S 2 2 K

C
O

O
227 127

VC 48

VC 45
2 1 1 2
L 5 5 4 8 4 4 6 20 20 21 22 23 20 20 10 2 2 L

C
2 1 1 2

O
227 228 128 127

VC 48

V C 45
M 1 1 2 3 3 4 5 5 3 6 23 21 24 24 22 22 24 5 1 1 3 1 1 M

C
O

O
227 127

V C 47

V C 46

VC 44
1 0 0 1
N 2 1 1 1 3 2 2 23 19 19 S 21 24 5 6 6 3 N

C
1 0 0 1

O
227 228 128 127

V C 44
P 0 0 1 S 21 19 19 4 4 0 0 P

C
O
227 127
0 1 1 0
R 0
227
1
227 127
1
127
0 R
T 3
226
3 3
126
3 T
3 0 0 3
U 3
226
0
227 127
0
126
3 U
V 2
226
2 2
126
2 V
2 1 1 2
W 2
226
1
226 126
1
126
2 W
Y Y
1 0 0 1
AA 1
226
0
226 126
0
126
1 AA
AB 1
226
1 1
126
1 AB
0 1 1 0
AC 0
226
1
225 125
1
126
0 AC
AD 0
226
0 0
126
0 AD
3 0 0 3
AE 3
225
0
225 125
0
125
3 AE
VC 68

VC 6 6

VC 65
AF 3 3 2 2 2 23 S 21 22 3 3 AF
C

C
O

O
225 125
VC 67

VC 84
2 1 1 2
AG 4 5 1 1 2 6 1 1 4 24 24 23 21 19 21 23 22 AG
C

C
2 1 1 2
O

O
225 224 124 125
V C 67

V C 84
AH 2 2 4 5 1 3 1 4 4 6 3 4 5 6 20 20 21 19 23 20 20 2 2 AH
C

C
O

O
225 125
VC 68

VC 66

VC 65
1 0 0 1
AJ 2 6 3 5 5 3 3 3 5 6 22 22 19 19 24 24 S AJ
C

C
1 0 0 1
O

O
225 224 124 125
VC 6 7

VC 84
AK 1 1 2 6 9 S 7 7 10 S 8 8 10 17 18 18 16 15 16 16 18 1 1 AK
C

C
O

O
225 125
VC 67

VC 8 4
0 0
AL 8 9 7 7 9 12 10 8 7 12 10 9 17 14 16 S 15 14 18 13 AL
C

C
0 0
O

O
225 125
VC 68

V C 66

VC 65
AM 0 0 10 8 12 12 S 9 11 12 8 7 11 12 9 15 15 14 13 17 17 14 13 S 0 0 AM
C

C
O

O
225 125
VC 68

V C 66

V C 65
3 3
AN 10 11 11 16 16 11 14 14 18 11 14 14 16 11 11 13 10 11 11 9 9 AN
C

C
3 3
O

O
224 124
VC 67

VC 94
AP 3 3 S 14 14 18 18 S 15 13 18 18 18 13 16 9 7 12 12 7 10 12 12 S 3 3 AP
C

C
O

O
224 124
VC 6 8

VC 94

VC 65
2 2
AR 13 13 17 15 16 15 17 13 15 15 17 13 9 7 10 10 7 8 8 6 AR
C

C
2 2
O

O
224 124
VC 6 8

VC 66

VC 6 5
AT 2 2 17 15 22 16 17 20 20 S 17 S 20 S 8 8 6 3 4 6 2 2 AT
C

C
O

O
224 124
V C 67

VC 94

1 1
AU 1 1 19 20 22 24 S 21 22 23 23 19 20 S 5 5 6 3 4 1 1 AU
C

1 1
O

224 224 124 124


V C 67

VC 94

0 0
AV G 19 20 21 24 23 21 19 22 21 19 22 22 4 4 3 1 2 2 5 G AV
V

V
C

0 0
O

224 124
VC 68

VC 66

VC 65
AW 0 0 S 21 23 23 23 19 24 24 21 24 24 2 2 3 1 1 1 5 0 0 AW
C

C
O

O
224 124

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Bank 44 Bank 68 Quad 224 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 84 Quad 225
Bank 46 Bank 94 Quad 226 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Quad 124 Quad 227 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 48 Quad 125 Quad 228 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 65 Quad 126 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 66 Quad 127 # IO_L#N_GC #


MGTREFCLK#P

Bank 67 Quad 128 VRP # MGTREFCLK#N

ug575_c3_43_100815

Figure 3-43: FFVC1517 Package—XCVU065 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


246
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-44

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A A
B V V B
C C
D V V D
E V V E
F F
G V V G
H H
J V V J
K E E K
L V V L
M E E M
N V V N
V V
P 11 10 12 P
R V 1 V R
T E 9 E T
U V 15 6 V U
V V
V 13 14 V
W V V W
Y E E 4 19 17 24 21 E E Y
AA V 22 23 V AA
V V
AB 2 0 8 7 AB
AC V 5 18 V AC
AD E 3 20 E AD
AE E 16 E AE
V V
AF 29 29 AF
AG V 29 29 33 29 V AG
AH E 29 34 29 29 E AH
AJ V 30 28 35 V AJ
AK E 26 26 26 29 E AK
AL V 26 26 29 26 V AL
AM 29 29 26 26 27 AM
AN V 26 26 26 26 26 V AN
AP 25 26 26 26 35 AP
AR V 25 25 25 25 V AR
AT V 25 25 25 V AT
AU 25 25 25 AU
AV 31 32 25 AV
AW 36 37 25 AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_44_100815

Figure 3-44: FFVC1517 Package—XCVU065 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


247
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVC1517 (XCVU080 and XCVU095)


X-Ref Target - Figure 3-45

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

V C 48

VC 45
A 3 3 20 22 24 24 23 22 24 3 3 1 2 1 1 4 23 23 19 3 3 A

C
O

O
228 129

VC 48

V C 45
3 3
B 20 22 21 23 23 22 21 24 6 1 4 2 3 4 2 2 22 19 24 B

C
3 3

O
228 129

VC 47

VC 46

VC 44
2 2
C 2 2 19 21 23 S 19 21 S 5 6 4 5 3 6 6 21 22 24 2 2 C

C
2 2

O
228 228 129 129

VC 48

VC 45
D 1 1 19 S 17 S 19 20 20 5 S 7 8 5 S 7 7 21 S 20 20 1 1 D

C
O

O
228 129

VC 48

VC 45
1 1
E 15 13 17 18 16 17 17 18 9 7 8 10 10 9 9 8 17 15 15 16 E

C
1 1

O
228 129

VC 47

VC 46

VC 44
F 0 0 16 15 14 13 18 16 14 14 18 9 12 12 10 10 12 12 8 17 18 14 16 S 0 0 F

C
O

O
228 129

VC 47

VC 46

VC 44
0 0
G 16 14 12 12 10 13 13 15 15 11 11 14 14 11 11 14 14 18 14 13 13 G

C
0 0

O
228 129

VC 48

VC 45
H 3 3 7 8 8 11 10 7 9 12 S 18 18 13 13 16 16 13 13 7 7 12 9 9 3 3 H

C
O

O
227 128

VC 47

VC 46

VC 44
3 3
J 7 9 9 11 7 9 11 12 17 15 15 S 18 18 17 15 8 8 11 12 J

C
3 3

O
227 128

VC 47

V C 46

VC 44
K 2 2 6 6 S 8 11 10 10 17 16 16 22 23 17 15 S 10 11 S 2 2 K

C
O

O
227 128

VC 4 8

VC 45
2 1 1 2
L 5 5 4 8 4 4 6 20 20 21 22 23 20 20 10 2 2 L

C
2 1 1 2

O
227 228 129 128

VC 48

VC 45
M 1 1 2 3 3 4 5 5 3 6 23 21 24 24 22 22 24 5 1 1 3 1 1 M

C
O

O
227 128

V C 47

V C 46

VC 44
1 0 0 1
N 2 1 1 1 3 2 2 23 19 19 S 21 24 5 6 6 3 N

C
1 0 0 1

O
227 228 129 128

VC 44
P 0 0 1 S 21 19 19 4 4 0 0 P

C
O
227 128
0 1 1 0
R 0
227
1
227 128
1
128
0 R
T 3
226
3 3
127
3 T
3 0 0 3
U 3
226
0
227 128
0
127
3 U
V 2
226
2 2
127
2 V
2 1 1 2
W 2
226
1
226 127
1
127
2 W
Y Y
1 0 0 1
AA 1
226
0
226 127
0
127
1 AA
AB 1
226
1 1
127
1 AB
0 1 1 0
AC 0
226
1
225 126
1
127
0 AC
AD 0
226
0 0
127
0 AD
3 0 0 3
AE 3
225
0
225 126
0
126
3 AE
VC 68

VC 66

VC 65
AF 3 3 2 2 2 23 S 21 22 3 3 AF
C

C
O

O
225 126
V C 67

VC 84
2 1 1 2
AG 4 5 1 1 2 6 1 1 4 24 24 23 21 19 21 23 22 AG
C

C
2 1 1 2
O

O
225 224 125 126
V C 67

VC 84
AH 2 2 4 5 1 3 1 4 4 6 3 4 5 6 20 20 21 19 23 20 20 2 2 AH
C

C
O

O
225 126
VC 6 8

VC 66

VC 65
1 0 0 1
AJ 2 6 3 5 5 3 3 3 5 6 22 22 19 19 24 24 S AJ
C

C
1 0 0 1
O

O
225 224 125 126
VC 67

VC 84
AK 1 1 2 6 9 S 7 7 10 S 8 8 10 17 18 18 16 15 16 16 18 1 1 AK
C

C
O

O
225 126
VC 67

V C 84
0 0
AL 8 9 7 7 9 12 10 8 7 12 10 9 17 14 16 S 15 14 18 13 AL
C

C
0 0
O

O
225 126
V C 68

VC 66

VC 65
AM 0 0 10 8 12 12 S 9 11 12 8 7 11 12 9 15 15 14 13 17 17 14 13 S 0 0 AM
C

C
O

O
225 126
VC 68

VC 66

VC 65
3 3
AN 10 11 11 16 16 11 14 14 18 11 14 14 16 11 11 13 10 11 11 9 9 AN
C

C
3 3
O

O
224 125
VC 67

VC 94
AP 3 3 S 14 14 18 18 S 15 13 18 18 18 13 16 9 7 12 12 7 10 12 12 S 3 3 AP
C

C
O

O
224 125
VC 68

VC 94

VC 65
2 2
AR 13 13 17 15 16 15 17 13 15 15 17 13 9 7 10 10 7 8 8 6 AR
C

C
2 2
O

O
224 125
VC 68

VC 66

VC 65
AT 2 2 17 15 22 16 17 20 20 S 17 S 20 S 8 8 6 3 4 6 2 2 AT
C

C
O

O
224 125
V C 67

V C 94

1 1
AU 1 1 19 20 22 24 S 21 22 23 23 19 20 S 5 5 6 3 4 1 1 AU
C

1 1
O

224 224 125 125


VC 67

V C 94

0 0
AV G 19 20 21 24 23 21 19 22 21 19 22 22 4 4 3 1 2 2 5 G AV
V

V
C

0 0
O

224 125
V C 68

VC 66

VC 65
AW 0 0 S 21 23 23 23 19 24 24 21 24 24 2 2 3 1 1 1 5 0 0 AW
C

C
O

O
224 125

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Bank 44 Bank 68 Quad 224 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 84 Quad 225
Bank 46 Bank 94 Quad 226 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Quad 125 Quad 227 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 48 Quad 126 Quad 228 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 65 Quad 127 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 66 Quad 128 # IO_L#N_GC #


MGTREFCLK#P

Bank 67 Quad 129 VRP # MGTREFCLK#N

ug575_c3_45_100815

Figure 3-45: FFVC1517 Package—XCVU080 and XCVU095 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


248
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-46

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A A
B V V B
C C
D V V D
E V V E
F F
G V V G
H H
J V V J
K E E K
L V V L
M E E M
N V V N
V V
P 11 10 12 P
R V 1 V R
T E 9 E T
U V 15 6 V U
V V
V 13 14 V
W V V W
Y E E 4 19 17 24 21 E E Y
AA V 22 23 V AA
V V
AB 2 0 8 7 AB
AC V 5 18 V AC
AD E 3 20 E AD
AE E 16 E AE
V V
AF 29 29 AF
AG V 29 29 33 29 V AG
AH E 29 34 29 29 E AH
AJ V 30 28 35 V AJ
AK E 26 26 26 29 E AK
AL V 26 26 29 26 V AL
AM 29 29 26 26 27 AM
AN V 26 26 26 26 26 V AN
AP 25 26 26 26 35 AP
AR V 25 25 25 25 V AR
AT V 25 25 25 V AT
AU 25 25 25 AU
AV 31 32 25 AV
AW 36 37 25 AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_46_100815

Figure 3-46: FFVC1517 Package—XCVU080 and XCVU095 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


249
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVD1517 (XCVU080 and XCVU095)


X-Ref Target - Figure 3-47

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

VC 71
3 3
A 18 15 24 21 21 24 22 20 20 3 3 A

C
3 3

O
131 130 130

VC 70
2
B 18 15 22 24 23 24 22 23 21 3 3 2 2 B

C
2

O
131 130 130

V C 70
2 1
C 16 20 22 19 23 23 19 19 21 1 1 C

C
2 1

O
131 130 130

V C 71
0
D S 16 20 19 S S 17 15 S 2 2 0 0 D

C
0

O
131 130 130

VC 71

VC 7 0
3 1
E 3 3 13 13 17 9 11 17 15 13 1 1 3 3 E

C
3 1

O
231 231 131 131 129

VC 70
2 1 3
F 2 2 14 14 17 9 7 11 14 13 18 0 0 F

C
2 1 3

O
231 231 131 131 129

V C 70
1 0
G 12 11 11 9 7 12 12 14 18 2 2 G

C
1 0

O
231 131 129

VC 71
0 0 2
H 1 1 12 7 9 10 10 8 8 16 16 24 24 S H

C
0 0 2

O
231 231 131 129

V C 71

V C 70
J 0 0 S 10 10 7 S 3 3 2 18 16 16 21 21 22 22 23 23 1 1 J

C
O

O
231 129

VC 70

VC 69
3 1 1
K 3 3 8 8 5 5 6 5 2 4 4 18 15 15 14 14 20 20 K

C
3 1 1

O
230 230 130 129

V C 71

VC 6 9
2
L 1 3 4 4 6 5 6 1 17 17 S S 13 13 19 19 0 0 L

C
2

O
230 129

VC 71

VC 69
1 0 0
M 2 2 1 3 2 2 6 1 10 10 12 12 5 5 6 M

C
1 0 0

O
230 230 130 129

VC 69
1
N 1 1 8 11 11 3 3 6 3 3 N

C
1

O
230 231 128

VC 69
0 0 1 3
P 0 0 8 9 9 1 1 4 4 P

C
0 0 1 3

O
230 230 231 129 128

VC 69
3 1
R 7 7 2 2 2 2 R

C
3 1

O
229 230 128
2 0 0 2
T 2
229
3
229
3 0
230 129
0
128
2 T
1
U 2
229
2 1
229
1
128
1 U
1 1
V 1
229
1
229
1 0
128
0
128
1 V
0 0 1 0
W 0
229
0
229 128
1
128
0 W
3 0 3
Y G Y

V
3 0 0 0 3
228 229 128 127
1 1
AA 3
228
3 1
228 127
1 3
127
3 AA
2 0 2
AB 2
228
2
228
2
127
0
127
2 AB
1 0
AC 1
228
0
228
2
127
2 AC
0 1 1 1
AD 0
228
1
228
1
1
227
23 23 VC 84
S 126
1
127
1 AD

VC 66
0
AE 0 0 21 21 S S S 23 24 24 S 10 10 1 1 AE
C

C
0
O

O
228 227 127

VC 66

V C 67
3 1 0 0
AF 3 3 19 19 22 24 23 20 20 22 18 17 16 16 23 22 22 9 9 AF

C
3 1 0 0

O
227 227 226 126 127

VC 65

VC 66
2 0
AG 20 22 24 23 21 22 18 17 15 15 21 21 8 8 7 0 0 AG
C

C
2 0

O
227 226 127
VC 84

VC 66
1 1 1 3
AH 2 2 20 18 18 21 19 19 24 12 14 14 13 20 20 6 12 7 AH
C

C
1 1 1 3
O

O
227 227 225 125 126
V C 84

V C 66
0
AJ 1 1 16 17 17 16 24 S 12 11 13 10 19 6 12 11 11 3 3 AJ
C

C
0
O

O
227 225 126
VC 65

VC 67
0 1 0 2
AK 0 0 16 14 15 15 S 16 18 9 9 11 10 19 1 3 4 4 AK
C

C
0 1 0 2
O

O
227 227 224 125 126
VC 65

VC 67
0
AL 3 3 S 14 13 13 17 15 15 18 7 7 8 8 1 3 5 5 2 2 AL
C

C
0
O

O
226 224 126

VC 66
3 1 1
AM 2 2 3 3 12 11 17 14 14 6 6 4 2 2 AM
C
3 1 1

O
226 226 224 124 126
V C 65

2 3 3
AN 2 2 12 11 9 13 13 5 2 2 4 1 1 AN
C

2 3 3
O

226 224 224 124 126


VC 94

1 2 0 0
AP 1 1 S 8 9 12 12 11 5 3 3 3 3 AP
C

1 2 0 0
O

226 226 224 124 124 126


VC 94

V C 66

0 2
AR 0 0 1 1 8 7 7 S 11 1 1 2 2 0 0 AR
C

0 2
O

226 226 224 124 124 126


V C 65

3 1 3
AT 3 3 10 10 S 10 10 9 6 6 5 1 1 3 3 AT
C

3 1 3
O

225 225 224 124 125 125


VC 94

2 1 2
AU 2 2 0 0 6 6 5 3 7 9 2 4 5 2 2 AU
C

2 1 2
O

225 225 224 124 125 125


VC 94

1 0 1
AV 1 1 4 5 3 1 7 2 4 1 3 0 0 1 1 AV
C

1 0 1
O

225 225 224 124 125 125


V C 65

0 0 0
AW G 4 2 2 1 8 8 1 3 AW
V

0 0 0 0
C

0 0 0
O

225 225 124 125 125

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Bank 65 Quad 124 Quad 224 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 66 Quad 125 Quad 225
Bank 67 Quad 126 Quad 226 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 69 Quad 127 Quad 227 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 70 Quad 128 Quad 228 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 71 Quad 129 Quad 229 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 84 Quad 130 Quad 230 # IO_L#N_GC #


MGTREFCLK#P

Bank 94 Quad 131 Quad 231 VRP # MGTREFCLK#N

ug575_c3_47_100815

Figure 3-47: FFVD1517 Package—XCVU080 and XCVU095 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


250
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-48

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A n n n n E n n V V A
B n n V n n E n n E E V B
C V n n V n n E n n V V C
D n n V n n E n n E E V D
E V V E n n V V E
F V E n n E E V V F
G V V n n E n n E G
H V E n n V H
J V V n n E E J
K V E n n V K
L V E n n E E L
M V E n n 15 V M
N V E E 1 E N
P V E 9 V P
R V E 12 E R
V
T V 11 V T
V
U V E 10 U
V
V V 13 20 0 V
V
W V E 6 W
V
Y V 19 24 21 Y
V
AA V E 14 22 23 AA
V
AB V 16 18 17 8 7 n n V AB
V
AC V E 4 AC
AD V E 5 V AD
AE V E 3 35 E AE
AF V E 2 33 29 29 29 V AF
AG V E 34 29 29 E AG
AH V E 29 29 29 30 V AH
AJ V E E 26 28 E AJ
AK V E 27 26 29 V AK
AL V V E 29 26 26 29 E AL
AM V E 29 26 26 V AM
AN V V E 26 26 E AN
AP V E E 26 26 26 E V V AP
AR V V E 35 26 V V AR
AT V E E 26 26 26 25 25 25 E V AT
AU V V E 25 26 31 25 25 V V AU
AV V E E 25 32 25 36 25 E V AV
AW E 25 25 25 37 25 V V AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_48_100815

Figure 3-48: FFVD1517 Package—XCVU080 and XCVU095 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


251
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVD1517 (XCVU125)
X-Ref Target - Figure 3-49

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

VC 73
3 3 3
A G 18 15 24 21 21 24 22 20 20 A

V
3 3 3 3

C
3 3 3

O
232 232 132 131 131

V C 72
2 3 2
B 2 2 18 15 22 24 23 24 22 23 21 3 3 2 2 B

C
2 3 2

O
232 232 233 132 131 131

V C 72
1 2 1
C 1 1 3 3 16 20 22 19 23 23 19 19 21 1 1 C

C
1 2 1

O
232 232 233 132 131 131

VC 7 3
0 2 0
D 0 0 S 16 20 19 S S 17 15 S 2 2 0 0 D

C
0 2 0

O
232 232 233 132 131 131

VC 73

V C 72
3 1
E 3 3 2 2 13 13 17 9 11 17 15 13 1 1 3 3 E

C
3 1

O
231 231 233 132 132 130

VC 72
2 1 1 3
F 2 2 14 14 17 9 7 11 14 13 18 0 0 F

C
2 1 1 3

O
231 231 233 132 132 130

VC 72
1 0 0
G 1 1 12 11 11 9 7 12 12 14 18 2 2 G

C
1 0 0

O
231 233 233 132 130

V C 73
0 0 2
H 1 1 0 0 12 7 9 10 10 8 8 16 16 24 24 S H

C
0 0 2

O
231 231 233 132 130

VC 73

VC 72
1
J 0 0 S 10 10 7 S 3 3 2 18 16 16 21 21 22 22 23 23 1 1 J

C
1

O
231 233 130

V C 72

V C 71
3 0 1 1
K 3 3 8 8 5 5 6 5 2 4 4 18 15 15 14 14 20 20 K

C
3 0 1 1

O
230 230 233 131 130

V C 73

VC 71
2 1
L 1 3 4 4 6 5 6 1 17 17 S S 13 13 19 19 0 0 L

C
2 1

O
230 232 130

VC 73

VC 71
1 0 0 0
M 2 2 1 3 2 2 6 1 10 10 12 12 5 5 6 M

C
1 0 0 0

O
230 230 232 131 130

VC 71
1
N 1 1 8 11 11 3 3 6 3 3 N

C
1

O
230 231 129

VC 7 1
0 0 1 3
P 0 0 8 9 9 1 1 4 4 P

C
0 0 1 3

O
230 230 231 130 129

VC 71
3 1
R 7 7 2 2 2 2 R

C
3 1

O
229 230 129
2 0 0 2
T 2
229
3
229
3 0
230 130
0
129
2 T
1
U 2
229
2 1
229
1
129
1 U
1 1
V 1
229
1
229
1 0
129
0
129
1 V
0 0 1 0
W 0
229
0
229 129
1
129
0 W
3 0 3
Y G Y

V
3 0 0 0 3
228 229 129 127
1 1
AA 3
228
3 1
228 127
1 3
127
3 AA
2 0 2
AB G AB

V
2 2 2 0 2
228 228 127 127
1 0
AC 1
228
0
228
2
127
2 AC
0 1 1 1
AD 0
228
1
228
1
1
227
23 23 VC 84
S 126
1
127
1 AD

VC 66
0
AE 0 0 21 21 S S S 23 24 24 S 10 10 1 1 AE
C

C
0
O

O
228 227 127

VC 66

VC 67
3 1 0 0
AF 3 3 19 19 22 24 23 20 20 22 18 17 16 16 23 22 22 9 9 AF

C
3 1 0 0

O
227 227 226 126 127

VC 65

VC 66
2 0
AG 20 22 24 23 21 22 18 17 15 15 21 21 8 8 7 0 0 AG
C

C
2 0

O
227 226 127
V C 84

V C 66
1 1 1 3
AH 2 2 20 18 18 21 19 19 24 12 14 14 13 20 20 6 12 7 AH
C

C
1 1 1 3
O

O
227 227 225 125 126
VC 84

V C 66
0
AJ 1 1 16 17 17 16 24 S 12 11 13 10 19 6 12 11 11 3 3 AJ
C

C
0
O

O
227 225 126
VC 6 5

VC 6 7
0 1 0 2
AK 0 0 16 14 15 15 S 16 18 9 9 11 10 19 1 3 4 4 AK
C

C
0 1 0 2
O

O
227 227 224 125 126
VC 65

VC 67
0
AL 3 3 S 14 13 13 17 15 15 18 7 7 8 8 1 3 5 5 2 2 AL
C

C
0
O

O
226 224 126

VC 66
3 1 1
AM 2 2 3 3 12 11 17 14 14 6 6 4 2 2 AM
C
3 1 1

O
226 226 224 124 126
VC 65

2 3 3
AN 2 2 12 11 9 13 13 5 2 2 4 1 1 AN
C

2 3 3
O

226 224 224 124 126


VC 94

1 2 0 0
AP 1 1 S 8 9 12 12 11 5 3 3 3 3 AP
C

1 2 0 0
O

226 226 224 124 124 126


VC 94

VC 66

0 2
AR 0 0 1 1 8 7 7 S 11 1 1 2 2 0 0 AR
C

0 2
O

226 226 224 124 124 126


VC 6 5

3 1 3
AT 3 3 10 10 S 10 10 9 6 6 5 1 1 3 3 AT
C

3 1 3
O

225 225 224 124 125 125


VC 94

2 1 2
AU 2 2 0 0 6 6 5 3 7 9 2 4 5 2 2 AU
C

2 1 2
O

225 225 224 124 125 125


V C 94

1 0 1
AV 1 1 4 5 3 1 7 2 4 1 3 0 0 1 1 AV
C

1 0 1
O

225 225 224 124 125 125


V C 65

0 0 0
AW G 4 2 2 1 8 8 1 3 AW
V

0 0 0 0
C

0 0 0
O

225 225 124 125 125

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Bank 65 Quad 124 Quad 224 Quad 232 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 66 Quad 125 Quad 225 Quad 233
Bank 67 Quad 126 Quad 226 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 71 Quad 127 Quad 227 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 72 Quad 129 Quad 228 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 73 Quad 130 Quad 229 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 84 Quad 131 Quad 230 # IO_L#N_GC #


MGTREFCLK#P

Bank 94 Quad 132 Quad 231 VRP # MGTREFCLK#N

ug575_c3_49_100815

Figure 3-49: FLVD1517 Package—XCVU125 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


252
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-50

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A E V V A
B V E E E V B
C V V E V V C
D V E E E V D
E V V E V V E
F V E E E V V F
G V V E E G
H V E V H
J V V E E J
K V E V K
L V E E E L
M V E 15 V M
N V E E 1 E N
P V E 9 V P
R V E 12 E R
V
T V 11 V T
V
U V E 10 U
V
V V 13 20 0 V
V
W V E 6 W
V
Y V 19 24 21 Y
V
AA V E 14 22 23 AA
V
AB V 16 18 17 8 7 V AB
V
AC V E 4 AC
AD V E 5 V AD
AE V E 3 35 E AE
AF V E 2 33 29 29 29 V AF
AG V E 34 29 29 E AG
AH V E 29 29 29 30 V AH
AJ V E E 26 28 E AJ
AK V E 27 26 29 V AK
AL V V E 29 26 26 29 E AL
AM V E 29 26 26 V AM
AN V V E 26 26 E AN
AP V E E 26 26 26 E V V AP
AR V V E 35 26 V V AR
AT V E E 26 26 26 25 25 25 E V AT
AU V V E 25 26 31 25 25 V V AU
AV V E E 25 32 25 36 25 E V AV
AW E 25 25 25 37 25 V V AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_50_100815

Figure 3-50: FLVD1517 Package—XCVU125 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


253
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVB1760 (XCVU080 and XCVU095)


X-Ref Target - Figure 3-51

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

VC 71

VC 51
A 24 24 21 23 24 24 23 23 21 21 23 23 S 23 23 24 17 17 16 G A

V
3 3

C
O

O
131

VC 70

V C 49

VC 50
3
B 22 21 23 22 22 21 S 22 22 19 S 8 10 21 24 22 15 16 B

C
3

O
131

VC 71

VC 50
2
C 22 20 19 20 19 19 21 20 24 24 19 8 10 19 21 22 15 S 18 2 2 C

C
2

O
131 131

VC 71

VC 51
1
D 20 19 S 20 18 17 17 20 15 17 17 11 19 20 20 13 14 18 D

C
1

O
131

VC 70

VC 4 9

VC 50
3 0
E 3 3 17 S 18 16 16 18 15 16 16 15 12 11 9 S 11 13 14 3 1 1 E

C
3 0

O
231 231 131 131

V C 49

VC 50
2
F 2 2 17 16 16 18 14 14 13 15 S 18 18 12 9 9 9 11 12 3 1 F

C
2

O
231 231

V C 71

VC 50
1 1 3
G 1 1 15 14 14 10 12 13 S 14 14 13 6 6 7 10 10 12 2 1 0 0 G

C
1 1 3

O
231 231 231 131 130

VC 70

VC 51
0
H 0 0 15 13 13 10 12 11 11 12 11 11 13 5 7 S 7 8 2 5 6 3 3 H

C
0

O
231 231 130

V C 70

V C 49

VC 50
3 2
J 3 3 10 10 12 12 11 8 9 S 10 12 9 S 4 5 7 8 5 6 2 2 J

C
3 2

O
230 230 130 130

VC 71

VC 48
2 0
K 8 8 9 9 11 8 7 9 8 10 7 9 4 3 3 15 17 17 4 4 1 1 K

C
2 0

O
230 231 130

VC 71

VC 5 1
1 1 1
L 2 2 6 5 7 7 S 7 6 6 8 7 6 6 2 1 15 16 13 10 10 9 L

C
1 1 1

O
230 230 131 130

VC 70

V C 49

VC 48
1
M 1 1 6 4 5 1 3 3 5 4 5 5 3 4 2 1 16 13 11 12 9 0 0 M

C
1

O
230 230 130

VC 70

VC 4 9

VC 48
0 0 0
N 0 0 4 3 3 1 1 5 2 4 1 3 2 4 18 18 14 14 11 12 8 7 N

C
0 0 0

O
230 230 131 130

VC 71

VC 48
3 0
P 2 2 1 2 1 2 S 23 23 19 S 8 7 3 3 P

C
3 0

O
229 230 129

VC 48
2 1 3
R 3 3 S 21 19 6 6 R

C
2 1 3

O
229 229 130 129

VC 48
1
T 2 2 21 24 20 3 5 5 2 2 T

C
1

O
229 229 129

VC 48
1 0 2
U 1 1 24 20 2 3 1 U

C
1 0 2

O
229 229 130 129
0
V 0
229
0 0
229
22 22 2 4 4 1 1
129
1 V

V C 47
0 1 1
W 3 3 24 19 19 18 16 16 W

C
0 1 1

O
229 228 129 129

VC 47
3 1
Y 22 24 21 18 15 15 0 0 Y

C
3 1

O
228 228 129
2 0 0
AA 2
228
2
228
2 22 23 23 21 14 14 17 129
0
129
0 AA

VC 47
1 0
AB S 20 20 13 13 17 3 3 AB

C
1 0

O
228 228 128

VC 4 7
0 1 3
AC 1 1 6 6 11 12 12 S AC

C
0 1 3

O
228 228 128 128

VC 47
1
AD 0 0 3 4 4 11 10 10 2 2 AD

C
1

O
228 227 128

VC 47
3 0 2
AE 3 3 3 2 2 S 8 AE

C
3 0 2

O
227 227 128 128

VC 47
0
AF 2 2 1 1 5 5 9 8 7 1 1 AF

C
0

O
227 227 128

VC 46
2 1
AG 1 1 24 24 23 23 21 16 16 18 9 7 AG

C
2 1

O
227 227 128
VC 66

VC 67
1 1
AH 23 23 21 S 7 4 3 20 S 24 21 17 17 18 S 24 22 0 0 AH
C

C
1 1
O

O
227 226 128
VC 66

VC 67

VC 46
0 0
AJ 0 0 22 22 21 9 9 7 2 2 4 3 14 20 22 24 15 15 14 14 24 22 AJ
C

C
0 0
O

O
227 227 128
V C 67

VC 46

V C 45
3 0
AK 20 20 19 19 12 12 S 8 1 1 5 14 22 19 19 S 13 13 21 19 20 20 23 23 AK
C

C
3 0
O

O
226 226
VC 66

V C 67

VC 46
2
AL 3 3 17 13 13 11 11 10 8 6 6 5 13 13 17 S 12 12 21 19 23 23 19 19 21 17 S AL
C

C
2
O

O
226 226
V C 66

V C 67

V C 46
1
AM 2 2 17 15 18 14 5 3 10 7 9 11 11 S 17 15 10 11 11 1 4 6 6 22 21 17 15 15 AM
C

C
1
O

O
226 225
VC 66

VC 67

VC 46

VC 45
1
AN 1 1 15 18 14 5 3 1 7 9 12 12 16 15 10 9 9 7 1 3 4 S 22 24 13 18 18 AN
C

C
1
O

O
226 226
VC 66

VC 65

VC 45
0
AP 0 0 S 6 6 1 2 8 8 10 S 16 18 18 S 8 8 7 2 3 5 24 13 14 16 AP
C

C
0
O

O
226 226
VC 8 4

V C 65

VC 46
3 0
AR 3 3 16 16 4 4 2 2 10 5 5 24 23 5 2 5 20 20 8 14 16 9 AR
C

C
3 0
O

O
225 225 225
V C 94

V C 44

VC 45
2
AT 2 2 23 23 21 S 5 3 3 2 6 6 3 3 24 23 2 2 3 5 15 17 7 8 11 11 9 AT
C

C
2
O

O
225 225
VC 94

VC 6 5

VC 45
1 1
AU 1 1 19 21 24 24 5 4 4 4 1 20 20 19 21 4 4 3 15 17 18 7 12 12 10 10 AU
C

C
1 1
O

O
225 225 224
VC 8 4

VC 65

VC 44
0
AV 0 0 19 22 22 20 20 1 6 2 2 4 1 22 22 19 21 1 1 13 13 16 18 S 5 5 AV
C

C
0
O

O
225 225
V C 84

VC 65

VC 44

VC 45
3 0
AW 3 3 13 13 14 11 1 6 S 8 12 11 11 13 17 17 6 6 14 14 S 16 23 1 3 3 AW
C

C
3 0
O

O
224 224 224
VC 94

VC 44

V C 45
2
AY 2 2 15 15 14 11 12 12 8 8 7 12 14 14 13 15 12 12 11 11 22 19 19 23 1 6 6 AY
C

C
2
O

O
224 224
VC 94

VC 65

VC 44
1
BA G 17 18 18 16 9 7 7 8 7 9 9 16 S 15 8 10 9 9 S 22 21 21 4 2 2 BA
V

1 1
C

C
1
O

O
224 224
VC 84

V C 65

VC 44

0
BB 0 0 17 16 S S 9 10 10 10 10 S 16 18 18 8 10 7 7 20 20 24 24 S 4 BB
C

0
O

224 224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Bank 44 Bank 65 Quad 129 Quad 229 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 66 Quad 130 Quad 230
Bank 46 Bank 67 Quad 131 Quad 231 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Bank 70 Quad 224 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 48 Bank 71 Quad 225 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 49 Bank 84 Quad 226 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 50 Bank 94 Quad 227 # IO_L#N_GC #


MGTREFCLK#P

Bank 51 Quad 128 Quad 228 VRP # MGTREFCLK#N

ug575_c3_51_100815

Figure 3-51: FFVB1760 Package—XCVU080 and XCVU095 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


254
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-52

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A n n n n n n A
B n n E n n E V V B
C n n V n n E n n C
D V n n V n n E V D
E V E n n E
F E E V V F
G V E V G
H V E E H
J V E V J
K V E K
L V E V L
M V E E M
N V E V N
V
P V P
V
R V 6 V R
T V E 15 E T
U V E 1 19 V U
V
V V 9 V
V
W V 10 18 V W
Y V 11 E Y
AA V E 12 20 24 21 V AA
V
AB V 13 22 23 AB
V
AC V 14 0 8 7 V AC
AD V E 16 E AD
AE V E 4 17 V AE
AF V 5 E AF
V
AG V 3 n n V AG
AH V E 2 E AH
AJ E AJ
AK V AK
AL V E AL
AM V E AM
AN V E AN
AP V 35 AP
AR V E 25 25 30 33 AR
AT V E E 25 25 25 25 28 34 AT
AU E 25 25 36 29 29 29 29 AU
AV V E 31 32 25 37 29 29 29 29 AV
AW V E 25 26 26 26 26 29 29 AW
AY V E E 25 25 26 26 26 26 26 AY
BA V E 25 26 26 26 27 26 BA
BB 26 26 35 26 29 29 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_52_100815

Figure 3-52: FFVB1760 Package—XCVU080 and XCVU095 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


255
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVB1760 (XCVU125)
X-Ref Target - Figure 3-53

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

VC 50

VC 53
3
A G 24 24 21 23 24 24 23 23 21 21 23 23 S 23 23 24 17 17 16 G A

V
3 3 3 3

C
3

O
233 233 132

V C 49

V C 51

V C 52
2 3
B 2 2 22 21 23 22 22 21 S 22 22 19 S 8 10 21 24 22 15 16 B

C
2 3

O
233 233 132

VC 5 0

VC 52
1 1 2
C 1 1 22 20 19 20 19 19 21 20 24 24 19 8 10 19 21 22 15 S 18 2 2 C

C
1 1 2

O
233 233 233 132 132

VC 50

VC 53
0 1
D 0 0 20 19 S 20 18 17 17 20 15 17 17 11 19 20 20 13 14 18 D

C
0 1

O
233 233 132

VC 49

V C 51

VC 52
3 0 0
E 3 3 17 S 18 16 16 18 15 16 16 15 12 11 9 S 11 13 14 3 1 1 E

C
3 0 0

O
232 232 233 132 132

VC 51

V C 52
2
F 2 2 17 16 16 18 14 14 13 15 S 18 18 12 9 9 9 11 12 3 1 F

C
2

O
232 232

VC 5 0

V C 52
1 1 3
G 1 1 15 14 14 10 12 13 S 14 14 13 6 6 7 10 10 12 2 1 0 0 G

C
1 1 3

O
232 232 232 132 131

VC 49

VC 53
0
H 0 0 15 13 13 10 12 11 11 12 11 11 13 5 7 S 7 8 2 5 6 3 3 H

C
0

O
232 232 131

VC 49

VC 51

VC 52
3 2
J 3 3 10 10 12 12 11 8 9 S 10 12 9 S 4 5 7 8 5 6 2 2 J

C
3 2

O
231 231 131 131

VC 50

VC 48
2 0
K 8 8 9 9 11 8 7 9 8 10 7 9 4 3 3 15 17 17 4 4 1 1 K

C
2 0

O
231 232 131

VC 50

V C 53
1 1 1
L 2 2 6 5 7 7 S 7 6 6 8 7 6 6 2 1 15 16 13 10 10 9 L

C
1 1 1

O
231 231 132 131

VC 4 9

VC 51

V C 48
1
M 1 1 6 4 5 1 3 3 5 4 5 5 3 4 2 1 16 13 11 12 9 0 0 M

C
1

O
231 231 131

V C 49

VC 51

VC 48
0 0 0
N 0 0 4 3 3 1 1 5 2 4 1 3 2 4 18 18 14 14 11 12 8 7 N

C
0 0 0

O
231 231 132 131

VC 50

VC 48
3 0
P 2 2 1 2 1 2 S 23 23 19 S 8 7 3 3 P

C
3 0

O
230 231 130

VC 48
2 1 3
R 3 3 S 21 19 6 6 R

C
2 1 3

O
230 230 131 130

VC 48
1
T 2 2 21 24 20 3 5 5 2 2 T

C
1

O
230 230 130

V C 48
1 0 2
U 1 1 24 20 2 3 1 U

C
1 0 2

O
230 230 131 130
0
V 0
230
0 0
230
22 22 2 4 4 1 1
130
1 V

V C 47
0 1 1
W 3 3 24 19 19 18 16 16 W

C
0 1 1

O
230 228 130 130

V C 47
3 1
Y 22 24 21 18 15 15 0 0 Y

C
3 1

O
228 228 130
2 0 0
AA 2
228
2
228
2 22 23 23 21 14 14 17 130
0
130
0 AA

VC 47
1 0
AB S 20 20 13 13 17 3 3 AB

C
1 0

O
228 228 129

V C 47
0 1 3
AC 1 1 6 6 11 12 12 S AC

C
0 1 3

O
228 228 129 129

V C 47
1
AD 0 0 3 4 4 11 10 10 2 2 AD

C
1

O
228 227 129

VC 47
3 0 2
AE 3 3 3 2 2 S 8 AE

C
3 0 2

O
227 227 129 129

VC 47
0
AF 2 2 1 1 5 5 9 8 7 1 1 AF

C
0

O
227 227 129

VC 46
2 1
AG 1 1 24 24 23 23 21 16 16 18 9 7 AG

C
2 1

O
227 227 129
VC 6 6

VC 67
1 1
AH 23 23 21 S 7 4 3 20 S 24 21 17 17 18 S 24 22 0 0 AH
C

C
1 1
O

O
227 226 129
V C 66

VC 67

V C 46
0 0
AJ 0 0 22 22 21 9 9 7 2 2 4 3 14 20 22 24 15 15 14 14 24 22 AJ
C

C
0 0
O

O
227 227 129
V C 67

VC 46

VC 45
3 0
AK 20 20 19 19 12 12 S 8 1 1 5 14 22 19 19 S 13 13 21 19 20 20 23 23 AK
C

C
3 0
O

O
226 226
VC 66

V C 67

VC 46
2
AL 3 3 17 13 13 11 11 10 8 6 6 5 13 13 17 S 12 12 21 19 23 23 19 19 21 17 S AL
C

C
2
O

O
226 226
V C 66

VC 67

VC 46
1
AM 2 2 17 15 18 14 5 3 10 7 9 11 11 S 17 15 10 11 11 1 4 6 6 22 21 17 15 15 AM
C

C
1
O

O
226 225
V C 66

VC 6 7

VC 46

V C 45
1
AN 1 1 15 18 14 5 3 1 7 9 12 12 16 15 10 9 9 7 1 3 4 S 22 24 13 18 18 AN
C

C
1
O

O
226 226
VC 66

VC 65

VC 45
0
AP 0 0 S 6 6 1 2 8 8 10 S 16 18 18 S 8 8 7 2 3 5 24 13 14 16 AP
C

C
0
O

O
226 226
VC 84

VC 65

V C 46
3 0
AR 3 3 16 16 4 4 2 2 10 5 5 24 23 5 2 5 20 20 8 14 16 9 AR
C

C
3 0
O

O
225 225 225
VC 94

VC 44

V C 45
2
AT 2 2 23 23 21 S 5 3 3 2 6 6 3 3 24 23 2 2 3 5 15 17 7 8 11 11 9 AT
C

C
2
O

O
225 225
VC 94

V C 65

VC 45
1 1
AU 1 1 19 21 24 24 5 4 4 4 1 20 20 19 21 4 4 3 15 17 18 7 12 12 10 10 AU
C

C
1 1
O

O
225 225 224
V C 84

VC 65

VC 44
0
AV 0 0 19 22 22 20 20 1 6 2 2 4 1 22 22 19 21 1 1 13 13 16 18 S 5 5 AV
C

C
0
O

O
225 225
VC 84

VC 65

VC 44

VC 45
3 0
AW 3 3 13 13 14 11 1 6 S 8 12 11 11 13 17 17 6 6 14 14 S 16 23 1 3 3 AW
C

C
3 0
O

O
224 224 224
VC 94

VC 44

VC 45
2
AY 2 2 15 15 14 11 12 12 8 8 7 12 14 14 13 15 12 12 11 11 22 19 19 23 1 6 6 AY
C

C
2
O

O
224 224
VC 94

VC 65

VC 44
1
BA G 17 18 18 16 9 7 7 8 7 9 9 16 S 15 8 10 9 9 S 22 21 21 4 2 2 BA
V

1 1
C

C
1
O

O
224 224
VC 84

VC 65

VC 44

0
BB 0 0 17 16 S S 9 10 10 10 10 S 16 18 18 8 10 7 7 20 20 24 24 S 4 BB
C

0
O

224 224

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Bank 44 Bank 52 Quad 130 Quad 230 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 53 Quad 131 Quad 231
Bank 46 Bank 65 Quad 132 Quad 232 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Bank 66 Quad 224 Quad 233 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#
V

Bank 48 Bank 67 Quad 225 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 49 Bank 84 Quad 226 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 50 Bank 94 Quad 227 # IO_L#N_GC #


MGTREFCLK#P

Bank 51 Quad 129 Quad 228 VRP # MGTREFCLK#N

ug575_c3_53_100815

Figure 3-53: FLVB1760 Package—XCVU125 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


256
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-54

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A A
B E E V V B
C V E C
D V V E V D
E V E E
F E E V V F
G V E V G
H V E E H
J V E V J
K V E K
L V E V L
M V E E M
N V E V N
V
P V P
V
R V 6 V R
T V E 15 E T
U V E 1 19 V U
V
V V 9 V
V
W V 10 18 V W
Y V 11 E Y
AA V E 12 20 24 21 V AA
V
AB V 13 22 23 AB
V
AC V 14 0 8 7 V AC
AD V E 16 E AD
AE V E 4 17 V AE
AF V 5 E AF
V
AG V 3 n n V AG
AH V E 2 E AH
AJ E AJ
AK V AK
AL V E AL
AM V E AM
AN V E AN
AP V 35 AP
AR V E 25 25 30 33 AR
AT V E E 25 25 25 25 28 34 AT
AU E 25 25 36 29 29 29 29 AU
AV V E 31 32 25 37 29 29 29 29 AV
AW V E 25 26 26 26 26 29 29 AW
AY V E E 25 25 26 26 26 26 26 AY
BA V E 25 26 26 26 27 26 BA
BB 26 26 35 26 29 29 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_54_100815

Figure 3-54: FLVB1760 Package—XCVU125 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


257
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVA2104 (XCVU080 and XCVU095)


X-Ref Target - Figure 3-55

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

VC 6 9

VC 71

VC 51

V C 49
A 10 10 S 12 22 22 21 21 22 22 S 24 20 20 S 22 20 S 22 22 21 24 24 23 18 16 16 A

C
O

O
VC 69

V C 70

V C 49
B 9 9 11 12 20 19 24 24 19 19 24 24 23 23 24 22 21 20 23 20 20 21 23 22 22 18 15 3 3 B

C
O

O
130

VC 69

VC 70

VC 50
C 3 3 8 7 7 11 20 19 23 23 20 21 21 24 22 21 21 24 21 19 24 23 19 19 21 20 19 S 15 17 C

C
O

O
230

VC 71

V C 51

VC 49
3
D 8 6 4 4 13 S S 18 20 23 23 S 22 19 23 23 19 24 S 16 17 21 20 S 19 13 17 2 2 D

C
3

O
230 130

VC 69

VC 51

VC 49
3
E 2 2 6 2 13 14 16 16 18 15 15 17 15 15 19 17 17 15 18 16 17 15 7 S 14 14 13 E

C
3

O
230 130

VC 69

VC 7 0

V C 50
2
F 1 1 3 3 2 14 16 17 16 14 14 17 17 18 18 18 13 15 18 14 13 15 7 11 11 6 6 3 1 1 F

C
2

O
230 230 130

VC 69

V C 71

VC 50

VC 49
2
G 0 0 1 1 5 15 17 S 13 13 17 13 13 16 18 13 14 16 14 13 12 10 10 12 12 4 3 G

C
2

O
230 130

VC 71

VC 51

VC 49
1
H 3 3 5 15 18 18 11 12 12 S 14 14 16 S 14 16 11 11 12 10 10 8 9 4 2 2 0 0 H

C
1

O
230 229 130

V C 68

VC 70

VC 50
1 1
J 2 2 21 24 S 7 11 10 S 11 12 8 S 11 12 9 9 7 8 8 9 5 1 1 J

C
1 1

O
229 230 130

VC 70

VC 50
0
K 1 1 21 24 23 23 8 7 9 10 11 12 7 8 11 12 9 S 7 8 21 19 S 5 3 3 K

C
0

O
230 229 129

VC 71

V C 51

VC 48
0 0
L 22 20 20 17 8 9 S 10 9 7 10 10 8 9 6 6 2 21 19 24 17 15 G L

V
0 0

C
0 0

O
229 230 130

VC 68

VC 51

VC 48
3
M 3 3 22 19 19 17 6 3 3 10 9 4 2 8 7 7 4 2 23 22 24 17 15 18 2 2 M

C
3

O
229 228 129

VC 68

VC 70

V C 50
1 1 3
N S 13 13 15 6 5 5 1 4 2 6 4 5 5 5 4 23 22 20 20 16 18 N

C
1 1 3

O
229 130 129

VC 71

VC 50

VC 48
2
P 2 2 16 18 14 15 4 4 2 1 3 5 6 4 5 3 3 3 10 11 13 14 14 16 1 1 P

C
2

O
229 228 129

VC 68

VC 51

VC 48
1 0 0 2
R 16 18 11 14 S 1 1 2 3 5 6 2 1 3 1 1 10 11 12 13 S R

C
1 0 0 2

O
229 229 130 129
VC 68

VC 70

VC 48
0 1
T 1 1 10 12 11 9 9 6 2 1 7 7 12 6 6 4 0 0 T
C

C
0 1
O

O
229 228 129 129
3 1 1
U 3
228
1
228
10 4 12 7 8 8 8 2 4 3
128
3
129
1 U
2 0
V 2
228
0
228
0 3 4 6 7 8 S 2 5 5 129
0 V
V C 68

VC 48
1 0 0
W 3 6 9 1 3 2 2 W
C

C
1 0 0
O

O
228 228 128 129
0 1 3
Y 0
228
3
227
3 5 1 2 9 1 3 128
1
128
3 Y
3 1 2
AA 3
227
1
227
5 1 2 1
128
1
128
2 AA
2 0 1
AB 2
227
2
227
2
128
0
128
1 AB
1 0 0
AC 1
227
0
227
0
128
0
128
0 AC
0 1 3
AD 0
227
1
227
1
127
1
127
3 AD
3 1 2
AE 3
226
1
226
3
127
3
127
2 AE
2 0 1
AF 2
226
0
227
0
127
0
127
1 AF
1 0 0
AG 1
226
0
226
23 24 24 22 2
127
2
127
0 AG

VC 47
0 1
AH 3 3 S 23 21 21 22 AH

C
0 1

O
226 226 126
3 1 3
AJ 3
225
1
225
22 22 17 17 14 19 20 20 1
127
1
126
3 AJ

VC 47
2 0
AK 2 2 21 24 24 20 18 18 14 19 11 S 0 0 AK

C
2 0

O
225 226 126 127
VC 67

VC 8 4

VC 47
0 2
AL 21 19 20 24 24 23 24 S 24 15 16 16 13 11 7 7 3 3 AL
C

C
0 2
O

O
225 126 126
V C 65

V C 47
1 1
AM 1 1 23 23 19 S S 22 22 23 22 22 24 20 24 22 15 S 13 12 12 9 2 2 AM
C

C
1 1
O

O
225 226 125 126
V C 65

VC 45

1 0 1
AN 0 0 15 15 18 17 20 20 21 21 20 20 S 20 22 24 24 10 8 8 9 AN
C

1 0 1
O

226 224 125 126


VC 67

VC 84

V C 47
0
AP 3 3 16 14 18 17 23 23 21 21 19 19 23 23 21 21 23 22 22 10 3 5 5 1 1 1 AP
C

C
0
O

O
225 225 126
VC 84

VC 44

0 0
AR 2 2 16 14 13 S 19 19 16 16 17 17 18 18 19 19 S 23 19 20 3 6 1 AR
C

0 0
O

225 224 126


VC 65

VC 45

VC 47
3
AT 1 1 1 13 7 7 17 18 18 S 13 18 18 16 16 21 21 17 19 20 2 2 6 4 4 0 0 AT
C

C
3
O

O
224 225 126
VC 67

V C 45

VC 46
3
AU 0 0 6 1 11 11 8 17 14 14 15 13 14 16 14 17 17 16 18 17 15 15 S 23 23 21 AU
C

C
3
O

O
225 125
V C 67

VC 84

VC 44

2
AV 16 16 4 6 12 12 9 8 13 13 15 15 14 16 S 14 15 16 14 18 13 S 19 19 24 24 21 3 3 AV
C

2
O

224 125
VC 66

VC 65

VC 44

VC 46
2
AW 3 3 18 18 4 3 2 5 9 S S 12 15 12 12 9 13 13 15 14 11 11 13 20 20 22 22 17 AW
C

C
2
O

O
224 125
VC 67

VC 45

VC 46

1
AY 17 17 13 3 2 5 10 10 S 12 11 7 10 11 11 9 11 11 S S 12 12 10 S 13 18 18 17 2 2 AY
C

1
O

224 125
V C 67

VC 94

V C 44

1
BA 2 2 15 13 S 23 22 22 10 11 7 S 10 7 7 10 12 7 9 9 8 10 16 16 13 15 15 BA
C

1
O

224 125
V C 66

VC 94

VC 44

V C 46
0
BB 15 14 14 S 24 24 23 20 10 8 9 8 8 5 5 10 12 9 7 7 7 8 14 14 11 11 1 1 BB
C

C
0
O

O
224 125
VC 66

V C 65

VC 45

V C 46

0
BC 1 1 12 12 11 3 19 19 21 20 8 9 5 6 2 S 8 8 9 6 5 1 3 3 12 9 S BC
C

0
O

224 125
VC 66

VC 9 4

VC 46

BD G 7 7 11 3 1 4 21 6 6 5 6 2 3 6 6 5 3 2 6 3 5 1 5 8 12 9 BD
V

0 0
C

C
O

125
VC 66

V C 94

VC 44

BE 0 0 8 8 9 9 1 4 5 6 4 4 3 1 4 3 1 4 5 3 1 2 1 3 2 4 5 8 10 7 BE
C

C
O

224
V C 66

VC 65

VC 4 5

VC 46

BF S 10 10 2 2 5 6 2 2 3 1 4 1 4 2 2 1 4 4 1 2 4 6 6 10 7 BF
C

C
O

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Bank 44 Bank 65 Bank 94 Quad 225 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 66 Quad 125 Quad 226
Bank 46 Bank 67 Quad 126 Quad 227 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Bank 68 Quad 127 Quad 228 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#
V

Bank 48 Bank 69 Quad 128 Quad 229 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 49 Bank 70 Quad 129 Quad 230 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 50 Bank 71 Quad 130 # IO_L#N_GC #


MGTREFCLK#P

Bank 51 Bank 84 Quad 224 VRP # MGTREFCLK#N

ug575_c3_55_100815

Figure 3-55: FFVA2104 Package—XCVU080 and XCVU095 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


258
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-56

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
A n n V A
B V V V B
C V V C
D V D
E V E
F V F
G V V G
H V H
J V V J
K V E K
L V V L
M V E M
N V V V N
P E E P
R V V R
V
T V T
U V 10 E V U
V
V E V V V
V
W V E 12 E W
Y E 11 E V Y
V
AA V E E AA
AB E 1 E V AB
AC V E 9 24 21 E E AC
V
AD E 15 19 18 22 23 E V AD
V
AE V E 6 17 8 7 E AE
V
AF E 0 20 E V AF
V
AG V E 13 E AG
AH E 14 V V AH
AJ V E 16 E V AJ
AK E V AK
AL V V E 5 28 30 E V AL
AM V E 4 35 29 29 V AM
AN V E 3 29 29 29 V AN
AP V E 2 34 33 29 E AP
AR V E 29 29 26 26 V AR
AT V E 29 29 29 AT
AU V 29 26 26 V AU
AV V 26 26 26 AV
AW 27 26 26 V AW
AY V 35 26 26 25 AY
BA 26 26 25 V BA
BB V 26 25 26 BB
BC 25 26 25 V BC
BD V 25 25 25 BD
BE V 25 25 25 36 V V BE
BF V 32 31 25 37 25 n n BF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_56_100815

Figure 3-56: FFVA2104 Package—XCVU080 and XCVU095 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


259
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVA2104 (XCVU125)
X-Ref Target - Figure 3-57

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

VC 7 1

VC 7 3

VC 53

VC 51
A G 10 10 S 12 22 22 21 21 22 22 S 24 20 20 S 22 20 S 22 22 21 24 24 23 18 16 16 A

C
O

O
VC 71

VC 7 2

VC 51
B 9 9 11 12 20 19 24 24 19 19 24 24 23 23 24 22 21 20 23 20 20 21 23 22 22 18 15 3 3 B

C
O

O
132

VC 71

VC 72

VC 52
C 3 3 8 7 7 11 20 19 23 23 20 21 21 24 22 21 21 24 21 19 24 23 19 19 21 20 19 S 15 17 C

C
O

O
233

V C 73

VC 53

VC 51
3
D 8 6 4 4 13 S S 18 20 23 23 S 22 19 23 23 19 24 S 16 17 21 20 S 19 13 17 2 2 D

C
3

O
233 132

VC 71

VC 53

V C 51
3
E 2 2 6 2 13 14 16 16 18 15 15 17 15 15 19 17 17 15 18 16 17 15 7 S 14 14 13 E

C
3

O
233 132

VC 71

VC 72

V C 52
2
F 1 1 3 3 2 14 16 17 16 14 14 17 17 18 18 18 13 15 18 14 13 15 7 11 11 6 6 3 1 1 F

C
2

O
233 233 132

VC 71

VC 73

VC 52

VC 51
2
G 0 0 1 1 5 15 17 S 13 13 17 13 13 16 18 13 14 16 14 13 12 10 10 12 12 4 3 G

C
2

O
233 132

VC 73

VC 53

VC 51
1
H 3 3 5 15 18 18 11 12 12 S 14 14 16 S 14 16 11 11 12 10 10 8 9 4 2 2 0 0 H

C
1

O
233 232 132

VC 70

VC 72

VC 52
1 1
J 2 2 21 24 S 7 11 10 S 11 12 8 S 11 12 9 9 7 8 8 9 5 1 1 J

C
1 1

O
232 233 132

VC 72

VC 5 2
0
K 1 1 21 24 23 23 8 7 9 10 11 12 7 8 11 12 9 S 7 8 21 19 S 5 3 3 K

C
0

O
233 232 131

VC 73

VC 53

VC 50
0 0
L 22 20 20 17 8 9 S 10 9 7 10 10 8 9 6 6 2 21 19 24 17 15 G L

V
0 0

C
0 0

O
232 233 132

V C 70

VC 53

V C 50
3
M 3 3 22 19 19 17 6 3 3 10 9 4 2 8 7 7 4 2 23 22 24 17 15 18 2 2 M

C
3

O
232 231 131

VC 70

VC 72

VC 52
1 1 3
N S 13 13 15 6 5 5 1 4 2 6 4 5 5 5 4 23 22 20 20 16 18 N

C
1 1 3

O
232 132 131

VC 7 3

VC 52

V C 50
2
P 2 2 16 18 14 15 4 4 2 1 3 5 6 4 5 3 3 3 10 11 13 14 14 16 1 1 P

C
2

O
232 231 131

VC 70

V C 53

V C 50
1 0 0 2
R 16 18 11 14 S 1 1 2 3 5 6 2 1 3 1 1 10 11 12 13 S R

C
1 0 0 2

O
232 232 132 131
VC 7 0

VC 72

V C 50
0 1
T 1 1 10 12 11 9 9 6 2 1 7 7 12 6 6 4 0 0 T
C

C
0 1
O

O
232 231 131 131
3 1 1
U 3
231
1
231
10 4 12 7 8 8 8 2 4 3
130
3
131
1 U
2 0
V 2
231
0
231
0 3 4 6 7 8 S 2 5 5 131
0 V
VC 70

VC 50
1 0 0
W 3 6 9 1 3 2 2 W
C

C
1 0 0
O

O
231 231 130 131
0 1 3
Y 0
231
3
227
3 5 1 2 9 1 3 130
1
130
3 Y
3 1 2
AA 3
227
1
227
5 1 2 1
130
1
130
2 AA
2 0 1
AB 2
227
2
227
2
130
0
130
1 AB
1 0 0
AC 1
227
0
227
0
130
0
130
0 AC
0 1 3
AD 0
227
1
227
1
127
1
127
3 AD
3 1 2
AE 3
226
1
226
3
127
3
127
2 AE
2 0 1
AF 2
226
0
227
0
127
0
127
1 AF
1 0 0
AG 1
226
0
226
23 24 24 22 2
127
2
127
0 AG

VC 47
0 1
AH 3 3 S 23 21 21 22 AH

C
0 1

O
226 226 126
3 1 3
AJ 3
225
1
225
22 22 17 17 14 19 20 20 1
127
1
126
3 AJ

VC 47
2 0
AK 2 2 21 24 24 20 18 18 14 19 11 S 0 0 AK

C
2 0

O
225 226 126 127
VC 67

V C 84

VC 47
0 2
AL 21 19 20 24 24 23 24 S 24 15 16 16 13 11 7 7 3 3 AL
C

C
0 2
O

O
225 126 126
VC 65

VC 4 7
1 1
AM 1 1 23 23 19 S S 22 22 23 22 22 24 20 24 22 15 S 13 12 12 9 2 2 AM
C

C
1 1
O

O
225 226 125 126
V C 65

V C 45

1 0 1
AN 0 0 15 15 18 17 20 20 21 21 20 20 S 20 22 24 24 10 8 8 9 AN
C

1 0 1
O

226 224 125 126


VC 67

VC 84

VC 47
0
AP 3 3 16 14 18 17 23 23 21 21 19 19 23 23 21 21 23 22 22 10 3 5 5 1 1 1 AP
C

C
0
O

O
225 225 126
VC 84

VC 44

0 0
AR 2 2 16 14 13 S 19 19 16 16 17 17 18 18 19 19 S 23 19 20 3 6 1 AR
C

0 0
O

225 224 126


VC 65

VC 45

VC 47
3
AT 1 1 1 13 7 7 17 18 18 S 13 18 18 16 16 21 21 17 19 20 2 2 6 4 4 0 0 AT
C

C
3
O

O
224 225 126
VC 67

VC 45

V C 46
3
AU 0 0 6 1 11 11 8 17 14 14 15 13 14 16 14 17 17 16 18 17 15 15 S 23 23 21 AU
C

C
3
O

O
225 125
VC 67

VC 84

VC 44

2
AV 16 16 4 6 12 12 9 8 13 13 15 15 14 16 S 14 15 16 14 18 13 S 19 19 24 24 21 3 3 AV
C

2
O

224 125
VC 66

V C 65

VC 44

V C 46
2
AW 3 3 18 18 4 3 2 5 9 S S 12 15 12 12 9 13 13 15 14 11 11 13 20 20 22 22 17 AW
C

C
2
O

O
224 125
VC 67

VC 45

V C 46

1
AY 17 17 13 3 2 5 10 10 S 12 11 7 10 11 11 9 11 11 S S 12 12 10 S 13 18 18 17 2 2 AY
C

1
O

224 125
V C 67

VC 94

VC 4 4

1
BA 2 2 15 13 S 23 22 22 10 11 7 S 10 7 7 10 12 7 9 9 8 10 16 16 13 15 15 BA
C

1
O

224 125
VC 66

VC 94

VC 44

VC 46
0
BB 15 14 14 S 24 24 23 20 10 8 9 8 8 5 5 10 12 9 7 7 7 8 14 14 11 11 1 1 BB
C

C
0
O

O
224 125
VC 66

V C 65

VC 45

VC 46

0
BC 1 1 12 12 11 3 19 19 21 20 8 9 5 6 2 S 8 8 9 6 5 1 3 3 12 9 S BC
C

0
O

224 125
VC 6 6

VC 94

VC 46

BD G 7 7 11 3 1 4 21 6 6 5 6 2 3 6 6 5 3 2 6 3 5 1 5 8 12 9 BD
V

0 0
C

C
O

125
VC 66

VC 94

VC 44

BE 0 0 8 8 9 9 1 4 5 6 4 4 3 1 4 3 1 4 5 3 1 2 1 3 2 4 5 8 10 7 BE
C

C
O

224
V C 66

V C 65

VC 4 5

V C 46

BF S 10 10 2 2 5 6 2 2 3 1 4 1 4 2 2 1 4 4 1 2 4 6 6 10 7 G BF
V
C

C
O

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Bank 44 Bank 65 Bank 94 Quad 225 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 66 Quad 125 Quad 226
Bank 46 Bank 67 Quad 126 Quad 227 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 47 Bank 70 Quad 127 Quad 231 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#
V

Bank 50 Bank 71 Quad 130 Quad 232 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 51 Bank 72 Quad 131 Quad 233 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 52 Bank 73 Quad 132 # IO_L#N_GC #


MGTREFCLK#P

Bank 53 Bank 84 Quad 224 VRP # MGTREFCLK#N

ug575_c3_57_100815

Figure 3-57: FLVA2104 Package—XCVU125 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


260
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-58

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
A V A
B V V V B
C V V C
D V D
E V E
F V F
G V V G
H V H
J V V J
K V E K
L V V L
M V E M
N V V V N
P E E P
R V V R
V
T V T
U V 10 E V U
V
V E V V V
V
W V E 12 E W
Y E 11 E V Y
V
AA V E E AA
AB E 1 E V AB
AC V E 9 24 21 E E AC
V
AD E 15 19 18 22 23 E V AD
V
AE V E 6 17 8 7 E AE
V
AF E 0 20 E V AF
V
AG V E 13 E AG
AH E 14 V V AH
AJ V E 16 E V AJ
AK E V AK
AL V V E 5 28 30 E V AL
AM V E 4 35 29 29 V AM
AN V E 3 29 29 29 V AN
AP V E 2 34 33 29 E AP
AR V E 29 29 26 26 V AR
AT V E 29 29 29 AT
AU V 29 26 26 V AU
AV V 26 26 26 AV
AW 27 26 26 V AW
AY V 35 26 26 25 AY
BA 26 26 25 V BA
BB V 26 25 26 BB
BC 25 26 25 V BC
BD V 25 25 25 BD
BE V 25 25 25 36 V V BE
BF V 32 31 25 37 25 BF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_58_100815

Figure 3-58: FLVA2104 Package—XCVU125 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


261
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVB2104 (XCVU080 and XCVU095)


X-Ref Target - Figure 3-59

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

VC 69

VC 71

VC 5 0
A 21 21 22 24 S 23 24 22 22 23 24 22 22 23 24 22 22 19 17 15 15 10 9 A

C
O

O
VC 69

VC 71

V C 50
B 20 22 23 24 23 24 21 19 23 24 21 19 23 24 S 23 19 17 16 16 10 9 G B

V
C

C
O

O
VC 70

VC 51

VC 50
C 19 20 23 S 22 19 21 19 20 20 21 19 S 20 24 23 21 20 13 13 12 12 C

C
O

O
VC 70

V C 51

VC 50
D 19 S 17 18 22 19 20 20 17 17 18 S 18 20 21 24 21 20 18 14 11 8 7 D

C
O

O
VC 69

VC 71

VC 50
E 15 17 18 16 16 17 17 16 16 18 S 17 18 21 S 23 24 18 14 S 11 8 7 E

C
O

O
VC 70

VC 49
F 15 13 14 18 18 15 15 15 14 14 S 17 16 16 19 23 24 6 6 2 S F

C
O

O
V C 70

V C 51

VC 50
G 13 14 16 16 14 14 S 15 13 13 14 14 15 19 20 21 5 4 2 G

C
O

O
VC 69

VC 71

VC 50
H 9 11 10 10 13 13 10 S 11 12 13 11 11 15 20 21 22 5 4 1 1 H

C
O

O
V C 71

VC 49
J 9 11 12 12 11 12 12 10 11 12 10 13 12 12 16 17 22 3 3 3 3 J

C
O

O
131

VC 70

V C 51
3 1 3
K 3 3 7 8 8 7 11 9 S 8 9 10 10 10 8 16 17 14 18 S K

C
3 1 3

O
231 231 231 131

VC 69

VC 51
2 2
L 2 2 7 5 S 7 8 8 9 8 9 7 7 9 8 7 15 14 18 10 2 2 L

C
2 2

O
231 231 131 131

VC 69

VC 71

VC 49
1 0 1
M 1 1 5 6 1 3 3 6 2 5 5 S 9 7 15 13 13 10 1 1 M

C
1 0 1

O
231 231 231 131 131

VC 70

V C 49
0 1 0
N 0 0 1 2 6 1 2 4 6 2 3 4 6 5 4 11 12 12 9 0 0 N

C
0 1 0

O
231 231 131 131 131

VC 7 0

V C 51
3 1 3
P 3 3 1 2 3 4 2 4 5 1 3 4 6 6 5 4 7 11 S 9 3 3 P

C
3 1 3

O
230 230 230 130 130

V C 69

VC 71

V C 49
2 0 2
R 2 2 3 4 5 1 6 3 2 1 7 8 8 2 2 2 R

C
2 0 2

O
230 230 131 130 130

VC 49
1 0 1
T 1 1 3 2 1 6 3 2 1 1 1 T

C
1 0 1

O
230 230 230 130 130
0 1 0
U 0
230
0
230
0 6 5 3 1 130
1 0
130
0
130
0 U
3 1 3
V 3
229
3
229
3 1
229
5 4 4 3
129
3
129
3 V

V C 46
2 0 2
W 2 2 21 22 24 24 2 2 W

C
2 0 2

O
229 229 130 129 129
1 0 1
Y 1
229
1
229
1 0
229
21 22 23 23 1
129
1
129
1 Y
0 1 0
AA 0
229
0
229
0 19 19 20 129
1 0
129
0
129
0 AA

V C 46
3 1 3
AB 3 3 S 20 3 3 AB

C
3 1 3

O
228 228 228 128 128
2 0 2
AC 2
228
2
228
2 16 17 17 18 129
0 2
128
2
128
2 AC
1 0 1
AD 1
228
1
228
1
0
228
S 16 14 18 1
128
1
128
1 AD

V C 46
0 1 0
AE 0 0 15 13 13 14 0 0 AE

C
0 1 0

O
228 228 128 128 128

VC 46
3 1 3
AF 3 3 15 12 12 9 3 3 AF

C
3 1 3

O
227 227 227 127 127
2 0 2
AG 2
227
2
227
2 5 5 11 11 9 128
0 2
127
2
127
2 AG
1 0 1
AH 1
227
1
227
1 0
227
4 4 10 10 8 7 1
127
1
127
1 AH

VC 46
0 1 0
AJ 0 0 1 2 3 3 6 8 7 0 0 AJ

C
0 1 0

O
227 227 127 127 127

VC 46
3 1 3
AK 3 3 1 2 6 S 3 3 AK

C
3 1 3

O
226 226 226 126 126
VC 66

V C 65

2 0 2
AL 2 2 24 23 22 23 24 24 23 22 21 24 24 24 24 23 S 24 2 2 AL
C

2 0 2
O

226 226 127 126 126


VC 67

VC 84

V C 45
1 0 1
AM 1 1 24 23 21 22 23 24 24 23 22 21 22 23 22 22 23 23 24 1 1 AM
C

C
1 0 1
O

O
226 226 226 126 126
VC 66

V C 44
0 1 0
AN 0 0 21 21 21 19 19 20 19 19 20 21 22 23 20 21 23 22 22 21 0 0 AN
C

C
0 1 0
O

226 226 O 126 126 126


VC 66

VC 65

3 1 3
AP 3 3 22 20 20 S 17 20 18 S 20 21 19 19 20 21 20 19 20 21 3 3 AP
C

3 1 3
O

225 225 225 125 125


VC 67

VC 84

VC 45
2 0 2
AR 2 2 22 19 19 16 17 18 S 16 17 16 S 17 18 20 19 S 20 2 2 AR
C

C
2 0 2
O

O
225 225 126 125 125
VC 84

VC 44

1 0 1
AT 1 1 S S 17 16 15 13 14 16 17 18 16 17 18 18 18 S 19 19 1 1 AT
C

1 0 1
O

225 225 225 125 125


VC 66

V C 65

0 1 0
AU 0 0 15 16 17 18 15 13 14 S 15 18 S 15 15 16 17 17 15 S 0 0 AU
C

0 1 0
O

225 225 125 125 125


V C 67

V C 65

3 1 0 3
AV 3 3 15 16 18 S 11 12 10 15 13 14 13 14 14 16 14 15 18 17 AV
C

3 1 0 3
O

224 224 224 125 124


VC 84

VC 44

2 0 2
AW 13 13 14 14 11 12 9 10 13 14 10 13 12 13 13 14 18 17 16 16 3 3 AW
C

2 0 2
O

224 224 124 124


VC 66

VC 44

1
AY 8 8 12 9 9 7 8 9 11 12 10 11 11 12 11 12 12 15 14 14 AY
C

1
O

124
VC 67

VC 65

VC 45

1 0 1
BA G 10 12 12 7 12 11 11 7 8 7 11 12 10 7 9 9 9 11 10 15 13 12 BA
V

1 0 1
O

224 124 124


V C 67

VC 94

VC 4 5

BB 2 2 10 11 8 8 7 10 10 S 5 6 7 8 9 10 7 8 8 9 8 8 10 13 12 11 10 6 2 2 BB
C

C
O

224 124
VC 68

VC 94

V C 44

V C 45
0 0
BC 9 9 11 7 7 6 6 5 6 4 8 9 S 3 6 6 S 6 7 7 S 7 11 10 6 5 BC
C

C
0 0
O

224 O 124
VC 68

VC 66

VC 65

VC 45

BD 1 1 6 6 S 4 5 5 3 3 4 6 5 2 3 4 3 6 4 4 5 7 8 9 5 4 1 1 BD
C

C
O

224 124
VC 67

VC 94

V C 45

BE 1 2 4 4 5 4 2 3 1 3 6 5 4 2 5 4 2 3 3 2 2 5 8 9 3 2 4 BE
C

C
O

O
VC 68

VC 94

V C 44

BF 0 0 1 2 3 3 5 1 1 2 1 2 2 S 4 1 1 5 2 1 1 3 1 1 S 3 2 1 1 0 0 BF
C

C
O

224 124

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Bank 44 Bank 67 Quad 125 Quad 225 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 68 Quad 126 Quad 226
Bank 46 Bank 69 Quad 127 Quad 227 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 49 Bank 70 Quad 128 Quad 228 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#
V

Bank 50 Bank 71 Quad 129 Quad 229 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 51 Bank 84 Quad 130 Quad 230 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 65 Bank 94 Quad 131 Quad 231 # IO_L#N_GC #


MGTREFCLK#P

Bank 66 Quad 124 Quad 224 VRP # MGTREFCLK#N

ug575_c3_59_100815

Figure 3-59: FFVB2104 Package—XCVU080 and XCVU095 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


262
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-60

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
A n n E n n E n n A
B V E n n B
C n n n n n n E n n V C
D n n n n V n n V n n D
E n n V n n E n n E
F n n n n V n n V V n n F
G n n V n n E n n G
H n n n n V n n V n n H
J n n V n n E n n J
K V n n V K
L V E n n E L
M V E V M
N V E E N
P V E V P
V
R V 12 E R
T V E V T
V
U V 11 E U
V V 10 E V V
W V E 1 V W
V
Y V 9 V Y
AA E 15 V AA
V
AB V V AB
V
AC V 6 19 V AC
AD V 13 E V AD
V
AE V 14 17 18 V AE
AF V E V AF
AG V E 16 0 20 24 21 E AG
V
AH V 5 22 23 V AH
AJ V E 3 8 7 V AJ
V
AK V 2 V AK
AL V E 4 29 30 28 E AL
AM V 29 29 33 E V AM
AN V E 29 34 29 V AN
AP E 29 29 29 E V AP
AR V E 26 35 29 29 E AR
AT V 26 29 29 E V AT
AU V E 27 26 26 V AU
AV E 26 26 26 V AV
AW E 26 26 26 E AW
AY 26 26 26 26 E AY
BA 25 26 26 V V BA
BB 25 25 25 BB
BC V 25 25 35 V BC
BD V 25 25 25 V BD
BE V 25 25 31 25 n n V BE
BF 25 32 36 37 BF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_60_100815

Figure 3-60: FFVB2104 Package—XCVU080 and XCVU095 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


263
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVB2104 (XCVU125)
X-Ref Target - Figure 3-61

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

VC 70

VC 72

VC 51
3
A 3 3 21 21 22 24 S 23 24 22 22 23 24 22 22 23 24 22 22 19 17 15 15 10 9 3 3 A

C
3

O
233 233 133

VC 70

VC 72

VC 51
1
B 20 22 23 24 23 24 21 19 23 24 21 19 23 24 S 23 19 17 16 16 10 9 G B

V
C

C
1

O
233

VC 71

VC 52

VC 51
2
C G 19 20 23 S 22 19 21 19 20 20 21 19 S 20 24 23 21 20 13 13 12 12 C

V
2 2 2 2

C
2

O
233 233 133

VC 71

V C 52

VC 51
1 0 3
D 1 1 19 S 17 18 22 19 20 20 17 17 18 S 18 20 21 24 21 20 18 14 11 8 7 D

C
1 0 3

O
233 233 233 133

VC 70

VC 72

VC 51
0
E 0 0 15 17 18 16 16 17 17 16 16 18 S 17 18 21 S 23 24 18 14 S 11 8 7 1 1 E

C
0

O
233 233 133

VC 7 1

V C 50
3 1 2
F 3 3 15 13 14 18 18 15 15 15 14 14 S 17 16 16 19 23 24 6 6 2 S F

C
3 1 2

O
232 232 232 133

V C 71

V C 52

V C 51
2
G 2 2 13 14 16 16 14 14 S 15 13 13 14 14 15 19 20 21 5 4 2 0 0 G

C
2

O
232 232 133

VC 70

VC 72

VC 51
1 0 1
H 1 1 9 11 10 10 13 13 10 S 11 12 13 11 11 15 20 21 22 5 4 1 1 H

C
1 0 1

O
232 232 232 133

VC 72

V C 50
0 0
J 0 0 9 11 12 12 11 12 12 10 11 12 10 13 12 12 16 17 22 3 3 3 3 J

C
0 0

O
232 232 132 133

VC 71

V C 52
3 1 1 3
K 3 3 7 8 8 7 11 9 S 8 9 10 10 10 8 16 17 14 18 S K

C
3 1 1 3

O
231 231 231 133 132

VC 70

VC 52
2 0 2
L 2 2 7 5 S 7 8 8 9 8 9 7 7 9 8 7 15 14 18 10 2 2 L

C
2 0 2

O
231 231 133 132 132

V C 70

VC 72

VC 50
1 0 1
M 1 1 5 6 1 3 3 6 2 5 5 S 9 7 15 13 13 10 1 1 M

C
1 0 1

O
231 231 231 132 132

V C 71

V C 50
0 1 0
N 0 0 1 2 6 1 2 4 6 2 3 4 6 5 4 11 12 12 9 0 0 N

C
0 1 0

O
231 231 132 132 132

VC 71

VC 5 2
3 1 3
P 3 3 1 2 3 4 2 4 5 1 3 4 6 6 5 4 7 11 S 9 3 3 P

C
3 1 3

O
230 230 230 131 131

VC 70

VC 72

V C 50
2 0 2
R 2 2 3 4 5 1 6 3 2 1 7 8 8 2 2 2 R

C
2 0 2

O
230 230 132 131 131

VC 50
1 0 1
T 1 1 3 2 1 6 3 2 1 1 1 T

C
1 0 1

O
230 230 230 131 131
0 1 0
U 0
230
0
230
0 6 5 3 1 131
1 0
131
0
131
0 U
3 1 3
V 3
229
3
229
3
1
229
5 4 4 3
130
3
130
3 V

V C 46
2 0 2
W 2 2 21 22 24 24 2 2 W

C
2 0 2

O
229 229 131 130 130
1 0 1
Y 1
229
1
229
1 0
229
21 22 23 23 1
130
1
130
1 Y
0 1 0
AA 0
229
0
229
0 19 19 20 130
1 0
130
0
130
0 AA

VC 46
3 1 3
AB 3 3 S 20 3 3 AB

C
3 1 3

O
228 228 228 129 129
2 0 2
AC 2
228
2
228
2 16 17 17 18 130
0 2
129
2
129
2 AC
1 0 1
AD 1
228
1
228
1
0
228
S 16 14 18 1
129
1
129
1 AD

VC 46
0 1 0
AE 0 0 15 13 13 14 0 0 AE

C
0 1 0

O
228 228 129 129 129

V C 46
3 1 3
AF 3 3 15 12 12 9 3 3 AF

C
3 1 3

O
227 227 227 128 128
2 0 2
AG 2
227
2
227
2 5 5 11 11 9 129
0 2
128
2
128
2 AG
1 0 1
AH 1
227
1
227
1 0
227
4 4 10 10 8 7 1
128
1
128
1 AH

VC 4 6
0 1 0
AJ 0 0 1 2 3 3 6 8 7 0 0 AJ

C
0 1 0

O
227 227 128 128 128

VC 46
3 1 3
AK 3 3 1 2 6 S 3 3 AK

C
3 1 3

O
226 226 226 127 127
VC 66

VC 65

2 0 2
AL 2 2 24 23 22 23 24 24 23 22 21 24 24 24 24 23 S 24 2 2 AL
C

2 0 2
O

226 226 128 127 127


VC 67

VC 84

V C 45
1 0 1
AM 1 1 24 23 21 22 23 24 24 23 22 21 22 23 22 22 23 23 24 1 1 AM
C

C
1 0 1
O

O
226 226 226 127 127
VC 66

VC 44
0 1 0
AN 0 0 21 21 21 19 19 20 19 19 20 21 22 23 20 21 23 22 22 21 0 0 AN
C

C
0 1 0
O

226 226 O 127 127 127


VC 6 6

VC 6 5

3 1 3
AP 3 3 22 20 20 S 17 20 18 S 20 21 19 19 20 21 20 19 20 21 3 3 AP
C

3 1 3
O

225 225 225 126 126


VC 67

VC 84

VC 45
2 0 2
AR 2 2 22 19 19 16 17 18 S 16 17 16 S 17 18 20 19 S 20 2 2 AR
C

C
2 0 2
O

O
225 225 127 126 126
VC 84

VC 44

1 0 1
AT 1 1 S S 17 16 15 13 14 16 17 18 16 17 18 18 18 S 19 19 1 1 AT
C

1 0 1
O

225 225 225 126 126


VC 66

VC 65

0 1 0
AU 0 0 15 16 17 18 15 13 14 S 15 18 S 15 15 16 17 17 15 S 0 0 AU
C

0 1 0
O

225 225 126 126 126


V C 67

VC 65

3 1 0 3
AV 3 3 15 16 18 S 11 12 10 15 13 14 13 14 14 16 14 15 18 17 AV
C

3 1 0 3
O

224 224 224 126 125


V C 84

V C 44

2 0 2
AW 13 13 14 14 11 12 9 10 13 14 10 13 12 13 13 14 18 17 16 16 3 3 AW
C

2 0 2
O

224 224 125 125


VC 66

VC 44

1
AY 8 8 12 9 9 7 8 9 11 12 10 11 11 12 11 12 12 15 14 14 AY
C

1
O

125
VC 67

VC 6 5

VC 45

1 0 1
BA G 10 12 12 7 12 11 11 7 8 7 11 12 10 7 9 9 9 11 10 15 13 12 BA
V

1 0 1
O

224 125 125


V C 67

VC 94

VC 45

BB 2 2 10 11 8 8 7 10 10 S 5 6 7 8 9 10 7 8 8 9 8 8 10 13 12 11 10 6 2 2 BB
C

C
O

224 125
VC 68

V C 94

V C 44

VC 45
0 0
BC 9 9 11 7 7 6 6 5 6 4 8 9 S 3 6 6 S 6 7 7 S 7 11 10 6 5 BC
C

C
0 0
O

224 O 125
VC 68

VC 66

VC 65

VC 45

BD 1 1 6 6 S 4 5 5 3 3 4 6 5 2 3 4 3 6 4 4 5 7 8 9 5 4 1 1 BD
C

C
O

224 125
VC 67

VC 94

VC 45

BE 1 2 4 4 5 4 2 3 1 3 6 5 4 2 5 4 2 3 3 2 2 5 8 9 3 2 4 V G BE
C

C
O

O
VC 68

VC 94

VC 44

BF 0 0 1 2 3 3 5 1 1 2 1 2 2 S 4 1 1 5 2 1 1 3 1 1 S 3 2 1 1 0 0 BF
C

C
O

224 125

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Bank 44 Bank 67 Quad 126 Quad 224 Quad 232 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 68 Quad 127 Quad 225 Quad 233
Bank 46 Bank 70 Quad 128 Quad 226 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 50 Bank 71 Quad 129 Quad 227 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#
V

Bank 51 Bank 72 Quad 130 Quad 228 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 52 Bank 84 Quad 131 Quad 229 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 65 Bank 94 Quad 132 Quad 230 # IO_L#N_GC #


MGTREFCLK#P

Bank 66 Quad 125 Quad 133 Quad 231 VRP # MGTREFCLK#N

ug575_c3_61_100815

Figure 3-61: FLVB2104 Package—XCVU125 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


264
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-62

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
A E E A
B V E B
C E V C
D V V D
E V E E
F V V V F
G V E G
H V V H
J V E J
K V V K
L V E E L
M V E V M
N V E E N
P V E V P
V
R V 12 E R
T V E V T
V
U V 11 E U
V V 10 E V V
W V E 1 V W
V
Y V 9 V Y
AA E 15 V AA
V
AB V V AB
V
AC V 6 19 V AC
AD V 13 E V AD
V
AE V 14 17 18 V AE
AF V E V AF
AG V E 16 0 20 24 21 E AG
V
AH V 5 22 23 V AH
AJ V E 3 8 7 V AJ
V
AK V 2 V AK
AL V E 4 29 30 28 E AL
AM V 29 29 33 E V AM
AN V E 29 34 29 V AN
AP E 29 29 29 E V AP
AR V E 26 35 29 29 E AR
AT V 26 29 29 E V AT
AU V E 27 26 26 V AU
AV E 26 26 26 V AV
AW E 26 26 26 E AW
AY 26 26 26 26 E AY
BA 25 26 26 V V BA
BB 25 25 25 BB
BC V 25 25 35 V BC
BD V 25 25 25 V BD
BE V 25 25 31 25 V BE
BF 25 32 36 37 BF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_62_100815

Figure 3-62: FLVB2104 Package—XCVU125 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


265
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLGB2104 (XCVU160 and XCVU190)


X-Ref Target - Figure 3-63

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

VC 70

VC 72

VC 51
3
A 3 3 21 21 22 24 S 23 24 22 22 23 24 22 22 23 24 22 22 19 17 15 15 10 9 3 3 A

C
3

O
233 233 133

VC 70

VC 7 2

VC 5 1
1
B 20 22 23 24 23 24 21 19 23 24 21 19 23 24 S 23 19 17 16 16 10 9 G B

V
C

C
1

O
233

VC 71

VC 52

V C 51
2
C G 19 20 23 S 22 19 21 19 20 20 21 19 S 20 24 23 21 20 13 13 12 12 C

V
2 2 2 2

C
2

O
233 233 133

VC 71

V C 52

VC 51
1 0 3
D 1 1 19 S 17 18 22 19 20 20 17 17 18 S 18 20 21 24 21 20 18 14 11 8 7 D

C
1 0 3

O
233 233 233 133

VC 70

VC 72

VC 51
0
E 0 0 15 17 18 16 16 17 17 16 16 18 S 17 18 21 S 23 24 18 14 S 11 8 7 1 1 E

C
0

O
233 233 133

VC 71

VC 50
3 1 2
F 3 3 15 13 14 18 18 15 15 15 14 14 S 17 16 16 19 23 24 6 6 2 S F

C
3 1 2

O
232 232 232 133

VC 71

VC 52

VC 51
2
G 2 2 13 14 16 16 14 14 S 15 13 13 14 14 15 19 20 21 5 4 2 0 0 G

C
2

O
232 232 133

V C 70

VC 72

VC 5 1
1 0 1
H 1 1 9 11 10 10 13 13 10 S 11 12 13 11 11 15 20 21 22 5 4 1 1 H

C
1 0 1

O
232 232 232 133

V C 72

V C 50
0 0
J 0 0 9 11 12 12 11 12 12 10 11 12 10 13 12 12 16 17 22 3 3 3 3 J

C
0 0

O
232 232 132 133

VC 71

V C 52
3 1 1 3
K 3 3 7 8 8 7 11 9 S 8 9 10 10 10 8 16 17 14 18 S K

C
3 1 1 3

O
231 231 231 133 132

VC 70

VC 52
2 0 2
L 2 2 7 5 S 7 8 8 9 8 9 7 7 9 8 7 15 14 18 10 2 2 L

C
2 0 2

O
231 231 133 132 132

VC 70

VC 72

VC 50
1 0 1
M 1 1 5 6 1 3 3 6 2 5 5 S 9 7 15 13 13 10 1 1 M

C
1 0 1

O
231 231 231 132 132

VC 71

V C 50
0 1 0
N 0 0 1 2 6 1 2 4 6 2 3 4 6 5 4 11 12 12 9 0 0 N

C
0 1 0

O
231 231 132 132 132

VC 71

VC 52
3 1 3
P 3 3 1 2 3 4 2 4 5 1 3 4 6 6 5 4 7 11 S 9 3 3 P

C
3 1 3

O
230 230 230 131 131

VC 70

V C 72

VC 50
2 0 2
R 2 2 3 4 5 1 6 3 2 1 7 8 8 2 2 2 R

C
2 0 2

O
230 230 132 131 131

VC 50
1 0 1
T 1 1 3 2 1 6 3 2 1 1 1 T

C
1 0 1

O
230 230 230 131 131
0 1 0
U 0
230
0
230
0 6 5 3 1 131
1 0
131
0
131
0 U
3 1 3
V 3
229
3
229
3
1
229
5 4 4 3
130
3
130
3 V

V C 46
2 0 2
W 2 2 21 22 24 24 2 2 W

C
2 0 2

O
229 229 131 130 130
1 0 1
Y 1
229
1
229
1 0
229
21 22 23 23 1
130
1
130
1 Y
0 1 0
AA 0
229
0
229
0 19 19 20 130
1 0
130
0
130
0 AA

VC 46
3 1 3
AB 3 3 S 20 3 3 AB

C
3 1 3

O
228 228 228 129 129
2 0 2
AC 2
228
2
228
2 16 17 17 18 130
0
2
129
2
129
2 AC
1 0 1
AD 1
228
1
228
1
0
228
S 16 14 18 1
129
1
129
1 AD

VC 46
0 1 0
AE 0 0 15 13 13 14 0 0 AE

C
0 1 0

O
228 228 129 129 129

VC 46
3 1 3
AF 3 3 15 12 12 9 3 3 AF

C
3 1 3

O
227 227 227 128 128
2 0 2
AG 2
227
2
227
2 5 5 11 11 9 129
0 2
128
2
128
2 AG
1 0 1
AH 1
227
1
227
1 0
227
4 4 10 10 8 7 1
128
1
128
1 AH

VC 46
0 1 0
AJ 0 0 1 2 3 3 6 8 7 0 0 AJ

C
0 1 0

O
227 227 128 128 128

VC 46
3 1 3
AK 3 3 1 2 6 S 3 3 AK

C
3 1 3

O
226 226 226 127 127
V C 66

V C 65

2 0 2
AL 2 2 24 23 22 23 24 24 23 22 21 24 24 24 24 23 S 24 2 2 AL
C

2 0 2
O

226 226 128 127 127


VC 67

VC 84

VC 45
1 0 1
AM 1 1 24 23 21 22 23 24 24 23 22 21 22 23 22 22 23 23 24 1 1 AM
C

C
1 0 1
O

O
226 226 226 127 127
VC 66

VC 44
0 1 0
AN 0 0 21 21 21 19 19 20 19 19 20 21 22 23 20 21 23 22 22 21 0 0 AN
C

C
0 1 0
O

O
226 226 127 127 127
VC 66

VC 65

3 1 3
AP 3 3 22 20 20 S 17 20 18 S 20 21 19 19 20 21 20 19 20 21 3 3 AP
C

3 1 3
O

225 225 225 126 126


VC 67

V C 84

VC 4 5
2 0 2
AR 2 2 22 19 19 16 17 18 S 16 17 16 S 17 18 20 19 S 20 2 2 AR
C

C
2 0 2
O

O
225 225 127 126 126
VC 84

V C 44

1 0 1
AT 1 1 S S 17 16 15 13 14 16 17 18 16 17 18 18 18 S 19 19 1 1 AT
C

1 0 1
O

225 225 225 126 126


VC 66

V C 65

0 1 0
AU 0 0 15 16 17 18 15 13 14 S 15 18 S 15 15 16 17 17 15 S 0 0 AU
C

0 1 0
O

225 225 126 126 126


VC 67

VC 65

3 1 0 3
AV 3 3 15 16 18 S 11 12 10 15 13 14 13 14 14 16 14 15 18 17 AV
C

3 1 0 3
O

224 224 224 126 125


V C 84

VC 44

2 0 2
AW 13 13 14 14 11 12 9 10 13 14 10 13 12 13 13 14 18 17 16 16 3 3 AW
C

2 0 2
O

224 224 125 125


VC 66

VC 44

1
AY 8 8 12 9 9 7 8 9 11 12 10 11 11 12 11 12 12 15 14 14 AY
C

1
O

125
VC 67

VC 65

VC 45

1 0 1
BA G 10 12 12 7 12 11 11 7 8 7 11 12 10 7 9 9 9 11 10 15 13 12 BA
V

1 0 1
O

224 125 125


V C 67

VC 9 4

VC 45

BB 2 2 10 11 8 8 7 10 10 S 5 6 7 8 9 10 7 8 8 9 8 8 10 13 12 11 10 6 2 2 BB
C

C
O

224 125
VC 68

V C 94

V C 44

VC 45
0 0
BC 9 9 11 7 7 6 6 5 6 4 8 9 S 3 6 6 S 6 7 7 S 7 11 10 6 5 BC
C

C
0 0
O

O
224 125
VC 68

VC 66

VC 65

VC 45

BD 1 1 6 6 S 4 5 5 3 3 4 6 5 2 3 4 3 6 4 4 5 7 8 9 5 4 1 1 BD
C

C
O

224 125
VC 67

VC 94

VC 45

BE 1 2 4 4 5 4 2 3 1 3 6 5 4 2 5 4 2 3 3 2 2 5 8 9 3 2 4 V G BE
C

C
O

O
VC 68

VC 94

V C 44

BF 0 0 1 2 3 3 5 1 1 2 1 2 2 S 4 1 1 5 2 1 1 3 1 1 S 3 2 1 1 0 0 BF
C

C
O

224 125

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Bank 44 Bank 67 Quad 126 Quad 224 Quad 232 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 45 Bank 68 Quad 127 Quad 225 Quad 233
Bank 46 Bank 70 Quad 128 Quad 226 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 50 Bank 71 Quad 129 Quad 227 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#
V

Bank 51 Bank 72 Quad 130 Quad 228 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 52 Bank 84 Quad 131 Quad 229 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 65 Bank 94 Quad 132 Quad 230 # IO_L#N_GC #


MGTREFCLK#P

Bank 66 Quad 125 Quad 133 Quad 231 VRP # MGTREFCLK#N

ug575_c3_63_100815

Figure 3-63: FLGB2104 Package—XCVU160 and XCVU190 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


266
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-64

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
A E E A
B V E B
C E V C
D V V D
E V E E
F V V V F
G V E G
H V V H
J V E J
K V V K
L V E E L
M V E V M
N V E E N
P V E V P
V
R V 12 E R
T V E V T
V
U V 11 E U
V V 10 E V V
W V E 1 V W
V
Y V 9 V Y
AA E 15 V AA
V
AB V V AB
V
AC V 6 19 V AC
AD V 13 E V AD
V
AE V 14 17 18 V AE
AF V E V AF
AG V E 16 0 20 24 21 E AG
V
AH V 5 22 23 V AH
AJ V E 3 8 7 V AJ
V
AK V 2 V AK
AL V E 4 29 30 28 E AL
AM V 29 29 33 E V AM
AN V E 29 34 29 V AN
AP E 29 29 29 E V AP
AR V E 26 35 29 29 E AR
AT V 26 29 29 E V AT
AU V E 27 26 26 V AU
AV E 26 26 26 V AV
AW E 26 26 26 E AW
AY 26 26 26 26 E AY
BA 25 26 26 V V BA
BB 25 25 25 BB
BC V 25 25 35 V BC
BD V 25 25 25 V BD
BE V 25 25 31 25 V BE
BF 25 32 36 37 BF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_64_100815

Figure 3-64: FLGB2104 Package—XCVU160 and XCVU190 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


267
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FFVC2104 (XCVU095)
X-Ref Target - Figure 3-65

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

V C 69
A 24 23 23 21 20 20 23 24 20 20 A

C
O
VC 70
B 24 19 21 24 22 23 24 22 22 B

C
O
V C 71
C 22 22 19 24 22 19 21 21 21 23 C

C
O
VC 71

VC 69
D 20 20 S S 19 21 19 19 23 G D

V
C

C
O

O
VC 70
3 3
E 18 18 S S 16 17 S 18 18 17 E

C
3 3

O
231 131

V C 70
1 1
F 1 1 3 3 15 15 17 18 16 17 15 16 15 17 3 3 1 1 F

C
1 1

O
231 231 231 131 131 131

VC 71

VC 69
0 2 2 0
G 0 0 2 2 16 17 18 13 14 15 16 S 15 2 2 0 0 G

C
0 2 2 0

O
231 231 231 231 131 131 131 131

VC 69
3 3
H 3 3 16 14 14 13 14 12 9 14 13 13 3 3 H

C
3 3

O
230 230 130 130

VC 70
2 2
J 2 2 S 10 7 13 13 10 11 12 9 10 14 12 5 3 2 2 J

C
2 2

O
230 230 130 130

VC 71

VC 69
1 1
K 1 1 10 7 12 12 10 11 8 7 10 11 11 12 5 3 1 1 K

C
1 1

O
230 230 130 130

V C 71

VC 69
0 0
L 0 0 8 8 11 11 9 6 8 7 S S 9 9 6 1 0 0 L

C
0 0

O
230 230 130 130

V C 70
3 1 1 3
M 3 3 4 4 2 1 9 6 4 1 3 3 8 7 6 1 2 3 3 M

C
3 1 1 3

O
229 229 231 131 129 129

VC 70

VC 6 9
2 0 0 2
N 2 2 2 1 3 5 4 1 2 5 8 7 4 4 2 2 2 N

C
2 0 0 2

O
229 229 231 131 129 129

V C 71
1 1 1 1
P 1 1 6 6 3 5 2 5 1 1 P

C
1 1 1 1

O
229 229 230 130 129 129
0 0 0 0
R 0
229
0
229
0 0
230 130
0 0
129
0
129
0 R
3 1 1 3
T 3
228
3
228
3 1
229 129
1 3
128
3
128
3 T
2 0 0 2
U 2
228
2
228
2 0
229 129
0 2
128
2
128
2 U
1 1 1 1
V 1
228
1
228
1 1
228 128
1 1
128
1
128
1 V
0 0 0 0
W 0
228
0
228
0 0
228 128
0 0
128
0
128
0 W
3 1 1 3
Y 3
227
3
227
3 1
227 127
1 3
127
3
127
3 Y
2 0 0 2
AA 2
227
2
227
2 0
227 127
0 2
127
2
127
2 AA
1 1 1 1
AB 1
227
1
227
1 1
226 126
1 1
127
1
127
1 AB
0 0 0 0
AC 0
227
0
227
0
0
226 126
0
0
127
0
127
0 AC
3 1 1 3
AD 3
226
3
226
3
1
225 125
1
3
126
3
126
3 AD
2 0 0 2
AE 2
226
2
226
2 0
225 125
0 2
126
2
126
2 AE
1 1 1 1
AF 1
226
1
226
1 1
224 124
1 1
126
1
126
1 AF
0 0 0 0
AG 0
226
0
226
0 0
224 124
0 0
126
0
126
0 AG
3 3
AH G AH
V

3 3 3 3 3 3
225 225 125 125
2 2
AJ 2
225
2
225
2 2
125
2
125
2 AJ
1 1
AK 1
225
1
225
1 1
125
1
125
1 AK
0 0
AL 0
225
0
225
0 0
125
0
125
0 AL
VC 65

VC 67
3 3
AM 3 3 S 3 4 1 5 2 3 2 3 3 AM
C

C
3 3
O

O
224 224 124 124
VC 84

VC 66

2 2
AN 2 2 23 21 1 3 2 4 1 5 4 2 1 3 6 2 1 2 2 AN
C

2 2
O

224 224 124 124


VC 84

VC 66

VC 68
1 1
AP 1 1 18 23 21 24 1 2 3 3 4 6 6 1 6 1 5 1 1 AP
C

C
1 1
O

O
224 224 124 124
VC 84

VC 65

VC 67

0 0
AR 0 0 15 18 16 16 24 5 5 6 7 7 8 8 5 5 4 4 3 5 2 4 6 0 0 AR
C

0 0
O

224 224 124 124


V C 65

VC 67

AT S 15 14 14 19 20 7 6 8 9 12 12 10 8 9 10 10 3 2 4 6 AT
C

C
O

O
VC 84

V C 66

VC 68
AU 17 17 13 13 19 20 9 7 8 9 11 11 10 8 11 9 8 8 12 12 AU
C

C
O

O
VC 94

VC 66

VC 68

AV 7 11 11 22 22 9 S 12 10 13 13 S 7 11 12 12 7 11 11 9 10 AV
C

C
O

O
VC 65

VC 67

AW 7 12 12 2 11 11 12 10 14 14 S 7 14 14 S 7 S 14 9 10 AW
C

C
O

O
VC 94

VC 67

VC 68

AY 9 S 2 1 6 13 13 14 15 15 16 18 13 13 15 15 15 14 13 13 AY
C

C
O

O
V C 94

V C 66

VC 68

BA 10 9 5 1 3 6 17 14 16 17 16 18 17 16 18 S 21 15 16 S 18 BA
C

C
O

O
VC 65

VC 68

BB 10 8 8 5 3 4 4 15 17 16 17 19 21 17 16 S 18 21 17 17 16 18 BB
C

C
O

O
V C 94

VC 67

BC S 15 18 18 S 19 21 19 21 24 19 19 23 BC
C

C
O

O
V C 66

BD 19 19 21 S S 20 23 19 21 S 24 20 23 BD
C
O
VC 66

VC 68

BE 23 20 21 22 24 20 23 24 23 22 22 22 20 BE
C

C
O

O
V C 65

V C 67

BF 23 20 22 24 22 22 24 23 20 20 22 24 24 BF
C

C
O

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Bank 65 Bank 94 Quad 131 Quad 231 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 66 Quad 124 Quad 224
Bank 67 Quad 125 Quad 225 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 68 Quad 126 Quad 226 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#


V

Bank 69 Quad 127 Quad 227 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 70 Quad 128 Quad 228 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 71 Quad 129 Quad 229 # IO_L#N_GC #


MGTREFCLK#P

Bank 84 Quad 130 Quad 230 VRP # MGTREFCLK#N

ug575_c3_65_100815

Figure 3-65: FFVC2104 Package—XCVU095 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


268
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-66

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
A V n n n n n n n n n n n n n n n n V A
B n n V n n V n n n n V n n V n n B
C n n n n V n n n n n n n n V n n n n C
D n n n n n n V n n n n V n n n n D
E n n n n V n n n n V n n n n E
F V E E V F
G V E E V G
H V E n n n n E V H
V V
J V n n n n V J
K V E n n 15 n n E V K
V V
L V n n n n V L
M V E 1 E V M
N V E E V N
P V E 9 E V P
R V E E V R
T V E 12 E V T
U V E E V U
V V E 11 E V V
W E E E E W
V V
Y V 10 V Y
AA V E E V AA
V V
AB V 13 20 0 V AB
AC V E 6 24 21 E V AC
AD V E 19 17 22 23 E V AD
AE V E 14 8 7 E V AE
AF V E 16 18 4 E V AF
AG V E E V AG
AH E n n 5 n n E n n AH
AJ V n n E E n n V AJ
V V
AK V n n 3 n n V AK
AL E n n E E n n E AL
V V
AM V n n 2 25 25 n n V AM
AN V n n 36 25 31 25 n n V AN
AP V 37 32 25 V AP
AR V 25 25 25 V AR
AT n n V n n 25 25 25 n n V n n AT
AU n n n n V 26 25 25 V n n n n AU
AV n n V n n 26 35 26 26 n n V n n AV
AW n n n n V 26 26 26 26 V n n n n AW
AY n n V n n 26 26 26 n n V n n AY
BA n n n n V 29 26 26 V n n n n BA
BB n n V n n 26 29 26 n n V n n BB
BC n n n n V 26 29 29 27 V n n n n BC
BD n n V n n n n n n 29 29 29 35 n n n n n n V n n BD
BE n n V n n 33 29 29 29 30 n n V n n BE
BF n n V n n V n n 34 29 29 28 n n V n n V n n BF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_66_100815

Figure 3-66: FFVC2104 Package—XCVU095 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


269
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLVC2104 (XCVU125)
X-Ref Target - Figure 3-67

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

V C 70
3 3
A 3 3 3 3 24 23 23 21 20 20 23 24 20 20 3 3 3 3 A

C
3 3

O
232 233 233 133 133 132

VC 71
3 2 2 3
B 2 2 24 19 21 24 22 23 24 22 22 2 2 B

C
3 2 2 3

O
232 233 233 133 133 132

V C 72
2 1 1 2
C 2 2 1 1 22 22 19 24 22 19 21 21 21 23 1 1 2 2 C

C
2 1 1 2

O
232 232 233 233 133 133 132 132

V C 72

VC 70
1 0 0 1
D G 20 20 S S 19 21 19 19 23 G D

V
0 0 0 0

C
1 0 0 1

O
232 233 233 133 133 132

VC 71
0 3 3 0
E 0 0 1 1 18 18 S S 16 17 S 18 18 17 1 1 0 0 E

C
0 3 3 0

O
232 232 232 231 131 132 132 132

V C 71
1 1
F 1 1 3 3 15 15 17 18 16 17 15 16 15 17 3 3 1 1 F

C
1 1

O
231 231 231 131 131 131

VC 72

VC 70
0 2 2 0
G 0 0 2 2 16 17 18 13 14 15 16 S 15 2 2 0 0 G

C
0 2 2 0

O
231 231 231 231 131 131 131 131

V C 70
3 1 1 3
H 3 3 16 14 14 13 14 12 9 14 13 13 3 3 H

C
3 1 1 3

O
230 230 233 133 130 130

VC 71
2 0 0 2
J 2 2 S 10 7 13 13 10 11 12 9 10 14 12 5 3 2 2 J

C
2 0 0 2

O
230 230 233 133 130 130

V C 72

V C 70
1 1 1 1
K 1 1 10 7 12 12 10 11 8 7 10 11 11 12 5 3 1 1 K

C
1 1 1 1

O
230 230 232 132 130 130

V C 72

VC 70
0 0 0 0
L 0 0 8 8 11 11 9 6 8 7 S S 9 9 6 1 0 0 L

C
0 0 0 0

O
230 230 232 132 130 130

VC 71
3 1 1 3
M 3 3 4 4 2 1 9 6 4 1 3 3 8 7 6 1 2 3 3 M

C
3 1 1 3

O
229 229 231 131 129 129

VC 71

VC 70
2 0 0 2
N 2 2 2 1 3 5 4 1 2 5 8 7 4 4 2 2 2 N

C
2 0 0 2

O
229 229 231 131 129 129

V C 72
1 1 1 1
P 1 1 6 6 3 5 2 5 1 1 P

C
1 1 1 1

O
229 229 230 130 129 129
0 0 0 0
R 0
229
0
229
0 0
230 130
0 0
129
0
129
0 R
3 1 1 3
T 3
228
3
228
3 1
229 129
1 3
128
3
128
3 T
2 0 0 2
U 2
228
2
228
2 0
229 129
0 2
128
2
128
2 U
1 1 1 1
V 1
228
1
228
1 1
228 128
1 1
128
1
128
1 V
0 0 0 0
W 0
228
0
228
0
0
228 128
0
0
128
0
128
0 W
3 1 1 3
Y 3
227
3
227
3 1
227 127
1 3
127
3
127
3 Y
2 0 0 2
AA 2
227
2
227
2 0
227 127
0 2
127
2
127
2 AA
1 1 1 1
AB 1
227
1
227
1 1
226 126
1 1
127
1
127
1 AB
0 0 0 0
AC 0
227
0
227
0 0
226 126
0 0
127
0
127
0 AC
3 1 1 3
AD 3
226
3
226
3
1
225 125
1
3
126
3
126
3 AD
2 0 0 2
AE 2
226
2
226
2 0
225 125
0 2
126
2
126
2 AE
1 1 1 1
AF 1
226
1
226
1 1
224 124
1 1
126
1
126
1 AF
0 0 0 0
AG 0
226
0
226
0 0
224 124
0 0
126
0
126
0 AG
3 3
AH G G AH
V

V
3 3 3 3
3 3
225 225 125 125
2 2
AJ 2
225
2
225
2 2
125
2
125
2 AJ
1 1
AK 1
225
1
225
1 1
125
1
125
1 AK
0 0
AL 0
225
0
225
0 0
125
0
125
0 AL
VC 65

VC 67
3 3
AM 3 3 S 3 4 1 5 2 3 2 3 3 AM
C

C
3 3
O

O
224 224 124 124
V C 84

VC 66

2 2
AN 2 2 23 21 1 3 2 4 1 5 4 2 1 3 6 2 1 2 2 AN
C

2 2
O

224 224 124 124


V C 84

VC 66

VC 68
1 1
AP 1 1 18 23 21 24 1 2 3 3 4 6 6 1 6 1 5 1 1 AP
C

C
1 1
O

O
224 224 124 124
VC 84

VC 65

V C 67
0 0
AR 0 0 15 18 16 16 24 5 5 6 7 7 8 8 5 5 4 4 3 5 2 4 6 0 0 AR
C

C
0 0
O

O
224 224 124 124
V C 65

VC 67

AT S 15 14 14 19 20 7 6 8 9 12 12 10 8 9 10 10 3 2 4 6 AT
C

C
O

O
VC 84

VC 66

VC 68
AU 17 17 13 13 19 20 9 7 8 9 11 11 10 8 11 9 8 8 12 12 AU
C

C
O

O
VC 94

VC 6 6

VC 68

AV 7 11 11 22 22 9 S 12 10 13 13 S 7 11 12 12 7 11 11 9 10 AV
C

C
O

O
VC 65

VC 67

AW 7 12 12 2 11 11 12 10 14 14 S 7 14 14 S 7 S 14 9 10 AW
C

C
O

O
V C 94

VC 67

VC 68
AY 9 S 2 1 6 13 13 14 15 15 16 18 13 13 15 15 15 14 13 13 AY
C

C
O

O
VC 94

VC 66

VC 68

BA 10 9 5 1 3 6 17 14 16 17 16 18 17 16 18 S 21 15 16 S 18 BA
C

C
O

O
VC 65

VC 68

BB 10 8 8 5 3 4 4 15 17 16 17 19 21 17 16 S 18 21 17 17 16 18 BB
C

C
O

O
VC 94

V C 67

BC S 15 18 18 S 19 21 19 21 24 19 19 23 BC
C

C
O

O
VC 66

BD 19 19 21 S S 20 23 19 21 S 24 20 23 BD
C
O
VC 66

VC 68

BE 23 20 21 22 24 20 23 24 23 22 22 22 20 BE
C

C
O

O
V C 65

VC 67

BF 23 20 22 24 22 22 24 23 20 20 22 24 24 BF
C

C
O

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Bank 65 Bank 94 Quad 131 Quad 229 SelectIO Pins Dedicated Pins Transceiver Pins
Bank 66 Quad 124 Quad 132 Quad 230
Bank 67 Quad 125 Quad 133 Quad 231 # IO_L#P VREF #
MGT[H or Y]RXP#

Bank 68 Quad 126 Quad 224 Quad 232 # IO_L#N MGTAVTTRCAL MGT[H or Y]RXN#
V

Bank 70 Quad 127 Quad 225 Quad 233 S IO (single−ended) G MGTRREF # MGT[H or Y]TXP#

Bank 71 Quad 128 Quad 226 # IO_L#P_GC # MGT[H or Y]TXN#

Bank 72 Quad 129 Quad 227 # IO_L#N_GC #


MGTREFCLK#P

Bank 84 Quad 130 Quad 228 VRP # MGTREFCLK#N

ug575_c3_67_100815

Figure 3-67: FLVC2104 Package—XCVU125 I/O Bank Diagram

UltraScale Device Packaging and Pinouts Send Feedback


270
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

X-Ref Target - Figure 3-68

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
A V n n n n V A
B V V V V B
C V V C
D V V D
E V V E
F V E E V F
G V E E V G
H V E E V H
V V
J V V J
K V E 15 E V K
V V
L V V L
M V E 1 E V M
N V E E V N
P V E 9 E V P
R V E E V R
T V E 12 E V T
U V E E V U
V V E 11 E V V
W E E E E W
V V
Y V 10 V Y
AA V E E V AA
V V
AB V 13 20 0 V AB
AC V E 6 24 21 E V AC
AD V E 19 17 22 23 E V AD
AE V E 14 8 7 E V AE
AF V E 16 18 4 E V AF
AG V E E V AG
AH E n n 5 n n E AH
AJ V n n E E n n V AJ
V V
AK V n n 3 n n V AK
AL E n n E E n n E AL
V V
AM V n n 2 25 25 n n V AM
AN V n n 36 25 31 25 n n V AN
AP V 37 32 25 V AP
AR V 25 25 25 V AR
AT n n V n n 25 25 25 n n V n n AT
AU n n n n V 26 25 25 V n n n n AU
AV n n V n n 26 35 26 26 n n V n n AV
AW n n n n V 26 26 26 26 V n n n n AW
AY n n V n n 26 26 26 n n V n n AY
BA n n n n V 29 26 26 V n n n n BA
BB n n V n n 26 29 26 n n V n n BB
BC n n n n V 26 29 29 27 V n n n n BC
BD n n V n n n n n n 29 29 29 35 n n n n n n V n n BD
BE n n V n n 33 29 29 29 30 n n V n n BE
BF n n V n n V n n 34 29 29 28 n n V n n V n n BF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Power Pins Dedicated Pins Multi−Function I/O Pins

GND 0 CCLK_0 15 PUDC_B_0 25 A[16 to 28]


VBATT 1 CFGBVS_0 16 RDWR_FCS_B_0 26 A[00 to 15]_D[16 to 31]
VCCAUX_IO 2 D00_MOSI_0 17 TCK_0 27 CSI_ADV_B
VCCAUX 3 D01_DIN_0 18 TDI_0 28 DOUT_CSO_B
VCCINT 4 D02_0 19 TDO_0 29 D[04 to 15]
VCCINT_IO 5 D03_0 20 TMS_0 30 EMCCLK
VCCO_[bank number] 6 DONE_0 21 VP 31 FOE_B
VCCBRAM 7 DXP 22 VN 32 FWE_FCS2_B
VCCADC 8 DXN 23 VREFP 33 I2C_SCLK
GNDADC 9 INIT_B_0 24 VREFN 34 I2C_SDA
n NC 10 M0_0 35 PERSTN[0 to 1]
E MGTAVCC_[R or L] 11 M1_0 36 RS0
V MGTAVTT_[R or L] 12 M2_0 37 RS1
V
MGTVCCAUX_[R or L] 13 POR_OVERRIDE
14 PROGRAM_B_0

ug575_c3_68_100815

Figure 3-68: FLVC2104 Package—XCVU125 Configuration/Power Diagram

UltraScale Device Packaging and Pinouts Send Feedback


271
UG575 (v1.19) May 10, 2023
Chapter 3: Device Diagrams

FLGC2104 (XCVU160 and XCVU190)


X-Ref Target - Figure 3-69

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

VC 70
3 3
A 3 3 3 3 24 23 23 21 20 20 23 24 20 20 3 3 3 3 A

C
3 3

O
232 233 233 133 133 132

VC 71
3 2 2 3
B 2 2 24 19 21 24 22 23 24 22 22 2 2 B

C
3 2 2 3

O
232 233 233 133 133 132

VC 72
2 1 1 2
C 2 2 1 1 22 22 19 24 22 19 21 21 21 23 1 1 2 2 C

C
2 1 1 2

O
232 232 233 233 133 133 132 132

VC 72

VC 70
1 0 0 1
D G 20 20 S S 19 21 19 19 23 G D

V
0 0 0 0

C
1 0 0 1

O
232 233 233 133 133 132

VC 71
0 3 3 0
E 0 0 1 1 18 18 S S 16 17 S 18 18 17 1 1 0 0 E

C
0 3 3 0

O
232 232 232 231 131 132 132 132

VC 71
1 1
F 1 1 3 3 15 15 17 18 16 17 15 16 15 17 3 3 1 1 F

C
1 1

O
231 231 231 131 131 131

V C 72

VC 70
0 2 2 0
G 0 0 2 2 16 17 18 13 14 15 16 S 15 2 2 0 0 G

C
0 2 2 0

O
231 231 231 231 131 131 131 131

V C 70
3 1 1 3
H 3 3 16 14 14 13 14 12 9 14 13 13 3 3 H

C
3 1 1 3

O
230 230 233 133 130 130

VC 71
2 0 0 2
J 2 2 S 10 7 13 13 10 11 12 9 10 14 12 5 3 2 2 J

C
2 0 0 2

O
230 230 233 133 130 130

V C 72

VC 70
1 1 1 1
K 1 1 10 7 12 12 10 11 8 7 10 11 11 12 5 3 1 1 K

C
1 1 1 1

O
230 230 232 132 130 130

VC 72

VC 70
0 0 0 0
L 0 0 8 8 11 11 9 6 8 7 S S 9 9 6 1 0 0 L

C
0 0 0 0

O
230 230 232 132 130 130

V C 71
3 1 1 3
M 3 3 4 4 2 1 9 6 4 1 3 3 8 7 6 1 2 3 3 M

C
3 1 1 3

O
229 229 231 131 129 129

VC 71

VC 70
2 0 0 2
N 2 2 2 1 3 5 4 1 2 5 8 7 4 4 2 2 2 N

C
2 0 0 2

O
229 229 231 131 129 129

VC 72
1 1 1 1
P 1 1 6 6 3 5 2 5 1 1 P

C
1 1 1 1

O
229 229 230 130 129 129
0 0 0 0
R 0
229
0
229
0 0
230 130
0 0
129
0
129
0 R
3 1 1 3
T 3
228
3
228
3 1
229 129
1 3
128
3
128
3 T
2 0 0 2
U 2
228
2
228
2 0
229 129
0 2
128
2
128
2 U
1 1 1 1
V 1
228
1
228
1
1
228 128
1
1
128
1
128
1 V
0 0 0 0
W 0
228
0
228
0 0
228 128
0 0
128
0
128
0 W
3 1 1 3
Y 3
227
3
227
3 1
227 127
1 3
127
3
127
3 Y
2 0 0 2
AA 2
227
2
227
2 0
227 127
0 2
127
2
127
2 AA
1 1 1 1
AB 1
227
1
227
1
1
226 126
1
1
127
1
127
1 AB
0 0 0 0
AC 0
227
0
227
0 0
226 126
0 0
127
0
127
0 AC
3 1 1 3
AD 3
226
3
226
3
1
225 125
1
3
126
3
126
3 AD
2 0 0 2
AE 2
226
2
226
2 0
225 125
0 2
126
2
126
2 AE
1 1 1 1
AF 1
226
1
226
1 1
224 124
1 1
126
1
126
1 AF
0 0 0 0
AG 0
226
0
226
0 0
224 124
0 0
126
0
126
0 AG
3 1 1 3
AH G G AH
V

V
3 3 3 1 1 3 3 3
225 225 222 122 125 125
2 0 0 2
AJ 2
225
2
225
2 0
222 122
0 2
125
2
125
2 AJ
1 1 1 1
AK 1
225
1
225
1 1
221 121
1 1
125
1
125
1 AK
0 0 0 0
AL 0
225
0
225
0 0
221 121
0 0
125
0
125
0 AL
V C 65

VC 67
3 1 1 3
AM 3 3 S 3 4 1 5 2 3 2 3 3 AM
C

C
3 1 1 3
O

O
224 224 220 120 124 124
VC 84

VC 6 6

2 0 0 2
AN 2 2 23 21 1 3 2 4 1 5 4 2 1 3 6 2 1 2 2 AN
C

2 0 0 2
O

224 224 220 120 124 124


V C 84

VC 66

VC 68
1 1
AP 1 1 18 23 21 24 1 2 3 3 4 6 6 1 6 1 5 1 1 AP
C

C
1 1
O

O
224 224 124 124
VC 84

VC 65

V C 67

0 0
AR 0 0 15 18 16 16 24 5 5 6 7 7 8 8 5 5 4 4 3 5 2 4 6 0 0 AR
C

0 0
O

224 224 124 124


VC 65

VC 67

3 3
AT 3 3 S 15 14 14 19 20 7 6 8 9 12 12 10 8 9 10 10 3 2 4 6 3 3 AT
C

3 3
O

222 222 122 122


VC 84

VC 66

VC 68
2 2
AU 2 2 17 17 13 13 19 20 9 7 8 9 11 11 10 8 11 9 8 8 12 12 2 2 AU
C

C
2 2
O

O
222 222 122 122
VC 94

VC 66

VC 68

1 1
AV 1 1 7 11 11 22 22 9 S 12 10 13 13 S 7 11 12 12 7 11 11 9 10 1 1 AV
C

1 1
O

222 222 122 122


V C 65

V C 67

0 0
AW 0 0 7 12 12 2 11 11 12 10 14 14 S 7 14 14 S 7 S 14 9 10 0 0 AW
C

0 0

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