Lab DCT Assignment

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EEE 491 Lab Assignment

Lab-DCT: Discrete Cosine Transform


1. Technical Specifications
Lab-DCT shall read energy data of each filter bank from Lab-MEL’s dual-port RAM. Lab-DCT shall calculate discrete
cosine transform of the energy data and the results shall be stored in a simple dual-port RAM. The RAM size shall be
at least eight words. Lab-DCT output data width of the RAM shall be 16-bit. Use “Block Memory generator” and
“Multipliers” from the Vivado “IP Catalog”.

Lab-DCT in FPGA shall have the following input/output (IO) signals.


 “reset_in” input control signal, which resets all the registers in the design.
 “clock_in” input clock signal of the 100MHz clock oscillator on the Basys-3 board.
 “mel_addr_out” output signal that addresses the read-only port of the dual-port RAM in Lab-MEL.
 “mel_data_in” input signal from the read-only port of the dual-port RAM in Lab-MEL.
 “mem_addr_in” input signal that addresses the read-only port of the dual-port RAM in Lab-DCT.
 “mem_data_out” output signal of the read-only port of the dual-port RAM in Lab-DCT.
 “start_in” input control signal, which starts the DCT filtering function. This signal is active high asserted on a
single clock pulse (refer to waveform in Lab-ADC assignment).
 “ready_out” output status signal that indicates if DCT filtering function is completed and output data are
written to dual-port RAM of Lab-DCT and the function is ready for the next execution. This signal is active
high and asserted low just after the start signal is asserted (refer to waveform in Lab-ADC assignment).

After verifying your Lab-DCT design by using your test-bench simulation results, integrate Lab-DCT with the Lab-
PCB, ADC board, Lab-ADC, Lab-WINDOW, Lab-CTRL, Lab-FFT, Lab-MEL and Lab-DEBUG. Connect Lab-DEBUG to
Lab-DCT output. Control and observe the process sequence using start_in signal of Lab-CTRL and ready_out
signals of the components. On the Basys-3 board, use a button for start_in signaling and a LED for each
ready_out signals of the components.

2. Demonstration
 Present your test bench simulation results: inputs, outputs (waveforms). Test bench generates a number of test
data for band energies which may be stored in a ROM (filled with data in COE file), starts the Lab-DCT, and waits
for the ready signal and then it reads data from the dual-port RAM of Lab-DCT. Validate the DCT function by the
simulation output waveforms and by the results obtained on MATLAB.
 Configure your integrated design on Basys-3 board. Use start_in button and ready_out LEDs of the components
to observe/verify process sequence. If you need you may add more LEDs for further observations.
 Prepare the Lab-CTRL demonstration set up. Run the integrated system and transfer the DCT output data of each
frame to MATLAB. Compare and verify MEL filter results with the Lab-MATLAB results for sinus input
frequencies: 100Hz, 500Hz, 1KHz, 4KHz with 1.5V peak-to-peak amplitude for each frequency.

3. Guidance
 You can refer to https://link.springer.com/content/pdf/bbm:978-3-319-49220-9/1.pdf
 You can use the function given below for DCT. DCT(n) becomes cepstral coefficients where n is from 0 to N-1 and
N may typically be between 7 and 13. E(m) is the energy in the mel filter bank m. M is the total number of mel
filter banks.
( . )
DCT(n) = ∑ 𝐸(𝑚)𝑐𝑜𝑠( )
 DCT function can be implemented by using a ROM. Generate Cosine values for n and m variables on MATLAB,
include them in a ROM memory, and use them as the multiplication coefficient of the energy data. Represent
Cosine data in 16-bit.

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