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 Data

Instruction
decoder
Sign extend

Write Read

r15 Rd
Register file
pc r0 - r15 Result

Rn A Rm B

A B Acc

Barrel shifter MAC

N

ALU

Address register

Incrementer
Address
r2 : 0101 0011 1010 1111 1101 1010 0110 1011
r0 : 1010 1100 0101 0000 0010 0101 1001 0100
 2n

Register value
Before
X b31 b0
shift

Carry 32 - bit word

After
b31 b30 b0 0
LSL # 1
2n
Register value

b31 b0 X Before

32 - bit word Carry

After
0 b31 b1 b0
LSL # 1

Register value

b31 b0 X Before

Carry

After
b31 b31 b1 b0
ASR # 1
 Register value
b31 b0 X Before

Carry

b0 b31 b1 b0 After
ROR # 1

Register value
b31 b0 X Before

X b31 b1 b0 After
RRX

33 rd
Opcode Mnemonic Meaning Effect
[23:21]
000 MUL Multiply (32-bit result) Rd := (Rm * Rs) [31:0]
001 MLA Multiply-accumulate (32 -bit result) Rd := (Rm * Rs + Rn) [31:0]
100 UMULL Unsigned multiply long RdHi:RdLo := Rm * Rs
101 UMLAL Unsigned multiply -accumulate long RdHi:RdLo += Rm * Rs
110 SMULL Signed multiply long RdHi:RdLo := Rm * Rs
111 SMLAL Signed multiply-accumulate long RdHi:RdLo += Rm * Rs
 LDMIA r1, {r0, r2, r4}

r4 Memory
r3
r2 base_addr + 8
r1 base_addr base_addr + 4
r0 base_addr
31 28 27 25 24 23 0
cond 101 L 24-bit signed word offset
 func1 func1

: STMFD sp!,{regs,lr} :
: : :
BL func1 BL func2 :
: : :
: LDMFD sp!,{regs,pc} :
MOV pc,lr
 R0

R1

R2

R3 Low priority
registers
R4

R5
General
purpose R6
registers
R7

R8

R9
High priority
R10 registers
R11

R12

R13(SP)

R14(LR) PSP MSP

R15(PC)

PSR

PRIMASK Special register

CONTROL
User / Sys FIQ IRQ SVC Undef Abort Mon
r0
r1
r2
r3 User
mode
r4 r0 - r7
r5 User User User User User
r6 mode mode mode mode mode
r7 r0 - r12 r0 - r12 r0 - r12 r0 - r12 r0 - r12

r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (Ir) r14 (Ir) r14 (Ir) r14 (Ir) r14 (Ir) r14 (Ir) r14 (Ir)
r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc)

cpsr spsr spsr spsr spsr spsr spsr

Condition code flags (Reserved) Control bits

31 30 29 28 27 26 25 24 23 8 7 6 5 4 3 2 1 0

N Z C V . . . . . . . . I F T M4 M3 M2 M1 M0

Overflow
Carry borrow Mode bits
/ Extend State bit
Zero FIQ disable
Negative / less than IRQ disable
 "On" time, ton

Average
value

Period, T

100 % Pulse on time

Pulse period
 "On" time, ton

Average
value

Period, T

R
Vin Vout

C
 External IPA [31:0]
Instruction Instruction
coprocessor
cache MMU
interface

IMVA[31:0]

R13

ID[31:0]
IVA [31:0]

Trace ARM9TDMI AMBA ASB

iterface Processor core CP15 bus
port (integral embeddedlCE) interface

DVA[31:0]
DD[31:0] Write
buffer
R13
DMVA[31:0] DPA[31:0]

JTAG Data Data Write back

cache MMU PA TAG RAM WBPA[31:0]

DINDEX[5:0]
 Cortex-M3
Processor core system
Trace interface
Interrupt Controller

Register bank
Instruction
fetch unit

Decoder

system
Debug
(NVIC)

ALU Trace
Interrupts

Memory interface

Memory
Instruction bus protection Data bus
unit

Debug
Bus interconnect
interface Debug

Code Memory system Debug

memory and peripherals interface
Optional