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    Conditional Execution Branching.pptx

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    Conditional Execution Branching.pptx

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    Senthil

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    © All Rights Reserved
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    Download as pdf or txt
    of 37

    20RA210 –MICROCONTROLLERS

    AND EMBEDDED SYSTEMS


    MODULE-3 ARM INSTRUCTIONS
    Conditional execution

    • An unusual feature of the ARM instruction set is that


    every instruction (with the exception of certain v5T
    instructions) is conditionally executed.
    • The ARM Instruction Set conditional execution to all of its
    instructions, including supervisor calls and coprocessor
    instructions.
    • The condition field occupies the top four bits of the 32-bit
    instruction field:
    The 'never'
    condition
    • The 'never' condition (NV) should not be used -
    there are plenty of other ways to write no-ops
    (instructions that have no effect on the processor
    state) in ARM code.
    • The reason to avoid the 'never' condition is that
    ARM Limited have indicated that they may use
    this area of the instruction space for other
    purposes in the future.
    ARM condition codes
    Branch and Branch with Link (B, BL)

    • Branch and Branch with Link instructions are the


    standard way to cause a switch in the sequence of
    instruction execution.
    • The ARM normally executes instructions from sequential
    word addresses in memory, using conditional execution
    to skip over individual instructions where required.
    • Whenever the program must deviate from sequential
    execution a control flow instruction is used to modify the
    program counter.
    Binary encoding
    • Branch and Branch with Link instructions cause the processor
    to begin executing instructions from an address computed by
    sign extending the 24-bit offset specified in the instruction,
    shifting it left two places to form a word offset, then adding it
    to the program counter which contains the address of the
    branch instruction plus eight bytes.
    Assembler format
    • 'L'specifies the branch and link variant
    • if 'L' is not included a branch without link is generated.
    • '<cond>' should be one of the mnemonic extensions
    Branch, Branch with Link and exchange
    (BX, BLX)
    • These instructions are available on ARM chips which
    support the Thumb (16-bit) instruction set, and are a
    mechanism for switching the processor to execute
    Thumb instructions or for returning symmetrically to ARM
    and Thumb calling routines.
    Software Interrupt (SWI)

    • The software interrupt instruction is used for calls to the


    operating system and is often called a 'supervisor call'.
    • It puts the processor into supervisor mode and begins
    executing instructions from address 0x08.
    Software Interrupt (SWI)

    • The 24-bit immediate field does not influence the


    operation of the instruction but may be interpreted
    by the system code.
    1. Save the address of the instruction after the SWI in
    r14_svc.
    2. Save the CPSR in SPSR_svc.
    3. Enter supervisor mode and disable IRQs (but not
    FIQs) by setting CPSR[4:0] to 100112andCPSR[7]tol.
    4. Set the PC to 08 ]6 and begin executing the
    instructions there.
    Data processing instructions

    • The ARM data processing instructions are used to


    modify data values in registers.
    • The operations that are supported include arithmetic
    and bit-wise logical combinations of 32-bit data
    types.
    • One operand may be shifted or rotated en route to
    the ALU, allowing, for example, shift and add in a
    single instruction.
    Single word and unsigned byte data
    transfer instructions
    • These instructions are the most flexible way to transfer
    single bytes or words of data between ARM's registers
    and memory.
    • Transferring large blocks of data is usually better done
    using the multiple register transfer instructions, and
    recent ARM processors also support instructions for
    transferring half-words and signed bytes.
    Binary encoding
    Assembler
    format
    Examples
    Half-word and signed byte data
    transfer instructions
    • These instructions are not supported by some
    early ARM processors.
    • As a result of their late addition to the
    architecture they are somewhat 'shoe-horned'
    into the instruction space as indicated by the
    split immediate field
    Binary encoding
    Description
    • These instructions are very similar to the word
    and unsigned byte forms described in the
    previous section, but here the immediate
    offset is limited to eight bits and the scaled
    register offset is no longer available.
    Assembler
    formats
    Examples
    Multiple register transfer instructions
    • The ARM multiple register transfer instructions allow
    any subset (or all) of the 16 registers visible in the
    current operating mode to be loaded from or stored
    to memory.
    • A form of the instruction also allows the operating
    system to load or store the user-mode registers to
    save or restore the user process state, and another
    form allows the CPSR to be restored from the SPSR as
    part of a return from an exception handler.
    Binary encoding
    Assembler
    format
    Examples
    Swap memory and register instructions
    (SWP)
    • Swap instructions combine a load and a store
    of a word or an unsigned byte in a single
    instruction.
    • These instructions are little used outside their
    role in the construction of semaphores.
    Binary encoding
    Description
    • The instruction loads the word (B = 0) or
    unsigned byte (B = 1) at the memory location
    addressed by Rn into Rd, and stores the same
    data type from Rm into the same memory
    location.
    • Rd and Rm may be the same register (but
    should both be distinct from Rn), in which
    case the register and memory values are
    exchanged.
    Assembler
    format
    Example
    The Thumb Instruction Set
    • The Thumb instruction set addresses the issue
    of code density.
    • It may be viewed as a compressed form of a
    subset of the ARM instruction set.
    • Thumb instructions map onto ARM instructions,
    and the Thumb programmer's model maps onto
    the ARM programmer's model.
    The Thumb programmer's model
    • The Thumb instruction set is a subset of the ARM
    instruction set and the instructions operate on a
    restricted view of the ARM registers
    • The instruction set gives full access to the eight 'Lo'
    general purpose
    Registers r0 to r7, and makes extensive use of r13 to r15
    for special purposes:
    • • r13 is used as a stack pointer.
    • • r14 is used as the link register.
    • • r15 is the program counter (PC).
    .
    The Thumb programmer's model
    Thumb branch instructions
    • These control flow instructions include the
    various forms of PC-relative branch and
    branch-and-link instruction seen in the ARM
    instruction set, and the branch-and-exchange
    instruction for switching between the ARM
    and Thumb instruction sets.
    Binary
    encodings
    Thumb implementation
    Example and exercises

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