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    Previa_P4_4

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    mmroman530

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    © All Rights Reserved
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    Previa_P4_4

    Uploaded by

    mmroman530
    1 views3 pages

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    © All Rights Reserved
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    1 views3 pages

    Previa_P4_4

    Uploaded by

    mmroman530

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    © All Rights Reserved
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    of 3

    EP1. Diseñar el componente codificador.

    vhd

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity codificador is
    Port (entrada : in STD_LOGIC_VECTOR (7 downto 0);
    salida : out STD_LOGIC_VECTOR (11 downto 0));
    end codificador;

    architecture Behavioral of codificador is


    begin
    salida<=
    "000000001000" when "00000001",
    "000000010110" when "00000010",
    "000000110010" when "00000100",
    "000001100100" when "00001000",
    "000100101000" when "00010000",
    "001001010110" when "00100000",
    "010100010010" when "01000000",
    "100110010101" when "10000001",
    "100110010011" when "10000010",
    "100110010110" when "10000100",
    "100101101001" when "10001000",
    "100100110101" when "10010000",
    "011001010011" when "10100000",
    "011101000101" when "11000000",
    "000000000000" when others;

    ‐‐completar la arquitectura
    end Behavioral;

    EP2. Diseño del componente mux.vhd

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity mux is
    Port ( A : in STD_LOGIC_VECTOR (12 downto 0);
    B : in STD_LOGIC_VECTOR (12 downto 0);
    sel : in STD_LOGIC;
    Y : out STD_LOGIC_VECTOR (12 downto 0));
    end mux;

    architecture Behavioral of mux is

    begin
    withsel select
    Y<= A when '0',
    B when other;

    end Behavioral;
    Ep4_3

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
    entity BCD7seg is
    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
    segmentos : out STD_LOGIC_VECTOR (6 downto 0));
    end BCD7seg;
    ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
    architecture Behavioral of BCD7seg is
    begin
    with A select
    segmentos <=
    "0000001" when "0000",
    "1001111" when "0001",
    "0010010" when "0010",
    "0000110" when "0011",
    "1001100" when "0100",
    "0100100" when "0101",
    "0100000" when "0110",
    "0001111" when "0111",
    "0000000" when "1000",
    "0001100" when “1001”,
    "1111110" when "1111"
    “1111111” when others;
    end Behavioral;

    EP4_4
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity ca1000 is
    Port ( BCDin: in STD_LOGIC_vector (11 downto 0);
    BCDout: out STD_LOGIC_VECTOR (11 downto 0));
    end ca1000;

    architecture Behavioral of ca1000 is

    component Ca999
    port (BCDin: in std_logic_vector (11 downto 0);
    BCDout: out std_logic_vector (11 downto 0));
    end component;

    component sumadorBCD
    port ( A : in STD_LOGIC_VECTOR (3 downto 0);
    B : in STD_LOGIC_VECTOR (3 downto 0);
    Cin : in STD_LOGIC;
    Cout : out STD_LOGIC;
    S : out STD_LOGIC_VECTOR (3 downto 0));
    end component;

    Lógica Programable. VHDL


    Aritmética BCD en VHDL -10- Electrónica Digital
    signal U1: std_logic_vector (3 downto 0)
    signal C1: std_logic_vector (3 downto 0)
    signal D1: std_logic_vector (3 downto 0)
    signal

    begin
    U1: Ca999 PORT MAP ( BCDin=> __BCDin____,
    BCDout => __BCDout___);
    U2: sumadorBCD PORT MAP ( Cin=>__'1'____,
    A=> __BCDout(11 dowto 8)____,
    B=> _"0000"_____,
    S=> ____U1__,
    Cout =>______);
    U3: sumadorBCD PORT MAP ( Cin=>__Cout____,
    A=> __BCDout(7 downto 4)____,
    B=> _"0000"_____,
    S=> ___D1___,
    Cout =>_Cin_____);
    U4: sumadorBCD PORT MAP ( Cin=>___Cout___,
    A=> __BCDout(3 downto____,
    B=> "0000"______,
    S=> __C1____);
    end Behavioral;

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