MCP2557FD/8FD: CAN FD Transceiver With Silent Mode
MCP2557FD/8FD: CAN FD Transceiver With Silent Mode
MCP2557FD/8FD: CAN FD Transceiver With Silent Mode
VIO VDD
VIO
PERMANENT
TXD
DOMINANT DETECT
DRIVER CANH
VIO AND
SLOPE CONTROL
CANL
MODE
S
CONTROL
VDD CANH
RXD HS_RX
CANL
VSS
Note: Only the MCP2558FD has the VIO pin. In the MCP2557FD, the supply for the digital I/O is internally
connected to VDD.
From any
State
UnPowered (POR)
CAN High Impedance TXD Time-Out
Common Mode Tied to CAN Recessive
GND Common Mode VDD/2
HS RX OFF HS RX ON
RXD High RXD = f(HS RX)
Bandgap OFF
TXD High
And
Bandgap ok
Wake And
Start Bandgap VDD > VUVH Normal
CAN High Impedance And CAN Driven
Common Mode Tied to Silent Low Common Mode VDD/2
GND HS RX ON
HS RX OFF RXD = f(HS RX)
RXD High Bandgap Not Ok
Or
VDD < VUVL
Bandgap Not Ok
SILENT Low
Or SILENT High
SILENT High
VDD < VUVL
And
Silent
CAN Recessive (TX OFF)
Common Mode VDD/2
HS RX ON
RXD = f(HS RX)
VBAT
5V LDO
0.1 μF
CANH
VDD VDD
CANH
MCP2557FD
CANTX TXD
60 4700 pF
MCU
PIC®
CANRX RXD NC
60
RBX S CANL
CANL
VSS VSS
VBAT
5V LDO
3.3V LDO
0.1 µF
0.1 µF
RBX S CANL
CANL
VSS VSS
A number of terms are defined in ISO/DIS-11898 that 2.1.6 INTERNAL CAPACITANCE, CIN
are used to describe the electrical characteristics of a (OF A CAN NODE)
CAN transceiver device. These terms and definitions
Capacitance seen between CANL (or CANH) and
are summarized in this section.
ground during the Recessive state when the CAN node
2.1.1 BUS VOLTAGE is disconnected from the bus (see Figure 2-1).
VCANL and VCANH denote the voltages of the bus line 2.1.7 INTERNAL RESISTANCE, RIN
wires CANL and CANH relative to the ground of each (OF A CAN NODE)
individual CAN node.
Resistance seen between CANL (or CANH) and
2.1.2 COMMON MODE BUS VOLTAGE ground during the Recessive state when the CAN node
RANGE is disconnected from the bus (see Figure 2-1).
† Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Supply
VDD Pin
Voltage Range VDD 4.5 — 5.5 V
Supply Current IDD — 2.5 5 mA Recessive; VTXD = VDD
— 55 70 Dominant; VTXD = 0V
Silent Current IDDS — 1 3 mA MCP2557FD
— 1 3 MCP2558FD Includes IIO
Maximum Supply Current IDDMAX — 95 140 mA Fault condition: VTXD = VSS;
VCANH = VCANL = -5V to +18V
High Level of the POR VPORH — 3.0 3.95 V Note 1
Comparator for VDD
Low Level of the POR VPORL 1.0 2.0 3.2 V Note 1
Comparator for VDD
Hysteresis of POR VPORD 0.2 0.9 2.0 V Note 1
Comparator for VDD
High Level of the UV VUVH 4.0 4.25 4.4 V
Comparator for VDD
Low Level of the UV VUVL 3.6 3.8 4.0 V
Comparator for VDD
Hysteresis of UV comparator VUVD — 0.4 — V Note 1
VIO Pin
Digital Supply Voltage Range VIO 1.7 — 5.5 V
Supply Current on VIO IIO — 7 30 µA Recessive; VTXD = VIO
— 200 400 Dominant; VTXD = 0V
High Level of the POR VPORH_VIO 0.8 1.2 1.7 V
Comparator for VIO
Low Level of the POR VPORL_VIO 0.7 1.1 1.4 V
Comparator for VIO
Hysteresis of POR VPORD_VIO — 0.2 — V
Comparator for VIO
Bus Line (CANH; CANL) Transmitter
CANH; CANL: VO(R) 2.0 0.5 VDD 3.0 V VTXD = VDD; No load
Recessive Bus Output Voltage
Recessive Output Current IO(R) -5 — +5 mA -24V < VCAN < +24V
CANH: Dominant Output VO(D) 2.75 3.50 4.50 V TXD = 0; RL = 50 to 65
Voltage
CANL: Dominant Output 0.50 1.50 2.25 RL = 50 to 65
Voltage
Driver Symmetry VSYM 0.9 1.0 1.1 V 1 MHz square wave,
(VCANH+VCANL)/VDD Recessive and Dominant
states, and transition (Note 1)
Note 1: Characterized; not 100% tested.
2: Only MCP2558FD has a VIO pin. For MCP2557FD, VIO is internally connected to VDD.
3: -12V to 12V is ensured by characterization, and tested from -2V to 7V.
CANH
CANH, CANL
CANL
Time
VDD
CANH
CANL
VDD/2
RL
CL CL
Pin Pin
RL = 464
CL = 50 pF for all digital pins VSS VSS
VDD 0.1 µF
CANH
TXD
CAN RL CL
Transceiver
RXD
15 pF CANL
GND S
CAN Transient
RL
Transceiver Generator
RXD
CANL 1000 pF
GND S
VOL
VDIFF (H)(I)
VDD
TXD (transmit data
input voltage)
0V
VDIFF (CANH,
CANL differential
voltage)
Minimum pulse width until CAN bus goes to Dominant state after the falling edge.
TXD
VDIFF (VCANH-VCANL)
Driver is off
11 12
70%
TXD 30% 30%
5*tBIT(TXD) tLOOP(F)
TBIT(TXD)
VDIFF_BUS 900 mV
500 mV
13
tBIT(BUS)
70%
RXD
30%
tLOOP(R)
8
tBIT(RXD)
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
2.3
2.2 -40 25 150
Dominant Differential Output
2.1
2
1.9
1.8
(V)
1.7
1.6
1.5
1.4
1.3
40 45 50 55 60 65 70 75
RL (Ω)
2.3
Dominant Differential Output
2.2
2.1
2
1.9
(V)
1.8
1.7
1.6
1.5
1.4 -40 25 150
1.3
40 45 50 55 60 65 70 75
RL (Ω)
2.6
Dominant Differential Output
2.5
2.4
2.3
2.2
2.1
(V)
2
1.9
1.8
1.7 -40 25 150
1.6
40 45 50 55 60 65 70 75
RL (Ω)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.75mm Body [TDFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D A B
N
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.15 C
1 2
2X
0.15 C
TOP VIEW
0.10 C
(A3)
C A
SEATING
PLANE 8X
A1 0.08 C
SIDE VIEW
0.10 C A B
L D2
1 2
0.10 C A B
NOTE 1
E2
K
N
8X b
e 0.10 C A B
0.05 C
BOTTOM VIEW
Microchip Technology Drawing No. C04-129-MN Rev D Sheet 2 of 2
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.75mm Body [TDFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 0.50 BSC
Overall Height A 0.70 0.75 0.80
Standoff A1 0.00 0.02 0.05
Contact Thickness A3 0.20 REF
Overall Length D 2.00 BSC
Overall Width E 3.00 BSC
Exposed Pad Length D2 1.45 - 1.65
Exposed Pad Width E2 1.60 - 1.80
Contact Width b 0.20 0.25 0.30
Contact Length L 0.25 0.30 0.45
Contact-to-Exposed Pad K 0.20 - -
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.75mm Body [TDFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X2
EV
8
ØV
C Y2 EV
Y1
1 2
SILK SCREEN
X1
E
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.50 BSC
Optional Center Pad Width X2 1.65
Optional Center Pad Length Y2 1.80
Contact Pad Spacing C 2.90
Contact Pad Width (X8) X1 0.25
Contact Pad Length (X8) Y1 0.85
Thermal Via Diameter V 0.30
Thermal Via Pitch EV 1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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