80286

Introduction & Architecture

80286 ARCHITECTURE
80286 Architecture consists of four separate processing units:

1) Address Unit (AU)

2) Bus Unit (BU)

3) Instruction Unit (IU)

4) Execution Unit (EU)

 80286
Register Organization
 80286
Memory Access in GDT & LDT
STRUCTURE OF GLOBAL DESCRIPTOR
LOCAL AND GLOBAL DESCRIPTORS
CALCULATION OF MAXIMUM ACCESSIBLE VIRTUAL MEMORY
• Global Descriptors are 8K and Local Descriptors are 8K in number.

• Total no. of Descriptors = 8K + 8K = 16K

• There can be 16K Segments.

• Since each segment can have a maximum size of 64KB,

MAXIMUM ACCESSIBLE VIRTUAL MEMORY = 16K x 64KB = 1GB

ACCESS RIGHTS BYTE
DATA TYPES SUPPORTED BY 80286
 80386
Introduction & Architecture
Introduction : 80386
-----------------------------------------------------------------------------------------------------------------
• MMU supports paging, virtual memory and 4-level protection.

• Using paging, 80386 organizes the available physical memory into pages
of 4kB each.

• 8 debug registers (DR0-DR7) for hardware debugging and control.

• Has on-chip address translation queue.

• 2 versions: 80386DX & 80386SX (16-bit D’bus, 24-bit A’bus, low power &
low cost).

• 80386DX132 pin IC in PGA package20MHz & 33MHz versions.

 80386
Register Organization
 80386
Operating Modes
80386: Real Address Mode

• 80386 can address 1MB of Physical Memory using A0-A19.

• Paging Unit is disabled in this mode  Real Address = Physical Address.

• Segments in this mode can be read, written or executed  no protection.

• IVT of 80386 is allocated 1kB space from 00000H to 0003FFH.

48
 80386
Memory Access in Virtual Mode
Stores DBA
Structure of 80386 Segment Descriptor
 80486
Introduction
80586 (PENTIUM-1) PROCESSOR AND ITS
SUCCESSORS
 Features of Pentium Processors (80586)
64-bit data bus
• 8 bytes of data information can be transferred to and from memory in a
single bus cycle
• Supports burst read and burst write back cycles
• Supports pipelining

Instruction cache
• 8 KB of dedicated instruction cache
• 256 lines between instruction cache and prefetch buffers; allows 32 bytes to
be transferred from cache to buffer
 Features of Pentium Processors (80586)
Data cache
• 8 KB dedicate data cache gives data to execution units
• 32-bit lines

Two parallel integer execution units

• Allows the execution of two instructions to be executed simultaneously in a single
processor clock

Floating Point Unit

• FPU fetches operands from either FPR file or from data cache.
• 8 general-purpose floating-point registers (80 bits wide-64bits for mantissa & 16bits
for exponent)
• Speeds up (upto 5 times faster than 80486) common operations including add,
multiply, divide, exponentiation and rounding.
 Features of Pentium Processors (80586)
Branch Prediction Logic
• To reduce the time required for a branch caused by internal delays
• When a branch instruction is encountered, microprocessor begins prefetching
instruction at the branch address stored in Branch Target Buffer (BTB)

Data Integrity and Error Detection

• Has significant error detection and data integrity capability
• Data parity checking is done on byte – byte basis
• Address parity checking and internal parity checking features are added

Dual Integer Processor

• Allows execution of two instructions per clock cycle
 Features of Pentium Processor (80586)
Functional redundancy check
• To provide maximum error detection of the processor and interface to the processor

• A second processor ‘checker’ is used to execute in lock step with the ‘master’ processor

• It checks the master’s output and compares the value with the internal computed values

• An error signal is generated in case of mismatch

Superscalar architecture
• Three execution units
• One execution unit executes floating point instructions
• The other two (U pipe and V pipe) execute integer instructions
• Parallel execution of several instructions – superscalar processor
 Features of Pentium Processor (80586)
Intel MMX Architecture (introduced from P-II)
• Intel introduced MMX (Multimedia Extension) technology when there was need to
improve 2-D and 3-D imaging for multimedia applications.

• Most of the image processing algorithms in multimedia apps involve operations on several
pixels simultaneously.

• Most of the multimedia apps require Single Instruction Stream Multiple Data Stream
(SIMD) kind of architecture.

• Intel provides a set of 57 MMX instructions.

• Using conventional CPU, we can operate on 2 pixels simultaneously; whereas using MMX,
we can operate on 8 pixels concurrently.
 FEATURES OF PENTIUM PROCESSOR (80586)
INTEL MMX ARCHITECTURE
• MMX instructions use 8 FPRs as MMX registers and use only 64-bit mantissa portion of
these registers.
• As these MMX registers are 64-bit sized, one can pack a total of 8-pixel values in one
register manipulation of these 8 pixels simultaneously is possible with MMX technology.
• 4 MMX data types: Packed bytes, words, doubleword and one quadword.
• Some of the MMX instructions are PADD (B,W,D), PSUB, PCMPEQ, PCMPGT, PMULLW,
PMULHW, PMADDWD, PAND/POR/PXOR, PSRA/PSRL.

 EXAMPLE OF PCMPGT
 DATA TYPES FOR MMX

• 64 bits long. One data item can store:

8 one-byte integers:

4 two-byte integers:

2 four-byte integers

1 eight-byte integer
 APPLICATIONS OF MMX TECHNOLOGY
 Graphics
 MPEG video/image processing
 Music synthesis
 Speech compression
 Video conferencing
 Matrix and vector calculations
 Advanced 3D graphics
 Speech recognition
 PENTIUM PRO FEATURES
• The Pentium Pro processor has 36 address lines.

• The Pentium Pro processor is three-way superscalar.

• Using parallel processing techniques, the processor is able on average to decode, dispatch, and
complete execution of (retire) three instructions per clock cycle.
• The Pentium Pro introduced the dynamic execution (micro-data flow analysis, out-of-order
execution, superior branch prediction, and speculative execution) in a superscalar implementation.
• The processor was further enhanced by its caches. It has the same two on-chip 8KB 1st-Level
caches as the Pentium processor.
• An additional 256KB Level 2 cache in the same package as the processor.

• The L2 cache is connected to BIU, BIU generates memory addresses and control signals and
passes or fetches data or instructions either to L1 data cache or L1 instruction cache.

• The Instruction Fetch and Decode Unit (IFDU), contains three separate instruction decoders that
decode three instructions simultaneously
 PENTIUM PRO FEATURES
• It also includes Branch Prediction Logic.

• It predicts if the branch will be taken or not for a conditional jump instruction

• The instructions are then put into the instruction pool.

• The execute unit consists of three units namely two integer execution unit
and one floating point unit – two integer and one floating instruction can be
executed simultaneously

• The instruction once executed is retired and the result is written into the
destination location by the retire unit
• It is the last stage of instruction execution.
 INTEL CORE 2 DUO
Microarchitecture
The Cores
◦ Single-die(107 mm²),
◦ Two identical core(L1 cache 64K x 2),
◦ Shared L2 cache 6M
◦ No Hyper-threading, no L3 cache
◦ Keep front-side bus
◦ Larger L2 cache
INTEL CORE 2 DUO MICROARCHITECHTURE
 CORE 2 DUO FEATURES
• Intel Core 2 Duo processor family support Intel 64 architecture; they are
based on the high-performance, power-efficient Intel Core microarchitecture
built on 65 nm process technology.
• The Intel Core microarchitecture includes the following innovative features:
• Intel Wide Dynamic Execution to increase performance and execution
throughput
• Intel Intelligent Power Capability to reduce power consumption
• Intel Advanced Smart Cache which allows for efficient data sharing between
two processor cores
• Intel Smart Memory Access to increase data bandwidth and hide latency of
memory accesses
• Intel Advanced Digital Media Boost which improves application performance
using multiple generations of Streaming SIMD extensions
 CORE 2 DUO FEATURES
Intel® Wide Dynamic Execution enable each processor core to fetch, dispatch, execute in high bandwidths to
support retirement of up to four instructions per cycle.
• Fourteen-stage efficient pipeline
• Three arithmetic logical units per port
• Four decoders to decode up to five instruction per cycle
• Macro-fusion and micro-fusion to improve front-end throughput
• Peak issue rate of dispatching up to six micro-ops per cycle
• Peak retirement bandwidth of up to 4 micro-ops per cycle
• Advanced branch prediction
• Stack pointer tracker to improve efficiency of executing function/procedure entries and exits.
Intel® Advanced Smart Cache delivers higher bandwidth from the second level cache to the core, and optimal
performance and flexibility for single-threaded and multi-threaded applications.
• Large second level cache up to 4 MB and 16-way associativity
• Optimized for multicore and single-threaded execution environments
• 256-bit internal data path to improve bandwidth from L2 to first-level data cache
CORE 2 DUO FEATURES
Intel® Smart Memory Access prefetches data from memory in
response to data access patterns and reduces cache-miss exposure of
out-of-order execution.
• Hardware prefetchers to reduce effective latency of second-level
cache misses
• Memory disambiguation to improve efficiency of speculative
execution engine
Intel® Advanced Digital Media Boost improves most 128-bit SIMD
instruction with single-cycle throughput and floating-point operations.
• Single-cycle throughput of most 128-bit SIMD instructions
• Up to eight floating-point operation per cycle
 HYPER-THREADING TECHNOLOGY

Traditional methods to Enhance Performance-

Increase in clock rate

o Involves reducing clock cycle time

o Can increase the performance by increasing number of instructions finishing per second
o H/w limitations limit this feature

Cache hierarchies

o Having frequently used data on the processor caches reduces average accesses time
 HYPER-THREADING TECHNOLOGY
Pipelining

o Implementation Technique whereby multiple instructions are overlapped in execution

o Limited by the dependencies between instructions

o Effected by stalls and effective CPI is greater than 1

Instruction Level Parallelism

o It refers to techniques to increase the number of instructions executed in each clock cycle.

o Exists whenever the machine instructions that make up a program are insensitive to the
order in which they are executed if dependencies does not exist, they may be executed.
 HYPER-THREADING TECHNOLOGY
Thread level parallelism
Chip MultiProcessing
o Two processors, each with full set of execution and architectural resources, reside on a single die.
Time Slice Multi Threading
o single processor to execute multiple threads by switching between them
Switch on Event Multi Threading
o switch threads on long latency events such as cache misses
Simultaneous Multi Threading
o Multiple threads can execute on a single processor without switching.
o The threads execute simultaneously and make much better use of the resources.
o It maximizes the performance vs. transistor count and power consumption.
 HYPER-THREADING TECHNOLOGY

Hyper-Threading Technology brings the simultaneous multi-threading approach to the

Intel architecture.

 Hyper-Threading Technology makes a single physical processor appear as two or more

logical processors

 Hyper-Threading Technology first invented by Intel Corp.

 Hyper-Threading Technology provides thread-level-parallelism (TLP) on each processor

resulting in increased utilization of processor and execution resources.

Each logical processor maintain one copy of the architecture state

Hyper-Threading Technology Architecture

Arch State Arch State Arch State

Processor Execution Processor Execution

Resources Resources

Processor with out Hyper- Processor with Hyper-Threading

Threading Technology Technology
 Following resources are duplicated to support
Hyper-Threading Technology

Register Alias Tables

Next-Instruction Pointer

Instruction Streaming Buffers and Trace Cache Fill Buffers

Instruction Translation Look-aside Buffer

 HYPER-THREADING TECHNOLOGY

Sharing of Resources
 Major Sharing Schemes are-
o Partition
o Threshold
o Full Sharing
Partition
 Each logical processor uses half the resources
 Simple and low in complexity
 Ensures fairness and progress
 Good for major pipeline queues
 HYPER-THREADING TECHNOLOGY
Threshold

 Puts a threshold on number of resource entries a logical processor can use.

 Limits maximum resource usage
 For small structures where resource utilization in burst and time of utilization
is short, uniform and predictable
 Eg- Processor Scheduler
 HYPER-THREADING TECHNOLOGY
Full Sharing
 Most flexible mechanism for resource sharing, do not limit the maximum uses
for resource usage for a logical processor
 Good for large structures in which working set sizes are variable and there is no
fear of starvation
 Eg: All Processor caches are shared
Some applications benefit from a shared cache because they share code and
data, minimizing redundant data in the caches
 HYPER-THREADING TECHNOLOGY
SINGLE-TASK AND MULTI-TASK MODES
Two modes of operations
◦ single-task (ST)
◦ multi-task (MT).
MT-mode- There are two active logical processors and some of the resources are
partitioned.
 There are two flavors of ST-mode: single-task logical processor 0 (ST0) and
single-task logical processor 1 (ST1).
 In ST0- or ST1-mode, only one logical processor is active, and resources that were
partitioned in MT-mode are re-combined to give the single active logical processor
use of all the resources
HYPER-THREADING TECHNOLOGY

SINGLE-TASK AND MULTI-TASK MODES

HALT instruction that stops processor execution.

On a processor with Hyper-Threading Technology, executing

HALT transition the processor from MT-mode to ST0- or ST1-
mode, depending on which logical processor executed the
HALT.

In ST0- or ST1-modes, an interrupt sent to the halted logical

processor would cause a transition to MT-mode.
 HYPER-THREADING TECHNOLOGY
OPERATING SYSTEM
For best performance, the operating system should implement
two optimizations.

◦ The first is to use the HALT instruction if one logical

processor is active and the other is not. HALT will allow the
processor to transition MT mode to either the ST0- or ST1-
mode.

◦ The second optimization is in scheduling software threads

to logical processors. The operating system should schedule
threads to logical processors on different physical
processors before scheduling two threads to the same
physical processor.
 HYPER-THREADING TECHNOLOGY
Benefits of Hyper-Threading Technology

Higher transaction rates for e-Businesses

Improved reaction and response times for end-users and customers.

Increased number of users that a server system can support

Handle increased server workloads

Compatibility with existing server applications and operating systems

 HYPER-THREADING TECHNOLOGY

•Intel’s Hyper-Threading Technology brings the concept of simultaneous

multi-threading to the Intel Architecture.
•It will become increasingly important going forward as it adds a new
technique for obtaining additional performance for lower transistor and
power costs.
•The goal was to implement the technology at minimum cost while
ensuring forward progress on logical processors, even if the other is
stalled, and to deliver full performance even when there is only one
active logical processor.
 Concepts of RISC

RISC is a type of microprocessor architecture that utilizes a small, highly-

optimized set of instructions, rather than a more specialized set of instructions
often found in other types of architectures.
 Concepts of RISC

History Of RISC:
1. RISC approach developed as a result of development in 1970’s.
2. Increase in memory size.
3. Decrease in cost.
4. Advanced compilers.
5. In late 1970’s IBM was the first to start.
6. In 1980 , David Patterson ,began the project
that gives this approach RISC.
 Concepts of RISC

Characteristics Of RISC:
◦ Simplified instructions , taking 1 clock cycle.
◦ Large no. of general-purpose registers.
◦ Circuit is much simpler.
◦ Fast to decode.
◦ Fast to execute.
◦ Pipelining- fetching of next instruction while previous instruction executes.
 Concepts of RISC

RISC Has Five Design Principles:

• Simple Instructions:
The objective is to design simple instruction so that each can execute in one cycle.

• Register-to-Register Operations:
RISC processors only allow LOAD/STORE operations to access memory.

Rest of the operations work on the register-to-register basis.

This feature of restricting operands to registers also simplifies the control-unit.

 Concepts of RISC

Design Principles: (Cont.)

• Simple Addressing Modes:
RISC processors employ register-to-register instruction so most instruction use register-based
addressing.

Only LOAD/STORE instructions need memory addressing modes.

• Large Register Set:

For register-to-register operation large number of registers required.

Provide ample opportunities for the compiler to optimize their usage.

 Concepts of RISC

Design Principles: (Cont.)

• Fixed-Length:
RISC design use fixed-length instructions. Variable length instructions cause implementation
and execution inefficient.
The boundaries of various fields in an instruction such as opcode and source operands are fixed.
This allows efficient decoding and scheduling of instructions.
 Concepts of RISC

What Actually RISC Does?

 Break Operation into Simple Sub-Operation.

Example:-
Load X, Load Y,
add X and Y,
Store on Z
X *Y→Z
 Concepts of RISC

In Real Life Use of RISC Architectures:

 RISC architectures are now used across a wide range of platforms, from cellular telephones and
tablet computers.

 Intel was able to spend vast amounts of money on processor development to offset the RISC
advantages enough to maintain PC market share.

 New microprocessors can be developed and tested more quickly if being less complicated is
one of it’s aims.
 RISC Vs CISC
RISC stands for ‘Reduced Instruction Set Computer Whereas, CISC stands
for Complex Instruction Set Computer. The RISC processors have a smaller
set of instructions with few addressing nodes. The CISC processors have a
larger set of instructions with many addressing nodes.

RISC Vs CISC

1. Memory Unit
RISC has no memory unit and uses a separate hardware to implement
instructions. CISC has a memory unit to implement complex instructions

2. Program
RISC has a hard-wired unit of programming. CISC has a microprogramming
unit

3.Design
RISC is a complex compiler design. CISC is an easy compiler design

4.Calculations
RISC calculations are faster and more precise. CISC calculations are slow
and precise
 RISC Vs CISC
5.Decoding
RISC decoding of instructions is simple. CISC decoding of instructions is complex

6.Time
Execution time is very less in RISC. Execution time is very high in CISC.

7.External memory
RISC does not require external memory for calculations. CISC requires external
memory for calculations.

8. Pipelining
RISC Pipelining does function correctly. CISC Pipelining does not function
correctly.

9.Stalling
RISC stalling is mostly reduced in processors. CISC processors often stall.

10. Code Expansion

Code expansion can be a problem in RISC whereas, in CISC, Code expansion is
not a problem.
 RISC Vs CISC

11. Disc space

Space is saved in RISC whereas in CISC space is wasted. The best examples
of CISC instruction set architecture include VAX, PDP-11, Motorola 68k,And
your desktop PCs on Intel’s x86 architecture, whereas the best examples of
RISC architecture include DEC Alpha, ARC, AMD 29k, Atmel AVR, Intel
i860, Blackfin, i960, Motorola 88000, MIPS, PA-RISC, Power, SPARC,
SuperH, and ARM too.

12. Applications of RISC and CISC

RISC is used in high-end applications like video processing,
telecommunications and image processing.
CISC is used in low-end applications such as security systems, home
automation, etc.
 RISC CISC
1. RISC stands for Reduced Instruction Set 1. CISC stands for Complex Instruction Set
Computer. Computer.
`
2. RISC processors have simple instructions
2. CSIC processor has complex instructions that
take up multiple clocks for execution. The
taking about one clock cycle. The average clock
average clock cycle per instruction (CPI) is in
cycle per instruction (CPI) is 1.5
the range of 2 and 15.

3. Performance is optimized with more focus on 3. Performance is optimized with more focus on
software hardware.

4. It has no memory unit and uses a separate 4. It has a memory unit to implement complex
hardware to implement instructions.. instructions.

5. It has a hard-wired unit of programming. 5. It has a microprogramming unit.

6. The instruction set is reduced i.e. it has only 6. The instruction set has a variety of different
a few instructions in the instruction set. Many of instructions that can be used for complex
these instructions are very primitive. operations.
 7. CISC has many different addressing modes
7. The instruction set has a variety of different and can thus be used to represent higher-level
instructions that can be used for complex operations. programming language statements more
efficiently.

8. Complex addressing modes are synthesized using 8. CISC already supports complex addressing
the software. modes
9. Multiple register sets are present 9. Only has a single register set
10. They are normally not pipelined or less
10. RISC processors are highly pipelined
pipelined
11. The complexity of RISC lies with the compiler
11. The complexity lies in the microprogram
that executes the program
12. Execution time is very less 12. Execution time is very high
13. Code expansion can be a problem 13. Code expansion is not a problem
14. Decoding of instructions is simple. 14. Decoding of instructions is complex
15. It does not require external memory for
15. It requires external memory for calculations
calculations
16. The most common RISC microprocessors are 16. Examples of CISC processors are the
Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power System/360, VAX, PDP-11, Motorola 68000 family,
Architecture, and SPARC. AMD and Intel x86 CPUs.

17. RISC architecture is used in high-end applications 17. CISC architecture is used in low-end
such as video processing, telecommunications and applications such as security systems, home
image processing. automation, etc.
Microcontrollers
Microcontrollers
Microcontrollers
 ACCORDING TO BITS

4-BIT MICROCONTROLLERS
 ALU performs arithmetic and logical operations on a nibble (4-bits) at an instruction.
 Internal bus width of 4-bit.
 Small size, minimum pin count and low-cost controllers.
 Low power consumption and used for low end applications like LED & LCD display drivers, portable
battery chargers.
 Examples: Renasa M34501 256 and ATAM862 series from ATMEL.
8-BIT MICROCONTROLLER
 ALU performs arithmetic and logical operations on a byte (8-bits) at an instruction.
 Internal bus width of 8-bit.
 Examples: Intel 8051 family and Motorola MC68HC11 family.
16-BIT MICROCONTROLLER
 ALU performs arithmetic and logical operations on a word (16-bits) at an instruction.
 Internal bus width of 16-bit microcontroller is of 16-bit.
 Enhanced performance, computing capability and greater precision as compared to the 8-bit
microcontrollers.
 Examples: Intel 8096 family, Motorola MC68HC12 and MC68332 families.
32-BIT MICROCONTROLLER
 ALU performs arithmetic and logical operations on a double word (32-bits) at an instruction.
 Internal bus width of 32-bit.
 Much more enhanced performance, computing capability with greater precision as compared to
16-bit microcontrollers.
 Examples: Intel 80960 family, Motorola M683xx and Intel/Atmel 251 family.
 ACCORDING TO MEMORY/DEVICES
EMBEDDED MICROCONTROLLERS
 An embedded system has a microcontroller unit that has all the functional blocks (including
program as well as data memory) available on the same chip.
 Example: 8051 having Program & Data Memory, I/O Ports, Serial Communication, Counters
and Timers and Interrupt Control logic on the chip.
EXTERNAL MEMORY MICROCONTROLLERS

 An external system has a microcontroller unit that does not have all the functional blocks
available on a chip.
 All or part of the memory units are externally interfaced using an interfacing circuit called the
glue circuit.
 Example: 8031 has no program memory on the chip.
 ACCODING TO INSTRUCTION SET
CISC (COMPLEX INSTRUCTION SET COMPUTER)
ARCHITECTURE MICROCONTROLLERS
 Has an instruction set that supports many addressing modes for the arithmetic and logical
instructions, data transfer and memory accesses instructions.
 Many of the instructions are macro like.
 Allows the programmer to use one instruction in place of many simpler instructions.
 Example: Intel 8096 family.
RISC (REDUCED INSTRUCTION SET COMPUTER)
ARCHITECTURE MICROCONTROLLERS
 Contains an instruction set that supports fewer addressing modes for the arithmetic and logical instructions and for data
transfer instructions.
 Allows simultaneous access of program and data.
 Instruction pipelining increases execution speed
 Allow each instruction to operate on any register or use any addressing mode.
 Smaller chip and pin count.
 Very low power consumption.
 ACCORDING TO MEMORY ARCHITECTURE

 The architectures of microcontrollers differ in the way data and programs are stored and accessed.
1. VON-NEUMAN /PRINCETON ARCHITECTURE
 Single data bus that is used to fetch both instructions and data.
 Program instructions and data are stored in a common main memory.
When such a controller addresses main memory, it first fetches an instruction, and then it fetches the data to
support the instruction.
1. VON-NEUMAN /PRINCETON ARCHITECTURE(cont.)

Simplifies the microcontroller design because only one memory is accessed.

 The weakness is that two separate fetches can slow up the controller’s operation.
 Example: Motorola 68HC11.
2. HARVARD ARCHITECTURE
 Separate data bus and an instruction bus.
 Execution occur in parallel.
 Much faster execution than Von-Neuman architecture.
 Design complexity.
 Example: intel MCS-51 family and PIC microcontrollers.
Central Processing Unit (CPU)
 The central processing unit processes the program. It executes the instructions stored in the program
memory pointed to by the program counter in synchronization with the clock signal.
ALU
 The arithmetic/logic unit (ALU) performs mathematical and logical operations on data.
Oscillator
 A complex digital device that generates steady pulse rate required for timing. All the separate functions
are controlled by one central timing system. The timing pulse provides the basis for proper sequence of all
the separate sections of the microcontroller chip.
Read Only Memory (ROM)
ROM holds the program instructions and the constant data.
Microcontrollers use one or more of the following memory types for this purpose:
 ROM (mask-programmed ROM),
 PROM (one-time programmable ROM, which is not field programmable),
 EPROM (field programmable and usually UV erasable),
 EEPROM (field programmable, electrically erasable, byte erasable) and flash (similar to EEPROM
technology).
 Microcontrollers can have 4K, 8K and 16K, etc. of ROM
Random Access Memory (RAM)
 is used to hold intermediate results and other temporary data during the execution of the program.
Typically, microcontrollers have a few hundreds of bytes of RAM.
Special-Function Registers
 control various functions of a microcontroller. These are divided into two groups:
 Registers wired into the CPU
- Do not necessarily form part of addressable memory.
- Used to control program flow and arithmetic functions.
- Examples, status register, program counter, stack pointer, etc.
Registers
 Register is used to hold the contents of data being manipulated.
 Registers required by peripheral components
- The contents of these registers include set a timer or enable serial communication.
- Examples, a program counter, stack pointer, RAM address register, program address register and PC
incrementer.
Peripheral Components
 The analogue-to-digital converter - provides an interface between the microcontroller and the sensors that
produce analogue electrical equivalents of the actual physical parameters to be controlled.
 The digital-to-analogue converter - provides an interface between the microcontroller and the actuators
that provide the control function.
 I/O ports - provide an interface between the microcontroller and the peripheral I/O devices such as the
keyboard, display, etc.
 Counters/timers - are used to keep time and/or measure the time interval between events, count the number
of events and generate baud rates for the serial ports.
Watchdog timer

 A specialized program found as part of the microcontroller designed to prevent the microcontroller
from halting or “locking up” because of a user-written program since the instructions are processed step-
by-step.
 Uses a routine that is based on timing. If a program has not been completed or repeated as a loop
within a certain amount of time, the watchdog timer issues a reset command.
 A system reset sets all the register values to zero.
 The reset feature allows the controller to recover from the crash.

It releases the program and sets the controller to start over again.
Stack Pointer and Program Counter

 Stack pointer - keeps track of the last stack location used while the processor is busy manipulating data
values, checking ports, or checking interrupts.
 Program counter - is used to hold the address of the instruction to be executed next.

Buses

 Bus represents a physical connection used to carry a signal from one point to another inside a
microcontroller. The signal carried by a bus may represent address, data, control signal, or power.
 Microcontroller operation
MODULE
 When a microcontroller is mounted on a circuit board with other components function as a single
unit, is referred as a module or a microcontroller board.
 A microcontroller module typically consists of microcontroller, a power source, an interface for
connecting to a programming device, I/O ports, and additional memory.
 Microcontroller operation: (Cont.)
A power source - powers the microcontroller and any accompanying components located on the printed circuit
board.
 An interface - communicate with the controller.
 A set of input/output (I/O) ports - send and receive signals from the devices the microcontroller is designed
to control.
 I/O ports when programmed as an output pin, each pin can output digital signals. When programmed as an
input pin, each pin can receive digital signals.
 Digital-to-analog and analog-to-digital converters change the digital pulses into analog signals.
 Internal Operation
The microcontroller consists of thousands of digital circuits that are combined into areas to provide specific functions.
 The parts of the microcontroller are used to save data and programs, perform math and logic functions,
and generate timing signals.
 The different areas are connected by a bus system. The bus system contains tiny parallel circuits that carry the digital pulse
patterns from section to section.
 The ROM stores the program required for the microcontroller to function and controls how the chip components operate and how
data and instructions flow through the chip.
 RAM stores programs and data temporarily.
 Ports and registers are special memory locations dedicated to a specific function such as a hardware location or a place to
manipulate data.
ADVANTAGEOUS FEATURES
 Easy to use and Programmable.
 Reusable - Ability to reprogram using Flash, EEPROM or EPROM.
 Flexibility and dependable.
 Design and Simulation.
 Energy efficient, small and cost effective.
 Ports multifunctionality.
 High Integration and can fit inside other devices.
 Easy upgrade.
AREAS OF MICROCONTROLLER APPLICATION
 Home monitoring system.
 Automotive applications such as robotics.
 Appliances such as microwave oven, refrigerators, television and VCRs, stereos.
 Automobiles in engine control, diagnostics, climate control.
 Environmental control in greenhouse, temperature, humidity, factory, home.
 Instrumentation.
 Aerospace.
Basic Features related to Microprocessor and Microcontrollers