Dte Model

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
(Autonomous)
(ISO/IEC - 27001 - 2013 Certified)
SUMMER-2024 EXAMINATION
Model Answer – Only for the Use of RAC Assessors
Subject Name: Digital Techniques Subject Code: 22320
Important Instructions to examiners:

XXXX
X
1) The answers should be examined by key words and not as word-to-word as given in the model answer
scheme.
2) The model answer and the answer written by candidate may vary but the examiner may try to assess the
understanding level of the candidate.
3) The language errors such as grammatical, spelling errors should not be given more Importance (Not
applicable for subject English and Communication Skills.
4) While assessing figures, examiner may give credit for principal components indicated in the figure. The
figures drawn by candidate and model answer may vary. The examiner may give credit for any
equivalent figure drawn.
5) Credits may be given step wise for numerical problems. In some cases, the assumed constant values may
vary and there may be some difference in the candidate’s answers and model answer.
6) In case of some questions credit may be given by judgement on part of examiner of relevant answer
based on candidate’s understanding.
7) For programming language papers, credit may be given to any other program based on equivalent
concept.
8) As per the policy decision of Maharashtra State Government, teaching in English/Marathi and Bilingual
(English + Marathi) medium is introduced at first year of AICTE diploma Programme from academic
year 2021-2022. Hence if the students write answers in Marathi or bilingual language (English
+Marathi), the Examiner shall consider the same and assess the answer based on matching of concepts
with model answer.
Sub
Q. Marking
Q. Answer
No. Scheme
N.
1. Attempt any FIVE of the following: 10 M
a) List the uses of following codes: 2M
i) BCD Code
ii) ASCII
Ans. The uses of following codes are: 1 M for any

i) BCD Code: two uses of
1) In digital communication each code
2) In Digital computers
3) In many personal computers to store date and time
4) In other digital systems where, precise decimal arithmetic operations
are required e.g. calculators.
5) In real time clock systems
ii) ASCII:
1) In computers to represent characters, symbols and alphabets.
2) Most computer keyboards are standardized using ASCII.
3) ASCII is standard for character encoding used in appliances,
telecommunications, computers and other related devices.
4) It is used to display text in various devices.
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b) Write the one application of SR-FF and mention its one drawback.
XXXX
2M
Ans. Application of SR-FF: X1 M for
1) It is used in memory storage devices to store data temporarily such as Application
registers and registers are used in counters, microprocessors and digital signal &
processors. 1 M for
Drawback of SR-FF: Drawback
1) When the inputs of SR-FF are S=0, R=0 or S=1, R=1, the outputs are either
invalid or do not change due to race condition.
c) State the advantages of using tri state logic in combinational logic. 2M

Ans. Advantages of using tri state logic in combinational logic are: 1 M each for
1) It reduces crosstalk in a bus. any two
2) It prevents a bus conflict over a state of signal. Advantages
3) It allows multiple devices to share the same bus without interference.
Note: Any relevant advantages should be considered.

d) Draw excitation table of T FF. 2M
Ans. Excitation table of T FF: 1/2 M for each
I/O
Table: Excitation table of T FF combination
Output Q Input
Present state (Qn) Next state (Qn+1) Tn
0 0 0
0 1 1
1 0 1
1 1 0
e) List any two specifications of IC 0809. 2M

Ans. Specifications of IC 0809: 1 M for each
1) Input voltage range: 0 to 5 V Specification
2) Power consumption: Less than 15 mW (Any two
3) Conversion time:100 µsec Specifications)
4) Power Supply voltage: 5V
5) Resolution: 28
OR
1) Resolution: It is defined as the maximum number of digital output codes.

Resolution = 2n or VFS / 2n-1
2) Conversion time: It is the total time required to convert the analog input
signal into a corresponding digital output.
3) Quantization error: The error due to quantization process is called as
quantization error.
f) Define: Encoder 2M
Ans. Encoder is a combinational circuit which accepts N bit digital input and converts it 2 M for correct
into an M bit another digital word. Definition
g) Name four types of shift register. 2M
Ans. Types of shift register: 1/2 M each
1) Serial Input Serial Output (SISO) type
2) Serial Input Parallel Output (SIPO)
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3) Parallel Input Serial Output (PISO)

XXXX
4) Parallel Input Parallel Output (PIPO) X
5) Bidirectional Shift Register
6) Universal Shift Register
2. Attempt any THREE of the following: 12 M

a) Perform the following subtractions using 2’S compliment method. 4M
i) (1100) – (0011)
ii) (10101) – (11100)
Ans. 1 M to find 2’s

complement
&
1 M for correct
answer (of each
sub question)
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b) Draw the MUX tree for 32:1 MUX using 4:1 MUX only.
XXXX
4M
Ans. X
4 M for correct
diagram
Fig.: 32:1 MUX tree using 4:1 MUX

Note : For MUX 11 at the output, though input values are not written and only
input lines are drawn, marks should be given.
c) Name the basic building block used in CPLD and state their functions. 4M
Ans. The basic building blocks used in CPLD are: 1M for writing
1) PAL – like blocks names of
2) Input /Output (I/O) blocks blocks
3) Interconnecting wires &
Their functions are as below:
1) PAL – like blocks:
• Each PAL like block is made of 16 macrocells. 2 M for
• Inside each microcell there is an AND-OR combination the output function of
of which is applied to an EX-OR gate, flip-flop, multiplexers and PAL-like block
tristate buffers. &
• Every AND-OR combination contains up to about 20 AND gates 1/2 M for
and 1 OR gate. function of I/O
• The OR gate output is connected to the input of a EX-OR gate. block
&
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• The EX-OR gate can invert its input if one end of it is connected to
XXXX
1/2 M for
1. Xfunction of
• It will not invert the OR gate output if one end of it is connected to interconnecting
0. wires
• The EX-OR gate output is stored into a D FF.
• The output of this flip flop along with the output of the EX-OR gate
is applied to the inputs of a 2: 1 multiplexer. A multiplexer will
connect either the FF's output or the EX-OR gate output to the
tristate buffer depending on the state of its select input either 0 or 1.
• The tri-state buffer acts as a switch. Its output is connected to I/O
pin of the IC. This pin of the chip acts as output if the buffer is
enabled and the same pin acts as input pin if the buffer is disabled.
But if the pin is used as input pin, then the macrocell is disabled.
2) Input/output ( I/O) block: The PAL like blocks are connected to the I/O
blocks and to the interconnecting wires.
3) Interconnecting wires: Various blocks of CPLD are interconnected with
each other via interconnecting wires
d) Minimize the following expression using K-map: 4M
f (A, B, C, D) =Ʃm(2, 3, 6, 10, 11, 12, 14, 15)
Ans. Simplification using K-map: 1 M for
drawing k
map,
1M for
representing
function in k
map,
1 M for
grouping &
1M for final
expression
Fig: K-map representation of given function

Note: Any relevant grouping and expression should be considered to minimize
the given expression.
3. Attempt any THREE of the following: 12M

a) Compare TTL and CMOS logic on the basis of:
i) Noise margin
ii) Figure of merit 4M
iii) Speed of operation
iv) Fan in
Page 5 of 23
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Ans.
XXXX
1M for each
Parameters TTL CMOS XParameter
i) Noise margin 0.4Volt 1.45Volt
ii) Figure of merit 100 PJ 0.7 PJ
iii) Speed of
Fast Slow
operation
iv) Fan in low, often high fan-in,
around 2 to 4 allowing them to
inputs. accommodate a
relatively large
number of input
signals.
b) Realize the following logic operations using only NOR gates 4M

i) OR
ii) EX-NOR
Ans. 2M for each
i) OR gate using NOR gate: -
Boolean expression for an OR gate using NOR gate
Q = A+B
ii) EX-NOR gate using NOR gate: -

Boolean expression for an EX-NOR gate using NOR gate
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XXXX
X
Output of EX-NOR.
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XXXX
X
c) Design the IC7490 as mod-B counter and describe its operation. 4M

Ans. Design IC7490 as mod-8 2M for Design
&
A mod-8 counter will count the first step from 0 to 7 and reset at ninth step. 2M for
Operation
For remaining all step, output Y = 0
K-Map
Expression of Y
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XXXX
X
Operation
A mod-8 counter is a circuit that counts from 0 to 7 and then resets to 0. It can be
built using a variety of different integrated circuits (ICs), but one common choice is
the IC 7490.
The IC 7490 is a decade counter, which means that it can count from 0 to 9. However,
it can be configured to work as a mod-8 counter by connecting two of its reset pins
together. When this is done, the counter will count from 0 to 7 and then reset to 0.
Here is an example of how to build a mod-8 counter using the IC 7490:

Connect pins 2 and 3 of the IC 7490 together.
Connect pin 4 of the IC 7490 to VCC.
Connect pin 5 of the IC 7490 to ground.
Connect pin 6 of the IC 7490 to a clock signal.
Connect pins 11, 10, 9, and 8 of the IC 7490 to four LEDs.
Note 1: Consider mod B as mod 8 counter

Note 2: Consider any relevant diagram and description
d) Calculate the analog output of 8 -Bit DAC for digital input 10011100. Assume 4M
Vfullscale =5V.
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Ans.
XXXX
X2M for V R
&
2M for VO
Analog output of 8 -Bit DAC Vo = 3.061 volts
4. Attempt any THREE of the following: 12M

a) Draw the symbol, truth table and logical expression of following gates: 4M
i)EX-OR gate
ii) NAND gate
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Ans. i)EX-OR gate:

XXXX
X 1/2M
Symbol
each,
Truth table 1M
each & Logical
expression 1/2
M each
ii) NAND gate:
b) Draw the full adder circuit's logic diagram, truth table and K-map 4M
simplification.
Ans A full adder is a computational logic circuit that performs addition between three 1M for circuit
bits, the two input bits A and B, and carry Cin. logic diagram,
Full adder circuit's logic diagram: - 1M for Truth
table,
1M for K-map
&
1M for
simplified
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XXXX
Boolean
Xexpression
Full adder Truth table :
K- map simplification :-
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Simplified Boolean Expression:

XXXX
X
c) Draw the binary to gray code converter with the help of truth table and its K- 4M
map simplification.
Ans. Binary to Gray Code converter Truth Table: -
1M for Truth
Binary inputs Gray Output table &
Decimal 2M for K-map
B3 B2 B1 B0 G3 G2 G1 G0 simplification
&
0 0 0 0 0 0 0 0 0 1M for logic
1 0 0 0 1 0 0 0 1 diagram
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
Table: Binary to Gray Code converter Truth Table
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XXXX
X
K - MAP for G3: -
Table.: K map for G3

G3=B3
K - MAP for G2: -

G 2 = B3B 2 + B 3B 2
G2 = B3 XOR B2
Table.: K MAP FOR G2

K MAP FOR G1: -

G = B 2B1 + B 2 B1
B1 XOR B2
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XXXX
K MAP FOR G0: - X

G 0 = B1B 0 + B1B 0
B1 XOR B0
Diagram for Binary to Gray code converter:
d) Describe the working of clocked SR flip-flop with preset and clear. 4M

Ans.
2M for
diagram
&
2M for
working
Fig. : Clocked SR Flip Flop

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Working of clocked SR flip-flop with preset and clear:

XXXX
In the flip-flop when the power is switched ON, the state of the circuit is uncertain. X
It may come to set (Q=1) or reset (Q=0) state.
In many applications it is desired to Initially set or reset the flip-flop l.e. the initial
state of the flip-flop is to be assigned. This is accomplished by using preset (Pr) and
clear (Cr) Inputs.
These inputs may be applied at any time between clock pulses and are not in
synchronism with the clock. An S-R flip-flop with preset and clear is shown in Fig.
If Pr = Cr = 1, then both the circuit operates in accordance with the truth table of S-
R flip-flop given in table.
If Pr = 0 and Cr = 1, the output of G1 (Q) will certainly be 1.
Consequently, all the three inputs to G2 will be 1 which will make Q = 0. Hence
making Pr = 0 sets the flip-flop.
Similarly, if Pr = 1 and Cr = 0 then the flip-flop is reset.
The condition Pr = Cr = 0 must not be used, since this leads to an uncertain state.
Truth Table:
Table: Clocked SR flip-flop with preset and clear
Inputs operation
output
clk Pr Cr performed
1 1 1 Qn-1 Normal SR FF
x 0 1 1 FF is set
x 1 0 0 FF is reset
Note: Consider any relevant diagram and description.
e) Describe the working principle of dual slope type of ADC with neat diagram. 4M
Ans. 2M for
diagram
&
2M for
Working
Fig. : Dual slope type of ADC
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Working :
XXXX
Above Fig. shows the functional block diagram of a Dual-Slope ADC. It consists of X
four major blocks: 1. an integrator, 2. a comparator, 3. a binary counter and 4. a
switch driver, 5.T flip-flop.
This circuit is provided with a single-pole double throw electronic switch. The
initial state of the circuit is such that:
1. The output of the integrator is small and positive, so that the output of the
comparator is low. Thus, the AND gate is disabled.
2. The counter is kept reset, so that Y output of all flip-flops in the counter are
reading
3. The toggle mode flip-flop is kept reset.
The conversion process begins at t=0 with the switch S1 position 0 thereby
connecting the analog voltage Vx to the input of the integrator.
The integrator output is:
This results in high Vcr thus enabling the AND gate and the clock pulses reach the
clock (clk) Input terminal of the counter which was initially clear. The counter counts
from 00…. 00 to 11….. 111 when 2N-1 clock pulses are applied.
At the next clock pulse 2N, the counter is cleared and Q becomes 1. This controls the
state of S1 which now moves to position 1 at T1 thereby connecting -VR to the input
of the Integrator. The output of the Integrator now starts to move in the positive
direction. The counter continues to count until V0 < 0 As soon as V0 goes positive at
T2, Vc goes low enabling the AND gate. The counter will counting in the absence of
the clock pulses. The waveforms of voltages V0 and Vc are shown in below Fig.
Note: Consider any relevant diagram and description.
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5. Attempt any TWO of the following:

XXXX
12M
a) Design 4-bit ripple counter and draw output waveforms. X 6M
Ans.
2M for
diagram,
2M for Truth
Table
&
2M for
waveforms
Since it is 4 bit Ripple up counter , we need to use four Flip Flops .

Initially all the Flip Flops have Zero output QDQCQBQA = 0000
All the Flip Flops are negative edge triggered CLK is applied to the clock input of
FF-A .
Where as Q output of every Flip Flop is applied to the clock input of next Flip Flop.
Truth Table of 4 bit ripple counter:
Clock FF outputs
QD QC QB QA
Initially 0 0 0 0
1 (↓) 0 0 0 1
2 (↓) 0 0 1 0
3 (↓) 0 0 1 1
4 (↓) 0 1 0 0
5 (↓) 0 1 0 1
6 (↓) 0 1 1 0
7 (↓) 0 1 1 1
8 (↓) 1 0 0 0
9 (↓) 1 0 0 1
10 (↓) 1 0 1 0
11 (↓) 1 0 1 1
12 (↓) 1 1 0 0
13 (↓) 1 1 0 1
14 (↓) 1 1 1 0
15 (↓) 1 1 1 1
16 (↓) 0 0 0 0
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Waveforms:
XXXX
X
b) Compare weighted resister DAC with R-2R ladder type DAC (any six points). 6M
Ans. 1 M for each
Weighted Resistor (any six points)
Aspect R-2R Ladder DAC
DAC
Higher precision due to Generally precise, binary-
1) Precision
varied resistor values. weighted structure.
2) Component Higher due to many Lower due to binary-
Complexity unique resistor values. weighted structure.
May exhibit non- Typically, better linearity
3) Non-Linearity linearity due to resistor due to binary-weighted
tolerance. design.
Slower due to complex
Faster due to simpler
4) Conversion Speed voltage division
structure.
process.
Requires precise digital- Suited for direct binary-
5) Digital Inputs
to-analog conversion. weighted digital inputs.
More sensitive to
6) Accuracy vs. More forgiving due to
resistor tolerance
Tolerance binary-weighted structure.
variations.
7) Simplicity Simple. Slightly complicated.
8) Range of register Registers of only two
Wide range is required.
values value are required.
9) Number of registers
One Two.
per bit
Not easy to expand for
10) Ease of expansion Easy to expand.
more no of bits.
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XXXX
c) Convert the following X 6M
i) (ABCD)16 = ( ? ) 10
ii) (101011001111)2 = ( ? )10
iii) (101011001111)2 = ( ? )8
Ans. i) (ABCD)16 = ( ? ) 10 2M for each

conversion and
correct answer.
ii) (101011001111)2 = ( ? )10
iii) (101011001111)2 = ( ? )8
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XXXX
6. Attempt any TWO of the following: X 12M
a) Draw universal shift register and describe its operation. 6M
Ans.
3M for
diagram
&
3M for
Operation
Fig.: Universal Shift Register

Operation:
A shift register which can shift the data in both the directions (shift right or left) as
well as load it parallelly, is called as a Universal Shift Register.
This shift register is capable of performing the following operations:
1)Parallel loading (parallel input parallel output)
2)Left Shifting
3) Right Shifting
The mode control input is connected to Logic 1 for parallel loading operation
whereas it is connected to 0 for serial shifting.
With mode control pin connected to ground, the Universal Shift Register acts as a
Bi- directional register.
For serial left operation, the input is applied to the serial input which goes to AND
gate-1. Whereas for shift right operation , the serial input is applied to D input AND
gate 8
b) Draw the 4-Bit adder circuit using IC 7483 and describe its working with 6M
suitable examples.
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Ans.
XXXX
X
3M for
Diagram
&
3M for
working
Working:
1. Inputs (A0 to A3 and B0 to B3):

• Connect the four input pins (A0 to A3 and B0 to B3) of the IC 7483
to the corresponding bits of the two 4-bit binary numbers you want to
add.
2. Outputs (S0 to S3 and C4):
• The four sum outputs (S0 to S3) represent the result of the addition of
the two input numbers.
• The carry out output (C4) indicates if there's a carry generated beyond
the 4-bit result.
3. Carry Propagation:
• The IC 7483 internally generates carries as needed while adding the
input bits.
• It performs full binary addition, taking into account the input bits and
any carry from the previous stage.
4. Example:
• Let's say we want to add two 4-bit binary numbers: A = 1010 and B
= 0111.
• Connect A0 to A3 with 1010 and B0 to B3 with 0111.
• The resulting sum (S0 to S3) would be 10001 (binary representation
of 17 in decimal).
• The carry out (C4) would be 1, indicating that there's a carry beyond
the 4-bit result
Note: Consider any relevant correct diagram.
c) Draw the circuit diagram of 3-input TTL NAND gate and explain its working. 6M
Ans.
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Circuit Diagram:
XXXX
3M for
Xdiagram
&
3M Working
Fig.: Circuit diagram of 3 input TTL NAND Gate
Circuit Description:
The 3-input TTL NAND gate circuit consists of three input terminals and one output
terminal. Each input terminal is connected through an input resistor, and the output
is taken from the connection point between these resistors. The circuit operates with
a positive power supply voltage (Vcc) and a ground reference (GND).
Working:
1. Input Signals:
• The gate has three input terminals (A, B, and C), each connected
through a resistor.
• Inputs can be at logic level HIGH (typically Vcc, representing a
binary '1') or logic level LOW (typically GND, representing a binary
'0').
2. Voltage Divider Network:
• When any input terminal is at logic level LOW (GND), it pulls the
corresponding node of the voltage divider network to LOW.
• When all input terminals are at logic level HIGH (Vcc), the voltage at
the common node between the resistors is pulled up to HIGH.
3. Transistor Configuration:
• The output transistor configuration of a NAND gate ensures that when
any input is LOW, the base voltage of the transistor(s) is pulled down
to LOW.
• As a result, the transistor(s) conduct and pull the output voltage to
LOW.
• When the transistor Q3 is ON, the output at terminal Y is HIGH. The output
is LOW when the transistor Q4 is turned ON. The first and second states are
the normal operation of TTL. In the third state, both the transistors Q3 and
Q4 are turned OFF, which results in neither LOW nor HIGH output.
Page 23 of 23

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MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION

Important Instructions to examiners:

Ans. The uses of following codes are: 1 M for any

c) State the advantages of using tri state logic in combinational logic. 2M

Note: Any relevant advantages should be considered.

e) List any two specifications of IC 0809. 2M

1) Resolution: It is defined as the maximum number of digital output codes.

3) Parallel Input Serial Output (PISO)

2. Attempt any THREE of the following: 12 M

Ans. 1 M to find 2’s

Fig.: 32:1 MUX tree using 4:1 MUX

Fig: K-map representation of given function

3. Attempt any THREE of the following: 12M

b) Realize the following logic operations using only NOR gates 4M

ii) EX-NOR gate using NOR gate: -

c) Design the IC7490 as mod-B counter and describe its operation. 4M

Here is an example of how to build a mod-8 counter using the IC 7490:

Note 1: Consider mod B as mod 8 counter

Analog output of 8 -Bit DAC Vo = 3.061 volts

4. Attempt any THREE of the following: 12M

Ans. i)EX-OR gate:

ii) NAND gate:

Full adder Truth table :

Simplified Boolean Expression:

Table.: K map for G3

K - MAP for G2: -

Table.: K MAP FOR G2

Table.: K MAP FOR G1

Table.: K MAP FOR G0

Diagram for Binary to Gray code converter:

d) Describe the working of clocked SR flip-flop with preset and clear. 4M

Fig. : Clocked SR Flip Flop

Working of clocked SR flip-flop with preset and clear:

Table: Clocked SR flip-flop with preset and clear

Note: Consider any relevant diagram and description.

Fig. : Dual slope type of ADC

Note: Consider any relevant diagram and description.

5. Attempt any TWO of the following:

Since it is 4 bit Ripple up counter , we need to use four Flip Flops .

Truth Table of 4 bit ripple counter:

Ans. i) (ABCD)16 = ( ? ) 10 2M for each

ii) (101011001111)2 = ( ? )10

Fig.: Universal Shift Register

1. Inputs (A0 to A3 and B0 to B3):

Note: Consider any relevant correct diagram.

Fig.: Circuit diagram of 3 input TTL NAND Gate

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