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    Fifo &dpram

    Uploaded by

    Tejal Adake

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd

    Fifo &dpram

    Uploaded by

    Tejal Adake
    6 views2 pages

    Original Title

    fifo &dpram

    Copyright

    © © All Rights Reserved

    Available Formats

    TXT, PDF, TXT or read online from Scribd

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    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    6 views2 pages

    Fifo &dpram

    Uploaded by

    Tejal Adake

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    of 2

    dp_ram

    module dp_design #(parameter data_bits=3,addr_bits=3,depth=15,width=3)(input


    w_clk,r_clk,wr_en,rd_en,rst,input [data_bits:0]data_in,input
    [addr_bits:0]wr_addr,rd_addr,output reg [data_bits:0]data_out);
    reg [width:0]mem[0:depth];

    always@(posedge w_clk or negedge rst)


    begin
    if(rst) begin
    mem[wr_addr] <= 0;
    end
    else begin
    if(wr_en)
    mem[wr_addr] <= data_in;
    else;
    end
    end

    always@(posedge r_clk or negedge rst)


    begin
    if(rst) begin
    data_out <= 0;
    mem[rd_addr] <= 0;
    end
    else begin
    if(rd_en)
    data_out <= mem[rd_addr];
    else;
    end
    end

    endmodule

    fifo code

    module fifo #(parameter bits=15,count=5,depth=32)(input clk,reset,wr_en,rd_en,input


    [bits:0] wdata,output reg [bits:0] rdata,output empty,full,overflow,underflow);

    reg [count-1:0]wptr;
    reg [count-1:0]rptr;
    reg [bits:0]ram[depth-1:0];
    reg [count-1:0]count;

    assign empty=(count==0);
    assign full=(count==depth);
    assign overflow = full && wr_en;
    assign underflow = empty && rd_en;

    always@(posedge clk or posedge reset) begin


    if(reset) begin
    wptr <= 0;
    rptr <= 0;
    end
    else begin
    wptr <= ((wr_en && !full)||(wr_en && rd_en)) ? wptr+1:wptr;
    rptr <= ((rd_en && !empty)||(wr_en && rd_en)) ? rptr+1:rptr;
    end
    end

    always@(posedge clk) begin :write


    if(wr_en && !full)
    ram[wptr] <= wdata;
    else if(wr_en && rd_en)
    ram[wptr] <= wdata;
    end

    always@(posedge clk) begin :read


    if(rd_en && !empty)
    rdata<=ram[rptr];
    else if(wr_en && rd_en)
    rdata<=ram[rptr];
    end

    always@(posedge clk or posedge reset) begin : counter


    if(reset)
    count <= 0;
    else
    case({rd_en,wr_en})
    2'b10 : count <= (count==0) ? count : count-1;
    2'b01 : count <= (count==32) ? count : count+1;
    default : count <= count;
    endcase
    end

    endmodule

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