Shukla 2020

CHAPTER 13
Design of array multiplier circuit

using reversible logic approach with
optimized performance parameters
Vandana
1
Shukla1, O.P. Singh1, G.R. Mishra1 and R.K. Tiwari2
Amity School of Engineering & Technology, Amity University, Lucknow, India
2
Department of Physics and Electronics, Dr. R. M. L. Avadh University, Faizabad, India
13.1 Introduction
Digital systems are demanding low-loss processing circuits in today’s time. Among
arithmetic processing circuits, multipliers are considered as the performance defining
component. Here, in this paper, an Array multiplier circuit is designed for the
multiplication of two 4-bit binary numbers.
Initially, AOI logic was mainly used to design any digital circuit. Here, AOI stands
for AND, OR and Inverter gates. So, earlier basic logic gates were the fundamental
design entities for any digital design. These gates generally tend to cause power loss/
heat loss due to information loss during the execution of any signal processing step.
Low-loss digital circuits are designed using reversible logic technique. Reversible
logic aims to design any digital design with Reversible logic design units. This design
approach is extensively applicable in the areas of Low Power CMOS Design, Nano
Technology, Optical Computing, etc.
Earlier, in the year 1961, R. Landauer has proposed that k.T. ln 2 joules of energy
is dissipated per lost bit, for every step of operation [1]. Further, after some time, in
the year 1965, famous scientist G. E. Moore has given the law for increase in the den-
sity of design entities on unit chip area [2]. This increase in the component density is
observed as two folds in approximately two years time.
Moreover, both these concepts lead to the many fold increase in the quantity of
heat dissipation from given chip area for considered time span. Further, in the year
1973, it was proposed by C. H. Bennett that ideally lossless digital circuits may be
designed using reversible logic technology [3].
Based on this concept of reversible design approach, various researchers have
already proposed and applied different reversible design units for the designing of
numerous combinational and sequential digital circuits [48]. Multiplier circuits are
very vital component of any processing circuit. Here, a novel approach is proposed to
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design 4-bit array multiplier using available reversible logic gates of different sizes. This
design is further simulated and synthesized on ModelSim software and Xilinx tool.
This design is also compared with earlier reversible designs of array multiplier circuits
in terms of selected performance parameters. After comparison, it is inferred that the
proposed design is most optimized approach.
This paper is basically structured in six sections. Sections 13.1 and 13.2 presents
introduction of the work proposed in this paper and array multiplier design basics
respectively. After that, reversible logic basic concepts and proposed design for array
multiplier circuit using reversible approach are discussed in Sections 13.3 and 13.4
respectively. Result of proposed design is described in Section 13.5 along with the
analysis. The paper is concluded in Section 13.6 at the end.
13.2 Array multiplier design

Binary multiplication using array multipliers require only combinational digital
components [9,10]. As shown in Fig. 13.1 below, here we multiply two 4-bit binary
numbers denoted as A (A3A2A1A0) and B (B3B2B1B0) to generate the product
P (P7P6P5P4P3P2P1P0).
As shown in Fig. 13.1, four partial product bits (PP3, PP2, PP1 and PP0) requires
about sixteen multiplication steps (AND operations). Moreover, final product of num-
bers is generated by calculating sum of these shifted partial product bits. This sum is
calculated using three different 4- bit Adder circuits. Fig. 13.2 clearly shows the
required components and their connections to perform 4-bit multiplication shown in
Fig. 13.1.
Present paper proposes the reversible design of this array multiplier circuit for two
4-bit binary numbers with optimized performance parameters.
13.3 Reversible logic basics

Reversible logic fundamental concepts are basically described here in two sections i.e.
reversible design units and reversible design approach. These concepts are described as
follows:
Figure 13.1 Multiplication of 4-bit numbers A and B.

Design of array multiplier circuit using reversible logic approach with optimized performance parameters 117
Figure 13.2 4-bit array multiplier circuit.
Figure 13.3 Block diagram of reversible logic gate.
13.3.1 Reversible design units

Reversible logic gates are considered as the design units/entities of reversible circuits.
As shown in Fig. 13.3, Reversible logic gate is a digital logic gate with equal input
and output signal lines along with some other characteristics such as one to one map-
ping between input and output lines, any output line is high for a total of half of the
input combinations possible and low fan-out.
Till now, numerous reversible logic gates of different sizes have been proposed in
literature [1114]. Some of these gates are shown in Table 13.1 below.
Table 13.1 Example of reversible logic gates.

Block diagram Output equations QC
P=A; 1
Q=A"B;
P=A; 4
Q=A.B"C;
R=A.D"C;
S=A0 . B"C"D;
P=A; 6
Q=A"B"C;
R=A"B"D;
S=(A"D"B). (A"D"C) "(A"D);
These gates are generally utilized in different combinations to design the aimed
digital circuit using reversible approach.
13.3.2 Reversible design approach

In this approach any digital design available in AOI logic is redesigned utilizing only
reversible design units. The designed digital circuit must have fewer number of revers-
ible design units, minimum garbage outputs, low quantum cost and no feedback con-
nection [48].
Here, garbage output is defined as the surplus signal generated from the designed
circuit, apart from the required outputs. Along with this, other performance parameter
considered in case of reversible circuit design is quantum cost. It is defined as the total
cost of 1 3 1 and 2 3 2 size basic reversible/quantum gates required to design the
overall reversible design. Here, quantum cost of 1 3 1 and 2 3 2 size reversible gates
are 0 and 1 respectively.
13.4 Proposed reversible array multiplier

Here, we present a design approach for 4-bit array multiplier circuit with reversible
approach. According to multiplier circuit shown in Fig. 13.2, we require some AND
operation and three 4-bit adder circuits. These reversible sub-circuits are explained
below:
Figure 13.4 AND operation for ith partial product.
Figure 13.5 4-Bit adder circuit.
13.4.1 Reversible and operation

In this array multiplier circuit all bits of multiplicand are required to be multiplied
with all four bits of multiplier to generate bits of partial products. Here, we have uti-
lized BME gates to perform this operation. As shown in Fig. 13.4, two BME gates are
required to be connected in cascade for generating ith partial product.
Here output bits are taken from second and third output bits of both BME gates.
this circuit generates three garbage outputs with a total of 12 quantum cost.
Moreover, for other three partial products, this circuit is repeated in the aimed array
multiplier circuit design.
13.4.2 4-Bit addition operation

Fig. 13.5 clearly describes this aimed 4-bit adder circuit design using only WG gates.
Here, we cascade four WG gates to perform addition of two 4-bit binary numbers.
This circuit generates a total of 5 garbage output signals with 24 quantum cost.
Above mentioned circuits are connected according to 4-bit array multiplier circuit
shown in Fig. 13.2.
Table 13.2 Comparison table.

Design TG GO QC
Proposed design 20 25 120
Existing design 1 [15] 20 27 127
Figure 13.6 Comparison chart.
13.5 Result and analysis

The proposed design for array multiplier discussed in Section 13.4 generates a total of
27 garbage outputs with 120 quantum cost. This design requires only 20 reversible
logic gates, which include 8 BME gates and 12 WG gates.
Comparison of proposed design with existing designs is shown in Table 13.2
below. Here, total reversible logic units utilized in the design, garbage signals gener-
ated and quantum cost are the parameters used for comparison.
Further, Fig. 13.6 provides the chart for comparison of these parameters of pro-
posed design with existing ones.
Figure 13.7 Simulated waveforms.
Figure 13.8 Synthesized circuit.
It is clearly visible from comparison chart shown in Fig. 13.6, that our proposed design
provides most optimized approach for 4-bit array multiplier design using reversible design
units. Here, ModelSim tool is used for simulation of the circuit along with Xilinx Spartan
3E with Device XC3S500E with 200 MHz frequency for synthesis. Simulated waveform
and synthesized circuit for proposed design are shown in Figs. 13.7 and 13.8 respectively.
13.6 Conclusion
Multiplier circuits are among the most vital component of any digital processing sys-
tem. Here, in this paper, a 4-bit array multiplier circuit design is proposed utilizing
available reversible design units. This design utilizes a total of 20 reversible logic gates
with 25 garbage output signals and 120 quantum cost. Moreover, proposed design is
also compared with the existing designs in terms of selected parameters and concluded
as the most optimized design. Simulated output waveform and synthesized circuit for
proposed design are also presented here. This design may be further applied to pro-
duce other low power digital designs.
References
[1] R. Landauer, Irreversibility and heat generation in the computational process, IBM J. Res. Dev. 5
(1961) 183191.
[2] G.E. Moore, Cramming more compounds onto integrated circuits, Electronics 38 (1965) 8.
[3] C.H. Bennett, Logical reversibililty of computation, IBM J. Res. Dev. (1973) 525532.
[4] S.K. Noor Mahammad, S.K. Sastry Hari, S. Shroff, V. Kamakoti, Constructing online
testable circuits using reversible logic, Proceedings of the 10th IEEE VLSI Design and Test
Symposium (VDAT), IEEE, Goa, India, 2006, pp. 373383.
[5] H. Thapliyal, A.P. Vinod, Design of reversible sequential elements with feasibility of transistor
implementation, Proceedings of the 2007 IEEE International Symposium on Circuits and Systems,
IEEE, New Orleans, LA, 2007, pp. 625628.
[6] P. Singla, N.K. Malik, a cost - effective design of reversible programmable logic array, Int. J.
Comput. Appl. 41 (2012) 15.
[7] T. Toffoli, Reversible computing. Tech memo MIT/LCS/ TM-151, MIT Lab for Computer
Science, 1980.
[8] V. Shukla, O.P. Singh, G.R. Mishra, An efficient approach for the reversible realization of 2:4
decoder circuit, J. Int. Acad. Phys. Sci. 21 (2017) 4.
[9] W.I. Fletcher, An engineering approach to digital design, PHI Learning Private Limited, (India),
1980.
[10] T.L. Floyd, Digital Fundamentals, Pearson Education, Inc, 2009.
[11] H. Thapliyal, M.B. Srinivas, A New Reversible TSG Gate and Its Application For Designing
Efficient Adder Circuits, 7th International Symposium on Representations and Methodology of
Future Computing Technologies (RM 2005), Tokyo, Japan, 2005.
[12] M. Haghparast, K. Navi, A novel fault tolerant reversible gate for nanotechnology based systems,
Am. J. Appl. Sci. 5 (5) (2008) 519523.
[13] H. Thapliyal, N. Ranganathan, Design of efficient reversible binary subtractors based on a new
reversible gate, IEEE Comput. Soc. Annu. Symp. VLSI (2009) 229234.
[14] L. Ni, Z. Guan, X. Dai, W. Li, Using new designed NLG gate for the realization of four- bit
reversible numerical comparator, International Conference on Educational and Network
Technology (ICENT-2010), IEEE, 2010, pp. 254258.
[15] Y.R. Babu, Y. Syamala, Implementation and testing of multipliers using reversible logic, Proceeding
of International Conference on Advances in Recent Technologies in Communication and
Computing 2011, IET, 2011, pp. 171175.
[16] B.P. Sharath, K.V. Suhas, A new approach to the design and implementation of multipliers using
reversible logic, Int. J. Eng. Sci. Invent. 2 (10) (2013) 2023.
[17] A. Baneriee, A. Pathak, Reversible multiplier circuit, Proceeding of 3rd International Conference
on Emerging Trends in Engineering and Technology, IEEE, Goa, India, 2010, pp. 781786.
[18] M. Haghparast, M. Mohammadi, K. Navi, M. Eshghi, Optimized reversible multiplier circuit, J.

Circuits Syst. Comput. 18 (2009) 113.
[19] M.S. Islam, M.M. Rahman, Z. Begum, M.Z. Hafiz, Low cost quantum realization of reversible
multiplier circuit, Inf. Technol. J. 8 (2009) 208213.
[20] M. Shams, M. Haghparast, K. Navi, Novel reversible multiplier circuit in nanotechnology, World
Appl. Sci. J. 3 (2008) 806813.
[21] H. Thapliyal, M.B. Shrinivas, Novel reversible multiplier architecture using reversible TSG gate,
IEEE Int. Conf. Comput. Syst. Appl. (2006) 100103.

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CHAPTER 13

Design of array multiplier circuit

13.2 Array multiplier design

13.3 Reversible logic basics

Figure 13.1 Multiplication of 4-bit numbers A and B.

Figure 13.2 4-bit array multiplier circuit.

Figure 13.3 Block diagram of reversible logic gate.

13.3.1 Reversible design units

Table 13.1 Example of reversible logic gates.

13.3.2 Reversible design approach

13.4 Proposed reversible array multiplier

Figure 13.4 AND operation for ith partial product.

Figure 13.5 4-Bit adder circuit.

13.4.1 Reversible and operation

13.4.2 4-Bit addition operation

Table 13.2 Comparison table.

Figure 13.6 Comparison chart.

13.5 Result and analysis

Figure 13.7 Simulated waveforms.

Figure 13.8 Synthesized circuit.

[18] M. Haghparast, M. Mohammadi, K. Navi, M. Eshghi, Optimized reversible multiplier circuit, J.

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