TEACHING PLAN

A. TRIMESTER:

B. INFORMATION ABOUT THE COURSE:

1. Name of Course/Module Computer Architecture & Organzation

2. Course Code CSN 6114
3. Name of Course Coordinator(s) Assoc. Prof. Dr. Tan Saw Chin

C. DETAILS OF TEACHING STAFF (INCLUDING THE COURSE COORDINATOR):

Name Room Number Email Address Tel. No.

Goh Hui Ngo 3016 [email protected] 03-8312 5223

Kannan RamaKrishna 3003 [email protected] 03-8312 5405
Khairi Shazwa 2014 [email protected] 03-8312 5674
Liana Ameerah 3013 [email protected] 03-8312 5618
Lee Fong Yee 2018 [email protected] 03-8312 5119
Ng Hu 3010 [email protected] 03-8312 5411
Tan Saw Chin 2101 [email protected] 03-8312 5346

D. The detailed information about the course is provided in the attached Course Information document.
The “Course Information” document is the property of Multimedia University (“MMU”). It contains
proprietary and confidential information and is meant for internal use only. Any sharing or
distribution of these documents (Course Information and Teaching Plan) with any external party is
strictly prohibited unless prior consent or approval is obtained from MMU’s authorised personnel.

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 E. WEEKLY LESSON PLAN AND ASSESSMENT DUE DATES
IMPORTANT NOTES
ASSESSMENT METHOD & Please state:
WEEK TOPICS/ACTIVITIES
WEIGHTAGE i. Replacement classes (if applicable)
ii. Public holidays and MMU major events
1. Introduction to Digital Logic and LabA0(Simulator:circuitverse) * 28 March (Thu) - Nuzul Quran (Selangor)
Boolean algebra. & Lab coursework distribution
Digital and analog systems, Logic gates, (60%)
Boolean algebra, Simplification using
boolean algebra, Boolean analysis of logic
circuit
2. Combinational Logic Circuits LabA1(2%)
Standard forms of boolean expressions,
Simplification using Karnaugh map.
3. Combinational Logic Circuits LabA2(2%) * 10 & 11 April (Wed & Thu) - Eidul-Fitri [Online T&L
Design of combinational logic circuits, Week]
Standard combinational logic circuits
4. Sequential Logic Circuits LabA3(2%) Assignment 1(group: 4 Members): Released(10%)
Latches and flip-flops, Asynchronous and
synchronous counters.
5. Sequential Logic Circuits LabA4(2%)
Basic functions and types of shift registers,
Shift register counters
6. Number Systems, Codes and Machine LabA5(2%) *1 May (Wed) – Labour Day
Level Representation of Data
Number system conversions and
arithmetic, Numeric and alphanumeric
codes.
7. Number Systems, Codes and Machine Assignment 1 Submission (due date: 12 May 2024
Level Representation of Data 11:59 PM)
Integer representation and arithmetic,
Floating-point representation and
arithmetic
8. Computer Evolution, Performance, and Lab 1: ARM
System Buses Mid-Term Test 1 (10%): 14 May 2024 (9pm-10pm)
Basic concepts and computer evolution, Online (Topic: Week1-Week5)
Introduction to embedded systems and the
Internet of Things (IoT), Performance
issues, Computer components and

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 functions, Instruction cycle and interrupts,
Bus interconnection structure, Case
Studies: Quick path interconnect and
peripheral component interconnect
approaches.
9. Structure and Function of Assignment 2(Group: 4 Members): Released (10%)
Central Processing Unit and Lab 2: ARM
Operation of Control Unit
Internal structure of CPU, Organization of *22 May (Wed) - Wesak Day
registers, Instruction cycle with indirect
stage, Instruction pipelining: strategy,
performance, source, data and control
hazards.

10. Structure and Function of LabB1(2.5%)

Central Processing Unit and
Operation of Control Unit
Control unit operation
Case Studies: register organization and
interrupt processing of Intel x86 and ARM
processors.
11. Instruction Set Architecture and Design LabB2(2.5%) *3 June ( Mon) - Agong's Birthday
Characteristics and functions of instruction
sets, types of operands, types of
operations, Addressing modes,
Instruction formats, Case Studies: Intel x86
and ARM data and operation types,
addressing modes, and instruction formats.
Assembly language programming with Intel
x86 / ARM.
12. Memory System Organization and LabB3(2.5%)
Architecture
Characteristics of memory systems,
Memory hierarchy, Cache memory:
principles, mapping functions, replacement
algorithms, write policy, and multilevel
caches, Semiconductor main memory:
types and characteristics
13. Input / Output Interfacing Strategies LabB4(2.5%) *17 June (Mon) - Hari Raya Korban

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 Structure and function of I/O modules, Data
transfer techniques: programmed I/O, Mid-Term Test 2 (10%): 19June 2024 (9pm-10pm)
interrupt-driven I/O, direct memory access, Online (Topic: Week8-Week11 , Lab 1 & 2: ARM,
Direct cache access strategies, I/O LabB1)
Channels and Processors, Case Studies:
USB, Firewire, SCSI, Thunderbolt,
InfiniBand.
14. Multiprocessing, Alternative Assignment 2 Submission (due date: 30 June 2024
Architectures, and Performance 11:59 PM)
Enhancements
Flynn’s taxonomy: Multiple Processor
Organizations, Cache Coherence problem,
Multi-threading, Multi-Core Computing,
General-Purpose Graphic Processing Units
(GPUs), Instruction Level Parallelism and
Superscalar processors

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 Prepared by: Course Coordinator

Name Date 7/3/2024

Assoc. Prof. Dr. Tan Saw Chin
Signature & Official Stamp

Date Verified by AIC Meeting :

Work Distribution:

1. NgHu: Lecture Notes & Tutorial: (upload to MMLS on 18-21 March 2024)
2. SCTan: Assignment 1 & Assignment 2 (announce on MMLS based on the date in lecture plan)
3. Mid-Term Test 1(3 structured question): Goh(Compile)) & Khairi (26 April 2024)
4. Mid-Term Test 2(3 structured question): Kannan (Compile) & Liana (27 May 2024)
5. Final & Supplementary Examination (2 questions: each question 10 marks): 12 April 2024
Q1. Week 1,2,3 (Goh)
Q2. Week 4,5 (Khairi)
Q3. Week 6,7, 8 (Kannan/Liana)
Q4. Week 9,10,11 (NgHu)
Q5. Week 12, 13, Lab ARM (SCTan)

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